On 4/10/24 18:30, Philippe Mathieu-Daudé wrote:
The M68K architecture uses big endianness. Directly use
the big-endian LD/ST API.
Mechanical change using:
$ end=be; \
for acc in uw w l q tul; do \
sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \
-e "s/st${acc}_p(/st$
On Fri, 4 Oct 2024 at 17:22, Philippe Mathieu-Daudé wrote:
>
> Introduce the CPUClass::is_big_endian() handler and its
> common default.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/hw/core/cpu.h | 3 ++-
> hw/core/cpu-common.c | 7 +++
> 2 files changed, 9 insertions(+), 1 del
Add the VIRTIO_GPU_F_RESOURCE_UUID feature to enable the assignment
of resources UUIDs for export to other virtio devices.
Signed-off-by: Dorinda Bassey
---
hw/display/vhost-user-gpu.c| 4
hw/display/virtio-gpu-base.c | 3 +++
include/hw/virtio/virtio-gpu.h | 3 +++
3 files changed, 1
On 4/10/24 18:41, Peter Maydell wrote:
On Fri, 4 Oct 2024 at 17:22, Philippe Mathieu-Daudé wrote:
Introduce the CPUClass::is_big_endian() handler and its
common default.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 3 ++-
hw/core/cpu-common.c | 7 +++
2 files ch
On Fri, 4 Oct 2024 at 17:54, Philippe Mathieu-Daudé wrote:
>
> On 4/10/24 18:41, Peter Maydell wrote:
> > On Fri, 4 Oct 2024 at 17:22, Philippe Mathieu-Daudé
> > wrote:
> >>
> >> Introduce the CPUClass::is_big_endian() handler and its
> >> common default.
> >>
> >> Signed-off-by: Philippe Mathie
On 02.10.24 17:41, Vladimir Sementsov-Ogievskiy wrote:
On 26.06.24 14:53, Vladimir Sementsov-Ogievskiy wrote:
diff --git a/qapi/block-core.json b/qapi/block-core.json
index df5e07debd..0a6f08a6e0 100644
--- a/qapi/block-core.json
+++ b/qapi/block-core.json
@@ -6148,3 +6148,91 @@
##
{ 'struct
On Fri, Oct 4, 2024 at 6:00 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 10/4/24 5:33 AM, Andrew Jones wrote:
> > On Thu, Oct 03, 2024 at 11:36:00AM GMT, Tomasz Jeznach wrote:
> >> On Thu, Oct 3, 2024 at 6:06 AM Daniel Henrique Barboza
> >> wrote:
> >>>
> >>>
> >>>
> >>> On 10/3/24 6:26 AM, Andre
Michael Tokarev writes:
> currently, if an oss-fuzz fails, the script does just `exit 1`
> without any additional output, and looking at the build log in
> the gitlab ci it is not clear what actually failed, without
> looking at build-oss-fuzz script and seeing this `exit 1`.
>
> Print easily rec
On Fri, Oct 4, 2024 at 2:45 PM Jonah Palmer wrote:
>
> Implements the IOVA->GPA tree for handling mapping, unmapping, and
> translations for guest memory regions.
>
> When the guest has overlapping memory regions, an HVA to IOVA translation
> may return an incorrect IOVA when searching the IOVA->H
From: "Dr. David Alan Gilbert"
net_hub_port_find is unused since 2018's commit
af1a5c3eb4 ("net: Remove the deprecated "vlan" parameter")
qemu_receive_packet_iov is unused since commit
ffbd2dbd8e ("e1000e: Perform software segmentation for loopback")
in turn it was the last user of qemu_net
From: "Dr. David Alan Gilbert"
serial_set_frequnecy has been unused since it was added in 2009:
038eaf82c8 ("serial: Add interface to set reference oscillator frequency")
It looks like the 'baudbase' is now a property anyway so the wrapper
isn't needed.
Remove it.
Signed-off-by: Dr. David Al
From: Akihiko Odaki
Commit 2523baf7fb4d ("qemu-keymap: Make references to allocations
static") made references to allocations static to ensure LeakSanitizer
can track them. This trick unfortunately did not work with gcc version
14.0.1; that compiler is clever enough to know that the value of the
From: "Dr. David Alan Gilbert"
net_rx_pkt_get_l3_hdr_offset and net_rx_pkt_get_iovec_len haven't
been used since they were added.
Remove them.
Signed-off-by: Dr. David Alan Gilbert
Reviewed-by: Thomas Huth
Reviewed-by: Michael Tokarev
Signed-off-by: Michael Tokarev
(Mjt: also removed net_rx
From: "Dr. David Alan Gilbert"
handle_vm86_fault has been unused since:
1ade5b2fed ("linux-user/i386: Split out maybe_handle_vm86_trap")
Remove it, and it's local macros.
Signed-off-by: Dr. David Alan Gilbert
Reviewed-by: Thomas Huth
Reviewed-by: Michael Tokarev
Signed-off-by: Michael Toka
From: Philippe Mathieu-Daudé
Nothing in fw_cfg.c requires target-specific knowledge,
build it once for the 4 MIPS variants.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Michael Tokarev
Signed-off-by: Michael Tokarev
---
hw/mips/meson.build | 2 +-
1 file chang
From: "Dr. David Alan Gilbert"
vhost_dev_load_inflight and vhost_dev_save_inflight have been
unused since they were added in 2019 by:
5ad204bf2a ("vhost-user: Support transferring inflight buffer between qemu and
backend")
Remove them, and their helper vhost_dev_resize_inflight.
Signed-off-by
From: "Dr. David Alan Gilbert"
mch_mcfg_base has been unused since it was added by
6f1426ab0f ("ich9: APIs for pc guest info")
back in 2013.
Remove it.
Signed-off-by: Dr. David Alan Gilbert
Reviewed-by: Bernhard Beschow
Reviewed-by: Thomas Huth
Reviewed-by: Michael Tokarev
Signed-off-by:
From: "Dr. David Alan Gilbert"
remote_iohub_finalize has never been used.
Remove it.
Signed-off-by: Dr. David Alan Gilbert
Reviewed-by: Jagannathan Raman
Reviewed-by: Thomas Huth
Reviewed-by: Michael Tokarev
Signed-off-by: Michael Tokarev
---
hw/remote/iohub.c | 13 -
The following changes since commit 423be09ab9492735924e73a2d36069784441ebc6:
Merge tag 'warn-pull-request' of https://gitlab.com/marcandre.lureau/qemu
into staging (2024-10-03 10:32:54 +0100)
are available in the Git repository at:
https://gitlab.com/mjt0k/qemu.git tags/pull-trivial-patches
From: "Dr. David Alan Gilbert"
xen_be_copy_grant_refs is unused since 2019's
19f87870ba ("xen: remove the legacy 'xen_disk' backend")
xen_config_dev_console is unused since 2018's
6d7c06c213 ("Remove broken Xen PV domain builder")
Remove them.
Signed-off-by: Dr. David Alan Gilbert
Acked-b
From: "Dr. David Alan Gilbert"
rocker_fp_ports hasn't been used since it was added back in 2015.
Remove it.
Signed-off-by: Dr. David Alan Gilbert
Reviewed-by: Thomas Huth
Reviewed-by: Michael Tokarev
Signed-off-by: Michael Tokarev
---
hw/net/rocker/rocker.c | 5 -
hw/net/rocker/rocker.h
From: "Dr. David Alan Gilbert"
blk_by_public last use was removed in 2017 by
c61791fc23 ("block: add aio_context field in ThrottleGroupMember")
blk_activate last use was removed earlier this year by
eef0bae3a7 ("migration: Remove block migration")
blk_add_insert_bs_notifier, blk_op_block_al
From: "Dr. David Alan Gilbert"
cursor_get_mono_image has been unused since 2018's
0015ca5cba ("ui: remove support for SDL1.2 in favour of SDL2")
Remove it.
Signed-off-by: Dr. David Alan Gilbert
Reviewed-by: Marc-André Lureau
Reviewed-by: Thomas Huth
Reviewed-by: Michael Tokarev
Signed-off
From: "Dr. David Alan Gilbert"
pcie_chassis_find_slot has been unused since it was added.
Remove it.
Signed-off-by: Dr. David Alan Gilbert
Reviewed-by: Thomas Huth
Reviewed-by: Michael Tokarev
Signed-off-by: Michael Tokarev
---
hw/pci/pcie_port.c | 10 --
include/hw/pci/pci
From: Bernhard Beschow
Signed-off-by: Bernhard Beschow
Reviewed-by: Cédric Le Goater
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Michael Tokarev
---
MAINTAINERS | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/MAINTAINERS
From: "Dr. David Alan Gilbert"
replay_disable_events has been unused since 2019's
c8aa7895eb ("replay: don't drain/flush bdrv queue while RR is working")
Remove it.
Signed-off-by: Dr. David Alan Gilbert
Reviewed-by: Pavel Dovgalyuk
Reviewed-by: Thomas Huth
Reviewed-by: Michael Tokarev
Sig
From: Laurent Vivier
The file has been removed by c52e40596834
("linux-user,loongarch: move to syscalltbl file").
Signed-off-by: Laurent Vivier
Signed-off-by: Michael Tokarev
---
MAINTAINERS | 1 -
1 file changed, 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4ee2699543..d013db1
From: "Dr. David Alan Gilbert"
fw_cfg_init_io has been unused since
918a7f706b ("i386: load kernel on xen using DMA")
Remove it.
Signed-off-by: Dr. David Alan Gilbert
Reviewed-by: Igor Mammedov
Reviewed-by: Thomas Huth
Reviewed-by: Michael Tokarev
Signed-off-by: Michael Tokarev
---
hw/n
From: Thomas Huth
The _check() function is supposed to check whether the hash of the
downloaded file matches the expected one. Unfortunately, during the
last rework of this function, the check was accidentally turned into
returning the hash value itself instead of a True/False value,
effectively
From: Philippe Mathieu-Daudé
We were including the "exec/tswap.h" header to get
target_words_bigendian() declaration, but since commit a276ec8e26
("hw/audio/virtio-snd: Always use little endian audio format")
removed this method call, we don't need this header anymore.
Signed-off-by: Philippe Ma
From: Peter Maydell
Accessing another device in a post_load hook is a bad idea, because
the order of device save/restore is not fixed, and so this
cross-device access makes the save/restore non-deterministic.
We previously only flagged up this requirement in the
record-and-replay developer docs;
From: Thomas Huth
The cris target has recently been removed (see commit 44e4075bf4 -
"target/cris: Remove the deprecated CRIS target"), but apparently this
line has been forgotten. So clean it up now.
Signed-off-by: Thomas Huth
Reviewed-by: Alex Bennée
Reviewed-by: Michael Tokarev
Signed-off-
Paolo Bonzini writes:
> From: Artyom Kunakovsky
>
> The point of CPU_CFLAGS is really just to select the appropriate multilib,
> for example for library linking tests, and -mcx16 is not needed for
> that purpose.
>
> Furthermore, if -mcx16 is part of QEMU's choice of a basic x86_64
> instruction
On Thu, 3 Oct 2024 at 19:57, Edgar E. Iglesias wrote:
>
> From: "Edgar E. Iglesias"
>
> The following changes since commit 423be09ab9492735924e73a2d36069784441ebc6:
>
> Merge tag 'warn-pull-request' of https://gitlab.com/marcandre.lureau/qemu
> into staging (2024-10-03 10:32:54 +0100)
>
> are
From: Tomasz Jeznach
Add PCIe Address Translation Services (ATS) capabilities to the IOMMU.
This will add support for ATS translation requests in Fault/Event
queues, Page-request queue and IOATC invalidations.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Fr
From: Tomasz Jeznach
The RISC-V IOMMU specification is now ratified as-per the RISC-V
international process. The latest frozen specifcation can be found at:
https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf
Add the foundation of the device emulation for RISC-V
From: Marc-André Lureau
Since commit e99441a3793b5 ("ui/curses: Do not use console_select()")
qemu_text_console_put_keysym() no longer checks for NULL console
argument, which leads to a later crash:
Thread 1 "qemu-system-x86" received signal SIGSEGV, Segmentation fault.
0x559ee186 in qem
Introduce CPUClass::is_big_endian() handler and expose
the cpu_is_big_endian() method. This will be useful later
when endianness will be propagated in the slow paths,
allowing removal of various TARGET_BIG_ENDIAN uses.
Philippe Mathieu-Daudé (8):
exec/tswap: Massage target_needs_bswap() definiti
On 4/10/24 01:41, Philippe Mathieu-Daudé wrote:
The x86 architecture uses little endianness. Directly use
the little-endian LD/ST API.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/multiboot.c | 36 ++--
hw/i386/x86-common.c | 26 +
Introduce the CPUClass::is_big_endian() handler and its
common default.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 3 ++-
hw/core/cpu-common.c | 7 +++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 04
Signed-off-by: Philippe Mathieu-Daudé
---
target/microblaze/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 135947ee800..93c0c6d36c8 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -119,6 +119,13 @@ st
Invert target_needs_bswap() comparison to match the
COMPILING_PER_TARGET definition (2 lines upper).
Signed-off-by: Philippe Mathieu-Daudé
---
include/exec/tswap.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/exec/tswap.h b/include/exec/tswap.h
index b7a41913475..e
To test the RISC-V IOMMU emulation we'll use its PCI representation.
Create a new 'riscv-iommu-pci' libqos device that will be present with
CONFIG_RISCV_IOMMU. This config is only available for RISC-V, so this
device will only be consumed by the RISC-V libqos machine.
Start with basic tests: a PC
From: Tomasz Jeznach
The RISC-V IOMMU can be modelled as a PCIe device following the
guidelines of the RISC-V IOMMU spec, chapter 7.1, "Integrating an IOMMU
as a PCIe device".
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Reviewed-by: Alistair F
Add a simple guideline to use the existing RISC-V IOMMU support we just
added.
This doc will be updated once we add the riscv-iommu-sys device.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
docs/specs/index.rst | 1 +
docs/specs/riscv-iommu.rst | 90 ++
From: Tomasz Jeznach
This header will be used by the RISC-V IOMMU emulation to be added
in the next patch. Due to its size it's being sent in separate for
an easier review.
One thing to notice is that this header can be replaced by the future
Linux RISC-V IOMMU driver header, which would become
From: Tomasz Jeznach
DBG support adds three additional registers: tr_req_iova, tr_req_ctl and
tr_response.
The DBG cap is always enabled. No on/off toggle is provided for it.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Reviewed-by: Alistair F
From: Tomasz Jeznach
The RISC-V IOMMU spec predicts that the IOMMU can use translation caches
to hold entries from the DDT. This includes implementation for all cache
commands that are marked as 'not implemented'.
There are some artifacts included in the cache that predicts s-stage and
g-stage e
Hi,
In this new version we fixed the IOVA == GPA MSI early check in patch 3,
in riscv_iommu_spa_fetch(), after discussions with Tomasz and Drew on
v8.
The motivation behind what was being was making the emulation work with
the existing VFIO irqbypass support in the kernel. In the end this was
not
Add an additional test to further exercise the IOMMU where we attempt to
initialize the command, fault and page-request queues.
These steps are taken from chapter 6.2 of the RISC-V IOMMU spec,
"Guidelines for initialization". It emulates what we expect from the
software/OS when initializing the IO
From: Tomasz Jeznach
Generate device tree entry for riscv-iommu PCI device, along with
mapping all PCI device identifiers to the single IOMMU device instance.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Reviewed-by: Alistair Francis
---
hw/r
The RISC-V IOMMU PCI device we're going to add next is a reference
implementation of the riscv-iommu spec [1], which predicts that the
IOMMU can be implemented as a PCIe device.
However, RISC-V International (RVI), the entity that ratified the
riscv-iommu spec, didn't bother assigning a PCI ID for
From: Tomasz Jeznach
Extend memory transaction attributes with process identifier to allow
per-request address translation logic to use requester_id / process_id
to identify memory mapping (e.g. enabling IOMMU w/ PASID translations).
Signed-off-by: Tomasz Jeznach
Reviewed-by: Frank Chang
Revie
On 03/10/2024 14.16, Michael Tokarev wrote:
currently, if an oss-fuzz fails, the script does just `exit 1`
without any additional output, and looking at the build log in
the gitlab ci it is not clear what actually failed, without
looking at build-oss-fuzz script and seeing this `exit 1`.
Print e
We try to avoid using cpu_loop_exit_atomic as it brings in an all-core
sync point. However on some cpu/kernel/benchmark combinations it is
starting to show up in the performance profile. To make it easier to
see whats going on add tracepoints for the slow path so we can see
what is triggering the w
On 10/3/24 07:00, Peter Maydell wrote:
This series is the remaining patches not yet applied from my "arm:
Drop deprecated boards" series; this is essentially the device
removals which didn't get review in that series and/or which had some
discussion about whether we should remove them.
To summar
On 10/3/24 16:43, Peter Xu wrote:
!---|
This Message Is From an External Sender
This message came from outside your organization.
|---!
On Thu, Oct 03, 2024 at
On 10/3/24 23:44, Thomas Huth wrote:
On 03/10/2024 23.40, Philippe Mathieu-Daudé wrote:
OK I guess I'm seeing Thomas point now; this series cover was not clear
enough. The goal is to remove TARGET_BIG_ENDIAN so we can build half
objects and do a little step toward the single binary.
Ok, that p
When validating the parameters of VBE ioport writes the X co-ordinate
is silently rounded down to a multiple of 8. For valid resolutions
(such as 1366x768) which are not divisible by 8 this causes
miscalculations because the display surface has shorter lines than
expected. For example, a VNC client
On Fri, 4 Oct 2024 at 02:24, Sebastian Huber
wrote:
>
> - Am 30. Sep 2024 um 17:16 schrieb Peter Maydell peter.mayd...@linaro.org:
>
> > On Mon, 23 Sept 2024 at 04:57, Sebastian Huber
> > wrote:
> >>
> >> In arm_load_kernel(), use the secondary boot hooks provided by the
> >> platform if PSCI
On Fri, Oct 04, 2024 at 02:54:38PM +0200, David Hildenbrand wrote:
> On 04.10.24 14:33, Peter Xu wrote:
> > On Fri, Oct 04, 2024 at 12:14:35PM +0200, David Hildenbrand wrote:
> > > On 03.10.24 18:14, Peter Xu wrote:
> > > > On Mon, Sep 30, 2024 at 12:40:32PM -0700, Steve Sistare wrote:
> > > > > Al
The _check() function is supposed to check whether the hash of the
downloaded file matches the expected one. Unfortunately, during the
last rework of this function, the check was accidentally turned into
returning the hash value itself instead of a True/False value,
effectively accepting each hash
On 10/4/24 5:33 AM, Andrew Jones wrote:
On Thu, Oct 03, 2024 at 11:36:00AM GMT, Tomasz Jeznach wrote:
On Thu, Oct 3, 2024 at 6:06 AM Daniel Henrique Barboza
wrote:
On 10/3/24 6:26 AM, Andrew Jones wrote:
On Tue, Oct 01, 2024 at 10:02:58PM GMT, Daniel Henrique Barboza wrote:
...
+/*
+ *
On Thu, Oct 03, 2024 at 11:36:00AM GMT, Tomasz Jeznach wrote:
> On Thu, Oct 3, 2024 at 6:06 AM Daniel Henrique Barboza
> wrote:
> >
> >
> >
> > On 10/3/24 6:26 AM, Andrew Jones wrote:
> > > On Tue, Oct 01, 2024 at 10:02:58PM GMT, Daniel Henrique Barboza wrote:
> > > ...
> > >> +/*
> > >> + * RISCV
Here's my proposal for the freeze dates for 9.2:
2024-11-05 Soft feature freeze (all feature changes must be in
a pullreq on list by this date)
2024-11-12 Hard feature freeze. Tag rc0
2024-11-19 Tag rc1
2024-11-26 Tag rc2
2024-12-03 Tag rc3
2024-12-10 Release; or tag rc4 if needed
2024-
On Thu, Aug 8, 2024 at 1:51 PM Yong-Xuan Wang wrote:
>
> In the section "4.7 Precise effects on interrupt-pending bits"
> of the RISC-V AIA specification defines that:
>
> If the source mode is Level1 or Level0 and the interrupt domain
> is configured in MSI delivery mode (domaincfg.DM = 1):
> The
On Fri, Oct 04, 2024 at 12:14:35PM +0200, David Hildenbrand wrote:
> On 03.10.24 18:14, Peter Xu wrote:
> > On Mon, Sep 30, 2024 at 12:40:32PM -0700, Steve Sistare wrote:
> > > Allocate anonymous memory using mmap MAP_ANON or memfd_create depending
> > > on the value of the anon-alloc machine prope
Implements searching the IOVA->GPA tree when translating guest-backed
memory (and searching the IOVA->HVA tree when translating host-only
memory).
By using the IOVA->GPA tree to find IOVA translations, we avoid the
issue where, if the guest has overlapping memory regions, HVAs backed by
guest memo
Implements the IOVA->GPA tree for handling mapping, unmapping, and
translations for guest memory regions.
When the guest has overlapping memory regions, an HVA to IOVA translation
may return an incorrect IOVA when searching the IOVA->HVA tree. This is
due to one HVA range being contained (overlapp
The guest may overlap guest memory regions when mapping IOVA to HVA
translations in the IOVA->HVA tree. This means that different HVAs, that
correspond to different guest memory region mappings, may translate to
the same IOVA. This can cause conflicts when a mapping is incorrectly
referenced.
For
On 04.10.24 14:33, Peter Xu wrote:
On Fri, Oct 04, 2024 at 12:14:35PM +0200, David Hildenbrand wrote:
On 03.10.24 18:14, Peter Xu wrote:
On Mon, Sep 30, 2024 at 12:40:32PM -0700, Steve Sistare wrote:
Allocate anonymous memory using mmap MAP_ANON or memfd_create depending
on the value of the an
On Tue, 3 Sept 2024 at 22:53, Philippe Mathieu-Daudé wrote:
>
> The recently removed 'cheetah' machine was the single user
> of the omap_uwire_attach() method. Remove it altogether with
> the uWireSlave structure. Replace the send/receive callbacks
> by Unimplemented logging.
>
> Signed-off-by: Ph
On 10/4/24 06:52, Alex Bennée wrote:
We try to avoid using cpu_loop_exit_atomic as it brings in an all-core
sync point. However on some cpu/kernel/benchmark combinations it is
starting to show up in the performance profile. To make it easier to
see whats going on add tracepoints for the slow path
Signed-off-by: Philippe Mathieu-Daudé
---
target/ppc/cpu_init.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 23881d09e9f..39ec290cdc0 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7341,8 +7341,6 @
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 89655b1900f..ad70ad802a7 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -132,6 +132,11 @@ static vaddr mips_cpu_get_pc(CPUSt
In order to re-use cpu_is_bigendian(), declare it on "internal.h"
after renaming it as mips_env_is_bigendian().
Reviewed-by: Jiaxun Yang
Tested-by: Jiaxun Yang
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/internal.h| 5 +
target/mips/tcg/ldst_helper.c | 15 +--
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 19191c23918..2bb87a9299f 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -122,6 +122,11 @@ void arm_restore_state_to_opc(CPUState
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 8
hw/core/cpu-common.c | 7 +++
2 files changed, 15 insertions(+)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 22ef7a44e86..2550bc98dee 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cp
For targets (or HW) which are only built for a particular
endianness, the generic LD/ST helpers are defined as the
target endianness variant. For example, on big-endian
targets, stl_p() is equivalent of stl_be_p().
This series replaces in bulk these LD/ST calls.
This is helpful for the single bin
The Hexagon target is only built for 64-bit.
Using ldtul_p() is pointless, replace by ldl_p().
Mechanical change doing:
$ sed -i -e 's/ldtul_p/ldl_p/' \
$(git grep -wl ldtul_p target/hexagon/)
Signed-off-by: Philippe Mathieu-Daudé
---
target/hexagon/gdbstub.c | 10 +-
1 file ch
Use ldn_p(TARGET_LONG_SIZE) instead of ldl_p() / ldq_p().
Signed-off-by: Philippe Mathieu-Daudé
---
include/gdbstub/helpers.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/gdbstub/helpers.h b/include/gdbstub/helpers.h
index 26140ef1ac0..fd83e366a51 100644
--- a/
The Alpha target is only built for 64-bit.
Using ldtul_p() is pointless, replace by ldq_p().
Mechanical change doing:
$ sed -i -e 's/ldtul_p/ldq_p/' $(git grep -wl ldtul_p target/alpha/)
Signed-off-by: Philippe Mathieu-Daudé
---
target/alpha/gdbstub.c | 2 +-
1 file changed, 1 insertion(+),
Introduce ldtul_le_p() and ldtul_be_p() to use directly
in place of ldtul_p() when a target endianness is fixed.
Signed-off-by: Philippe Mathieu-Daudé
---
include/gdbstub/helpers.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/gdbstub/helpers.h b/include/gdbstub/helpers.h
index f
The LoongArch architecture uses little endianness. Directly
use the little-endian LD/ST API.
Mechanical change using:
$ end=le; \
for acc in uw w l q tul; do \
sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \
-e "s/st${acc}_p(/st${acc}_${end}_p(/" \
$(git grep -wlE
The x86 architecture uses little endianness. Directly use
the little-endian LD/ST API.
Mechanical change using:
$ end=le; \
for acc in uw w l q tul; do \
sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \
-e "s/st${acc}_p(/st${acc}_${end}_p(/" \
$(git grep -wlE '(ld|
The x86 architecture uses little endianness. Directly use
the little-endian LD/ST API.
Mechanical change using:
$ end=le; \
for acc in uw w l q tul; do \
sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \
-e "s/st${acc}_p(/st${acc}_${end}_p(/" \
$(git grep -wlE '(ld|
The x86 architecture uses little endianness. Directly use
the little-endian LD/ST API.
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/i386/signal.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/linux-user/i386/signal.c b/linux-user/i386/signal.c
index cb90711834f.
Since commit 73ceb12960e ("Remove the unused sh4eb target")
we only build the SH4 architecture for little endianness.
Directly use the little-endian LD/ST API.
Mechanical change using:
$ end=le; \
for acc in uw w l q tul; do \
sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \
The S390X target is only built for 64-bit.
Using ldtul_p() is pointless, replace by ldq_p().
Mechanical change doing:
$ sed -i -e 's/ldtul_p/ldq_p/' $(git grep -wl ldtul_p target/s390x/)
Signed-off-by: Philippe Mathieu-Daudé
---
target/s390x/gdbstub.c | 30 +++---
1
The AVR architecture uses little endianness. Directly use
the little-endian LD/ST API.
Mechanical change using:
$ end=le; \
for acc in uw w l q tul; do \
sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \
-e "s/st${acc}_p(/st${acc}_${end}_p(/" \
$(git grep -wlE '(ld|
The Hexagon architecture uses little endianness. Directly use
the little-endian LD/ST API.
Mechanical change using:
$ end=le; \
for acc in uw w l q tul; do \
sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \
-e "s/st${acc}_p(/st${acc}_${end}_p(/" \
$(git grep -wlE '
The TriCore architecture uses little endianness. Directly use
the little-endian LD/ST API.
Mechanical change using:
$ end=le; \
for acc in uw w l q tul; do \
sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \
-e "s/st${acc}_p(/st${acc}_${end}_p(/" \
$(git grep -wlE '
The Alpha architecture uses little endianness. Directly use
the little-endian LD/ST API.
Mechanical change using:
$ end=le; \
for acc in uw w l q tul; do \
sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \
-e "s/st${acc}_p(/st${acc}_${end}_p(/" \
$(git grep -wlE '(l
From: "Xin Li (Intel)"
Add definitions of
1) VM-exit activate secondary controls bit
2) VM-entry load FRED bit
which are required to enable nested FRED.
Reviewed-by: Zhao Liu
Signed-off-by: Xin Li (Intel)
Link: https://lore.kernel.org/r/20240807081813.735158-3-...@zytor.com
Signed-off-by:
The following changes since commit 718780d20470c66a3a36d036b29148d5809dc855:
Merge tag 'pull-nvme-20241001' of https://gitlab.com/birkelund/qemu into
staging (2024-10-01 11:34:07 +0100)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstream
for you to
From: Lei Wang
Because the index value of the VMCS field encoding of FRED injected-event
data (one of the newly added VMCS fields for FRED transitions), 0x52, is
larger than any existing index value, raise the highest index value used
for any VMCS encoding to 0x52.
Because the index value of the
The RX architecture uses little endianness. Directly use
the little-endian LD/ST API.
Mechanical change using:
$ end=le; \
for acc in uw w l q tul; do \
sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \
-e "s/st${acc}_p(/st${acc}_${end}_p(/" \
$(git grep -wlE '(ld|s
From: "Xin Li (Intel)"
Macro CR4_FRED_MASK is defined twice, delete one.
Signed-off-by: Xin Li (Intel)
Link: https://lore.kernel.org/r/20240807081813.735158-2-...@zytor.com
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.h | 6 --
1 file changed, 6 deletions(-)
diff --git a/target/i386/
From: Ani Sinha
error_report() is more appropriate for error situations. Replace fprintf with
error_report() and error_printf() as appropriate. Some improvement in error
reporting also happens as a part of this change. For example:
From:
$ ./qemu-system-x86_64 --accel kvm
Could not access KVM ke
GCC is reporting a NULL pointer dereference when compiling aio_wait_kick()
with LTO.
The issue is that test-nested-aio-poll.c does not call qemu_init_main_loop().
It doesn't _need_ to because it never calls AIO_WAIT_WHILE(), but it seems
that LTO does not do enough dead-code elimination to catch t
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