Re: [PATCH v3 09/14] gpex: Allow more than 4 legacy IRQs

2024-10-03 Thread Akihiko Odaki
On 2024/09/28 17:57, Phil Dennis-Jordan wrote: From: Alexander Graf Some boards such as vmapple don't do real legacy PCI IRQ swizzling. Instead, they just keep allocating more board IRQ lines for each new legacy IRQ. Let's support that mode by giving instantiators a new "nr_irqs" property they

Re: [PATCH v3 04/14] hw/display/apple-gfx: Adds configurable mode list

2024-10-03 Thread Akihiko Odaki
On 2024/09/28 17:57, Phil Dennis-Jordan wrote: This change adds a property 'display_modes' on the graphics device which permits specifying a list of display modes. (screen resolution and refresh rate) PCI variant of apple-gfx only for the moment. Signed-off-by: Phil Dennis-Jordan --- hw/disp

Re: [PATCH v4 03/17] intel_iommu: Add a placeholder variable for scalable modern mode

2024-10-03 Thread CLEMENT MATHIEU--DRIF
LGTM, thanks for the update Reviewed-by: Clément Mathieu--Drif > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > Add an new element scalable_mode in IntelIOMMUState to mark scalable > modern

Re: [PATCH v3 10/14] hw/vmapple/aes: Introduce aes engine

2024-10-03 Thread Akihiko Odaki
On 2024/09/28 17:57, Phil Dennis-Jordan wrote: From: Alexander Graf VMApple contains an "aes" engine device that it uses to encrypt and decrypt its nvram. It has trivial hard coded keys it uses for that purpose. Add device emulation for this device model. Signed-off-by: Alexander Graf Co-aut

Re: [PATCH 08/13] hw/xtensa/xtfpga: Replace memcpy()+tswap32() by stl_endian_p()

2024-10-03 Thread Thomas Huth
On 03/10/2024 23.40, Philippe Mathieu-Daudé wrote: On 3/10/24 23:34, Pierrick Bouvier wrote: On 10/3/24 14:31, Pierrick Bouvier wrote: On 10/3/24 13:48, Philippe Mathieu-Daudé wrote: On 3/10/24 18:04, Pierrick Bouvier wrote: On 10/3/24 09:02, Philippe Mathieu-Daudé wrote: On 30/9/24 16:32, T

Re: [PATCH v8 03/12] hw/riscv: add RISC-V IOMMU base emulation

2024-10-03 Thread Tomasz Jeznach
On Thu, Oct 3, 2024 at 6:06 AM Daniel Henrique Barboza wrote: > > > > On 10/3/24 6:26 AM, Andrew Jones wrote: > > On Tue, Oct 01, 2024 at 10:02:58PM GMT, Daniel Henrique Barboza wrote: > > ... > >> +/* > >> + * RISCV IOMMU Address Translation Lookup - Page Table Walk > >> + * > >> + * Note: Code i

[PATCH v15 10/21] target/riscv: Add zicfiss extension

2024-10-03 Thread Deepak Gupta
zicfiss [1] riscv cpu extension enables backward control flow integrity. This patch sets up space for zicfiss extension in cpuconfig. And imple- ments dependency on A, zicsr, zimop and zcmop extensions. [1] - https://github.com/riscv/riscv-cfi Signed-off-by: Deepak Gupta Co-developed-by: Jim Sh

[PATCH v15 00/21] riscv support for control flow integrity extensions

2024-10-03 Thread Deepak Gupta
v15 for riscv zicfilp and zicfiss extensions support in qemu. I've rebased again on https://github.com/alistair23/qemu/blob/riscv-to-apply.next (tag: pull-riscv-to-apply-20241002) There is an additional patch in this with comment title "target/riscv: disallow probe accesses to shadow stack" cac

[PATCH v15 12/21] target/riscv: tb flag for shadow stack instructions

2024-10-03 Thread Deepak Gupta
Shadow stack instructions can be decoded as zimop / zcmop or shadow stack instructions depending on whether shadow stack are enabled at current privilege. This requires a TB flag so that correct TB generation and correct TB lookup happens. `DisasContext` gets a field indicating whether bcfi is enab

[PATCH v15 14/21] target/riscv: disallow probe accesses to shadow stack

2024-10-03 Thread Deepak Gupta
`check_zicbom_access` (`cbo.clean/flush/inval`) may probe shadow stack memory and must always raise store/AMO access fault because it has store semantics. For non-shadow stack memory even though `cbo.clean/flush/inval` have store semantics, it will not fault if read is allowed (probably to follow

[PATCH v15 09/21] target/riscv: Expose zicfilp extension as a cpu property

2024-10-03 Thread Deepak Gupta
Signed-off-by: Deepak Gupta Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 05f727222e..135559fc95 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1469,6 +1469,7 @@ const RISCVCPUM

[PATCH v15 07/21] target/riscv: zicfilp `lpad` impl and branch tracking

2024-10-03 Thread Deepak Gupta
Implements setting lp expected when `jalr` is encountered and implements `lpad` instruction of zicfilp. `lpad` instruction is taken out of auipc x0, . This is an existing HINTNOP space. If `lpad` is target of an indirect branch, cpu checks for 20 bit value in x7 upper with 20 bit value embedded in

[PATCH v15 18/21] target/riscv: compressed encodings for sspush and sspopchk

2024-10-03 Thread Deepak Gupta
sspush/sspopchk have compressed encodings carved out of zcmops. compressed sspush is designated as c.mop.1 while compressed sspopchk is designated as c.mop.5. Note that c.sspush x1 exists while c.sspush x5 doesn't. Similarly c.sspopchk x5 exists while c.sspopchk x1 doesn't. Signed-off-by: Deepak

[PATCH v15 05/21] target/riscv: additional code information for sw check

2024-10-03 Thread Deepak Gupta
sw check exception support was recently added. This patch further augments sw check exception by providing support for additional code which is provided in *tval. Adds `sw_check_code` field in cpuarchstate. Whenever sw check exception is raised *tval gets the value deposited in `sw_check_code`. Si

Re: [PULL v1 0/5] Xen Queue

2024-10-03 Thread Edgar E. Iglesias
On Thu, Oct 03, 2024 at 06:07:00PM +0100, Peter Maydell wrote: > On Thu, 3 Oct 2024 at 15:31, Edgar E. Iglesias > wrote: > > > > From: "Edgar E. Iglesias" > > > > The following changes since commit 423be09ab9492735924e73a2d36069784441ebc6: > > > > Merge tag 'warn-pull-request' of https://gitla

[PATCH v15 13/21] target/riscv: mmu changes for zicfiss shadow stack protection

2024-10-03 Thread Deepak Gupta
zicfiss protects shadow stack using new page table encodings PTE.W=1, PTE.R=0 and PTE.X=0. This encoding is reserved if zicfiss is not implemented or if shadow stack are not enabled. Loads on shadow stack memory are allowed while stores to shadow stack memory leads to access faults. Shadow stack ac

[PATCH v15 02/21] target/riscv: Add zicfilp extension

2024-10-03 Thread Deepak Gupta
zicfilp [1] riscv cpu extension enables forward control flow integrity. If enabled, all indirect calls must land on a landing pad instruction. This patch sets up space for zicfilp extension in cpuconfig. zicfilp is dependend on zicsr. [1] - https://github.com/riscv/riscv-cfi Signed-off-by: Deepa

[PATCH v15 17/21] target/riscv: implement zicfiss instructions

2024-10-03 Thread Deepak Gupta
zicfiss has following instructions - sspopchk: pops a value from shadow stack and compares with x1/x5. If they dont match, reports a sw check exception with tval = 3. - sspush: pushes value in x1/x5 on shadow stack - ssrdp: reads current shadow stack - ssamoswap: swaps contents of shadow sta

[PATCH v15 01/21] target/riscv: expose *envcfg csr and priv to qemu-user as well

2024-10-03 Thread Deepak Gupta
Execution environment config CSR controlling user env and current privilege state shouldn't be limited to qemu-system only. *envcfg CSRs control enabling of features in next lesser mode. In some cases bits *envcfg CSR can be lit up by kernel as part of kernel policy or software (user app) can choos

[PATCH v15 11/21] target/riscv: introduce ssp and enabling controls for zicfiss

2024-10-03 Thread Deepak Gupta
zicfiss introduces a new state ssp ("shadow stack register") in cpu. ssp is expressed as a new unprivileged csr (CSR_SSP=0x11) and holds virtual address for shadow stack as programmed by software. Shadow stack (for each mode) is enabled via bit3 in *envcfg CSRs. Shadow stack can be enabled for a m

[PULL v2 0/5] Xen Queue

2024-10-03 Thread Edgar E. Iglesias
From: "Edgar E. Iglesias" The following changes since commit 423be09ab9492735924e73a2d36069784441ebc6: Merge tag 'warn-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging (2024-10-03 10:32:54 +0100) are available in the Git repository at: https://gitlab.com/edgar.iglesi

[PULL v2 2/5] hw/xen: Expose handle_bufioreq in xen_register_ioreq

2024-10-03 Thread Edgar E. Iglesias
From: "Edgar E. Iglesias" Expose handle_bufioreq in xen_register_ioreq(). This is to allow machines to enable or disable buffered ioreqs. No functional change since all callers still set it to HVM_IOREQSRV_BUFIOREQ_ATOMIC. Reviewed-by: Stefano Stabellini Signed-off-by: Edgar E. Iglesias ---

[PULL v2 4/5] hw/xen: xenpvh: Add pci-intx-irq-base property

2024-10-03 Thread Edgar E. Iglesias
From: "Edgar E. Iglesias" Acked-by: Stefano Stabellini Signed-off-by: Edgar E. Iglesias --- hw/xen/xen-pvh-common.c | 36 1 file changed, 36 insertions(+) diff --git a/hw/xen/xen-pvh-common.c b/hw/xen/xen-pvh-common.c index 76a9b2b945..218ac851cf 100644 --

[PULL v2 3/5] hw/xen: xenpvh: Disable buffered IOREQs for ARM

2024-10-03 Thread Edgar E. Iglesias
From: "Edgar E. Iglesias" Add a way to enable/disable buffered IOREQs for PVH machines and disable them for ARM. ARM does not support buffered IOREQ's nor the legacy way to map IOREQ info pages. See the following for more details: https://xenbits.xen.org/gitweb/?p=xen.git;a=commitdiff;h=2fbd7e60

[PULL v2 1/5] hw/xen: Remove deadcode

2024-10-03 Thread Edgar E. Iglesias
From: "Dr. David Alan Gilbert" xen_be_copy_grant_refs is unused since 2019's 19f87870ba ("xen: remove the legacy 'xen_disk' backend") xen_config_dev_console is unused since 2018's 6d7c06c213 ("Remove broken Xen PV domain builder") Remove them. Signed-off-by: Dr. David Alan Gilbert Acked-b

Re: [PATCH 08/13] hw/xtensa/xtfpga: Replace memcpy()+tswap32() by stl_endian_p()

2024-10-03 Thread Philippe Mathieu-Daudé
On 3/10/24 18:04, Pierrick Bouvier wrote: On 10/3/24 09:02, Philippe Mathieu-Daudé wrote: On 30/9/24 16:32, Thomas Huth wrote: On 30/09/2024 09.34, Philippe Mathieu-Daudé wrote: Replace a pair of memcpy() + tswap32() by stl_endian_p(), which also swap the value using target endianness. Signed

Re: [PATCH 01/13] qemu/bswap: Introduce ld/st_endian_p() API

2024-10-03 Thread Philippe Mathieu-Daudé
On 30/9/24 09:34, Philippe Mathieu-Daudé wrote: Introduce the ld/st_endian_p() API, which takes an extra Alternatively we could use ld/st_te_p() since we already have ld/st_he_p() for host endianness. boolean argument to dispatch to ld/st_{be,le}_p() methods. Signed-off-by: Philippe Mathieu-

Re: [PATCH] qapi, machine-qmp-cmds.c: query-accelerator support

2024-10-03 Thread Philippe Mathieu-Daudé
On 2/10/24 20:06, Daniel Henrique Barboza wrote: On 9/27/24 7:50 AM, Daniel P. Berrangé wrote: Markus: QAPI design Qs for you at the bottom On Wed, Sep 25, 2024 at 10:19:33AM -0300, Daniel Henrique Barboza wrote: On 9/19/24 9:22 AM, Daniel P. Berrangé wrote: On Thu, Sep 19, 2024 at 08:20:5

Re: [PATCH v15 14/21] target/riscv: disallow probe accesses to shadow stack

2024-10-03 Thread Deepak Gupta
On Thu, Oct 03, 2024 at 11:33:35AM -0700, Deepak Gupta wrote: `check_zicbom_access` (`cbo.clean/flush/inval`) may probe shadow stack memory and must always raise store/AMO access fault because it has store semantics. For non-shadow stack memory even though `cbo.clean/flush/inval` have store sema

[PATCH v15 03/21] target/riscv: Introduce elp state and enabling controls for zicfilp

2024-10-03 Thread Deepak Gupta
zicfilp introduces a new state elp ("expected landing pad") in cpu. During normal execution, elp is idle (NO_LP_EXPECTED) i.e not expecting landing pad. On an indirect call, elp moves LP_EXPECTED. When elp is LP_EXPECTED, only a subsquent landing pad instruction can set state back to NO_LP_EXPECTED

[PATCH v15 04/21] target/riscv: save and restore elp state on priv transitions

2024-10-03 Thread Deepak Gupta
elp state is recorded in *status on trap entry (less privilege to higher privilege) and restored in elp from *status on trap exit (higher to less privilege). Additionally this patch introduces a forward cfi helper function to determine if current privilege has forward cfi is enabled or not based o

[PATCH v15 19/21] disas/riscv: enable disassembly for zicfiss instructions

2024-10-03 Thread Deepak Gupta
Enable disassembly for sspush, sspopchk, ssrdp & ssamoswap. Disasembly is only enabled if zimop and zicfiss ext is set to true. Signed-off-by: Deepak Gupta Acked-by: Alistair Francis --- disas/riscv.c | 40 +++- disas/riscv.h | 1 + 2 files changed, 40 inser

[PATCH v15 08/21] disas/riscv: enable `lpad` disassembly

2024-10-03 Thread Deepak Gupta
Signed-off-by: Deepak Gupta Co-developed-by: Jim Shu Co-developed-by: Andy Chiu Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- disas/riscv.c | 18 +- disas/riscv.h | 2 ++ 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c b/disas/r

Re: [PATCH] hw/riscv/spike: Replace tswap64() by ldq_endian_p()

2024-10-03 Thread Philippe Mathieu-Daudé
On 2/10/24 17:01, Daniel Henrique Barboza wrote: On 10/2/24 11:44 AM, Mark Cave-Ayland wrote: On 02/10/2024 15:17, Daniel Henrique Barboza wrote: Phil, this patch breaks 'make check-avocado' in my env: On 9/30/24 9:48 AM, Philippe Mathieu-Daudé wrote: Hold the target endianness in HTIFSta

Re: [PATCH] tests/tcg/plugins: Remove remainder of the cris target

2024-10-03 Thread Philippe Mathieu-Daudé
On 2/10/24 16:37, Thomas Huth wrote: The cris target has recently been removed (see commit 44e4075bf4 - "target/cris: Remove the deprecated CRIS target"), but apparently this line has been forgotten. So clean it up now. Crossed pull request ¯\_(ツ)_/¯ Thanks for cleaning. Reviewed-by: Philippe

Re: [PATCH] hw/char: Remove unused serial_set_frequency

2024-10-03 Thread Philippe Mathieu-Daudé
On 18/9/24 16:41, d...@treblig.org wrote: From: "Dr. David Alan Gilbert" serial_set_frequnecy has been unused since it was added in 2009: 038eaf82c8 ("serial: Add interface to set reference oscillator frequency") It looks like the 'baudbase' is now a property anyway so the wrapper isn't nee

Re: [PATCH] hw/pci: Remove unused pcie_chassis_find_slot

2024-10-03 Thread Philippe Mathieu-Daudé
On 19/9/24 01:47, d...@treblig.org wrote: From: "Dr. David Alan Gilbert" pcie_chassis_find_slot has been unused since it was added. Remove it. Signed-off-by: Dr. David Alan Gilbert --- hw/pci/pcie_port.c | 10 -- include/hw/pci/pcie_port.h | 1 - 2 files changed, 11 dele

Re: [PATCH v2 08/17] migration: Add load_finish handler and associated functions

2024-10-03 Thread Peter Xu
On Thu, Oct 03, 2024 at 10:34:28PM +0200, Maciej S. Szmigiero wrote: > To be clear, these loading threads are mostly blocking I/O threads, NOT > compute threads. > This means that the usual "rule of thumb" that the count of threads should > not exceed the total number of logical CPUs does NOT apply

[PATCH 04/16] hw/i386: Use explicit little-endian LD/ST API

2024-10-03 Thread Philippe Mathieu-Daudé
The x86 architecture uses little endianness. Directly use the little-endian LD/ST API. Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/multiboot.c | 36 ++-- hw/i386/x86-common.c | 26 +- 2 files changed, 31 insertions(+), 31 deletions(-

[PATCH 05/16] target/i386: Use explicit little-endian LD/ST API

2024-10-03 Thread Philippe Mathieu-Daudé
The x86 architecture uses little endianness. Directly use the little-endian LD/ST API. Signed-off-by: Philippe Mathieu-Daudé --- target/i386/gdbstub.c| 26 +++--- target/i386/tcg/sysemu/excp_helper.c | 4 ++-- target/i386/xsave_helper.c | 32 +++

[PATCH 02/16] exec/memop: Remove unused memop_big_endian() helper

2024-10-03 Thread Philippe Mathieu-Daudé
Last use of memop_big_endian() was removed in commit 592134617c9 ("accel/tcg: Reorg system mode store helpers"). Signed-off-by: Philippe Mathieu-Daudé --- include/exec/memop.h | 6 -- 1 file changed, 6 deletions(-) diff --git a/include/exec/memop.h b/include/exec/memop.h index f881fe7af4e..

[PATCH 09/16] hw/s390x: Use explicit big-endian LD/ST API

2024-10-03 Thread Philippe Mathieu-Daudé
The S390 architecture uses big endianness. Directly use the big-endian LD/ST API. Signed-off-by: Philippe Mathieu-Daudé --- hw/s390x/ipl.c | 4 +- hw/s390x/s390-pci-inst.c | 166 +++ 2 files changed, 85 insertions(+), 85 deletions(-) diff --git a/

[PATCH 08/16] hw/ppc/e500: Use explicit big-endian LD/ST API

2024-10-03 Thread Philippe Mathieu-Daudé
The 32-bit PPC architecture uses big endianness. Directly use the big-endian LD/ST API for the E500 hardware. Signed-off-by: Philippe Mathieu-Daudé --- hw/ppc/ppce500_spin.c | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/hw/ppc/ppce500_spin.c b/hw/

[PATCH 07/16] target/m68k: Use explicit big-endian LD/ST API

2024-10-03 Thread Philippe Mathieu-Daudé
The M68K architecture uses big endianness. Directly use the big-endian LD/ST API. Signed-off-by: Philippe Mathieu-Daudé --- target/m68k/gdbstub.c | 2 +- target/m68k/helper.c | 10 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/m68k/gdbstub.c b/target/m68k/gdb

[PATCH 10/16] target/s390x: Use explicit big-endian LD/ST API

2024-10-03 Thread Philippe Mathieu-Daudé
The S390 architecture uses big endianness. Directly use the big-endian LD/ST API. Signed-off-by: Philippe Mathieu-Daudé --- target/s390x/gdbstub.c | 4 ++-- target/s390x/ioinst.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub

[PATCH 06/16] hw/m68k: Use explicit big-endian LD/ST API

2024-10-03 Thread Philippe Mathieu-Daudé
The M68K architecture uses big endianness. Directly use the big-endian LD/ST API. Signed-off-by: Philippe Mathieu-Daudé --- hw/m68k/bootinfo.h | 28 ++-- hw/m68k/mcf5208.c | 2 +- hw/m68k/next-cube.c | 2 +- hw/m68k/q800.c | 4 ++-- 4 files changed, 18 insertio

[PATCH 11/16] hw/sparc: Use explicit big-endian LD/ST API

2024-10-03 Thread Philippe Mathieu-Daudé
The SPARC architecture uses big endianness. Directly use the big-endian LD/ST API. Signed-off-by: Philippe Mathieu-Daudé --- hw/sparc/leon3.c | 42 +- hw/sparc/sun4m.c | 6 +++--- hw/sparc64/sun4u.c | 6 +++--- 3 files changed, 27 insertions(+), 27 d

[PATCH 03/16] linux-user/i386: Use explicit little-endian LD/ST API

2024-10-03 Thread Philippe Mathieu-Daudé
The x86 architecture uses little endianness. Directly use the little-endian LD/ST API. Signed-off-by: Philippe Mathieu-Daudé --- linux-user/i386/signal.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/linux-user/i386/signal.c b/linux-user/i386/signal.c index cb90711834f.

[PATCH 00/16] misc: Use explicit endian LD/ST API

2024-10-03 Thread Philippe Mathieu-Daudé
For targets (or HW) which are only built for a particular endianness, the generic LD/ST helpers are defined as the target endianness variant. For example, on big-endian targets, stl_p() is equivalent of stl_be_p(). This series replaces in bulk these LD/ST calls. This is helpful for the single bin

[PATCH 12/16] target/sparc: Use explicit big-endian LD/ST API

2024-10-03 Thread Philippe Mathieu-Daudé
The SPARC architecture uses big endianness. Directly use the big-endian LD/ST API. Signed-off-by: Philippe Mathieu-Daudé --- target/sparc/gdbstub.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c index ec0036e9ef6..da72a7d3f

[PATCH 01/16] qemu/bswap: Undefine CPU_CONVERT() once done

2024-10-03 Thread Philippe Mathieu-Daudé
Better undefined macros once we are done with them, like we do few lines later with DO_STN_LDN_P(). Signed-off-by: Philippe Mathieu-Daudé --- include/qemu/bswap.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h index ad22910a5d1..b915835bead 1006

Re: [PATCH 12/13] hw/pci/pci_device: Introduce ld/st_endian_pci_dma() API

2024-10-03 Thread Richard Henderson
On 9/30/24 00:34, Philippe Mathieu-Daudé wrote: Introduce the ld/st_endian_pci_dma() API, which takes an extra boolean argument to dispatch to ld/st_{be,le}_pci_dma() methods. Signed-off-by: Philippe Mathieu-Daudé --- TODO: Update docstring regexp --- include/hw/pci/pci_device.h | 24

Re: [PATCH v2 1/4] hw/ppc/spapr_nvdimm: Simplify LD/ST API uses

2024-10-03 Thread Richard Henderson
On 9/27/24 14:50, Philippe Mathieu-Daudé wrote: ldn/stn methods handle the access size, no need for the switch case. Signed-off-by: Philippe Mathieu-Daudé --- hw/ppc/spapr_nvdimm.c | 47 --- 1 file changed, 4 insertions(+), 43 deletions(-) Reviewed-by

Re: [PATCH v2 2/4] hw/ppc/spapr_vof: Simplify LD/ST API uses

2024-10-03 Thread Richard Henderson
On 9/27/24 14:50, Philippe Mathieu-Daudé wrote: Directly call ldn_be_p once instead of ldl_be_p / ldq_be_p. Signed-off-by: Philippe Mathieu-Daudé --- hw/ppc/spapr_vof.c | 27 +-- 1 file changed, 9 insertions(+), 18 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PATCH v2 4/4] net/l2tpv3: Simplify LD/ST API uses

2024-10-03 Thread Richard Henderson
On 9/27/24 14:50, Philippe Mathieu-Daudé wrote: Directly call ldn_be_p once instead of ldl_be_p / ldq_be_p. Signed-off-by: Philippe Mathieu-Daudé --- net/l2tpv3.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/net/l2tpv3.c b/net/l2tpv3.c index b5547cb917..7a0d5dcfe9

Re: [PATCH 13/13] hw/net/tulip: Use ld/st_endian_pci_dma() API

2024-10-03 Thread Richard Henderson
On 9/30/24 00:34, Philippe Mathieu-Daudé wrote: Refactor to use the recently introduced ld/st_endian_pci_dma() API. No logical change intended. Signed-off-by: Philippe Mathieu-Daudé --- hw/net/tulip.c | 32 ++-- 1 file changed, 10 insertions(+), 22 deletions(-) d

Re: [PATCH 01/12] target/mips: Declare cpu_is_bigendian_env() in 'internal.h'

2024-10-03 Thread Richard Henderson
On 9/30/24 02:10, Philippe Mathieu-Daudé wrote: In order to re-use cpu_is_bigendian(), declare it on "internal.h" after renaming it as cpu_is_bigendian_env(). Signed-off-by: Philippe Mathieu-Daudé --- target/mips/internal.h| 6 ++ target/mips/tcg/ldst_helper.c | 15 +

Re: [PATCH 08/12] target/mips: Expose MIPSCPU::is_big_endian property

2024-10-03 Thread Richard Henderson
On 9/30/24 02:10, Philippe Mathieu-Daudé wrote: Add the "big-endian" property and set the CP0C0_BE bit in CP0_Config0. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu.h | 3 +++ target/mips/cpu.c | 9 - 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/target/

Re: {PATCH] accel/tcg: Fix CPU specific unaligned behaviour

2024-10-03 Thread Richard Henderson
On 10/2/24 08:47, Peter Maydell wrote: There's also something curious going on here -- this patch says "we check alignment before permissions, and that's wrong on PARISC". But there's a comment in target/arm/ptw.c that says "we check permissions before alignment, and that's wrong on Arm":

Re: [PATCH 04/12] target/mips: Convert mips16e decr_and_load/store() macros to functions

2024-10-03 Thread Richard Henderson
On 9/30/24 02:10, Philippe Mathieu-Daudé wrote: Functions are easier to rework than macros. Besides, there is no gain here in inlining these. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/mips16e_translate.c.inc | 101 +--- 1 file changed, 53 insertions(+), 48

Re: [PATCH 05/12] target/mips: Introduce mo_endian() helper

2024-10-03 Thread Richard Henderson
On 9/30/24 02:10, Philippe Mathieu-Daudé wrote: Introduce mo_endian() which returns the endian MemOp corresponding to the vCPU DisasContext. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.h | 5 + 1 file changed, 5 insertions(+) diff --git a/target/mips/tcg/translat

Re: [PATCH 11/12] target/mips: Remove target-specific code in mips_cpu_reset_hold()

2024-10-03 Thread Richard Henderson
On 9/30/24 02:11, Philippe Mathieu-Daudé wrote: Since all code creating vCPUs now set the 'cpu-big-endian' property, we can remove the target-specific #ifdef'ry in mips_cpu_reset_hold(): the CP0C0_BE bit is set using the property cpu->is_big_endian value. Signed-off-by: Philippe Mathieu-Daudé -

Re: [PATCH 1/2] hw/arm/boot: Use hooks if PSCI is disabled

2024-10-03 Thread Sebastian Huber
- Am 30. Sep 2024 um 17:16 schrieb Peter Maydell peter.mayd...@linaro.org: > On Mon, 23 Sept 2024 at 04:57, Sebastian Huber > wrote: >> >> In arm_load_kernel(), use the secondary boot hooks provided by the >> platform if PSCI is disabled also while booting a non-Linux kernel. >> While booting

Re: [PATCH v4] tests/tcg/x86_64: Add cross-modifying code test

2024-10-03 Thread Richard Henderson
On 10/1/24 08:03, Ilya Leoshkevich wrote: commit f025692c992c ("accel/tcg: Clear PAGE_WRITE before translation") fixed cross-modifying code handling, but did not add a test. The changed code was further improved recently [1], and I was not sure whether these modifications were safe (spoiler: they

[PATCH v15 15/21] target/riscv: AMO operations always raise store/AMO fault

2024-10-03 Thread Deepak Gupta
This patch adds one more word for tcg compile which can be obtained during unwind time to determine fault type for original operation (example AMO). Depending on that, fault can be promoted to store/AMO fault. Signed-off-by: Deepak Gupta Suggested-by: Richard Henderson Reviewed-by: Richard Hende

[PATCH v15 06/21] target/riscv: tracking indirect branches (fcfi) for zicfilp

2024-10-03 Thread Deepak Gupta
zicfilp protects forward control flow (if enabled) by enforcing all indirect call and jmp must land on a landing pad instruction `lpad`. If target of an indirect call or jmp is not `lpad` then cpu/hart must raise a sw check exception with tval = 2. This patch implements the mechanism using TCG. Ta

[PATCH v15 16/21] target/riscv: update `decode_save_opc` to store extra word2

2024-10-03 Thread Deepak Gupta
Extra word 2 is stored during tcg compile and `decode_save_opc` needs additional argument in order to pass the value. This will be used during unwind to get extra information about instruction like how to massage exceptions. Updated all callsites as well. Resolves: https://gitlab.com/qemu-project/

[PATCH v15 21/21] target/riscv: Expose zicfiss extension as a cpu property

2024-10-03 Thread Deepak Gupta
Signed-off-by: Deepak Gupta Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ac5ad6fa9d..0751d08d85 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1473,6 +1473,7 @@ const RISCVCPUM

[PATCH v15 20/21] disas/riscv: enable disassembly for compressed sspush/sspopchk

2024-10-03 Thread Deepak Gupta
sspush and sspopchk have equivalent compressed encoding taken from zcmop. cmop.1 is sspush x1 while cmop.5 is sspopchk x5. Due to unusual encoding for both rs1 and rs2 from space bitfield, this required a new codec. Signed-off-by: Deepak Gupta Acked-by: Alistair Francis --- disas/riscv.c | 19 +

Re: [PATCH v2 1/1] target/riscv: enable floating point unit

2024-10-03 Thread Richard Henderson
On 9/24/24 23:17, Heinrich Schuchardt wrote: The status and mstatus CSRs contain bit field FS, which control if the floating point unit of RISC-V hart is enabled. There seems to be no specification prescribing the value of the field when entering S-mode from M-mode. But OpenSBI, as the leading S

[PULL v2 5/5] hw/arm: xenpvh: Enable PCI for ARM PVH

2024-10-03 Thread Edgar E. Iglesias
From: "Edgar E. Iglesias" Enable PCI support for the ARM Xen PVH machine. Reviewed-by: Stefano Stabellini Signed-off-by: Edgar E. Iglesias --- hw/arm/xen-pvh.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/hw/arm/xen-pvh.c b/hw/arm/xen-pvh.c index 28af3910ea..33f0dd5982

Re: [PATCH] hw/audio/virtio-snd: Remove unnecessary "exec/tswap.h" header

2024-10-03 Thread Richard Henderson
On 9/26/24 03:21, Philippe Mathieu-Daudé wrote: We were including the "exec/tswap.h" header to get target_words_bigendian() declaration, but since commit a276ec8e26 ("hw/audio/virtio-snd: Always use little endian audio format") removed this method call, we don't need this header anymore. Signed-

Re: [PATCH v2 08/17] migration: Add load_finish handler and associated functions

2024-10-03 Thread Maciej S. Szmigiero
On 2.10.2024 23:25, Peter Xu wrote: On Wed, Oct 02, 2024 at 10:11:33PM +0200, Maciej S. Szmigiero wrote: On 1.10.2024 23:30, Peter Xu wrote: On Tue, Oct 01, 2024 at 10:41:14PM +0200, Maciej S. Szmigiero wrote: On 30.09.2024 23:57, Peter Xu wrote: On Mon, Sep 30, 2024 at 09:25:54PM +0200, Maci

Re: [PATCH 0/6] refactor RDMA live migration based on rsocket API

2024-10-03 Thread Michael Galaxy
On 9/30/24 14:47, Peter Xu wrote: !---| This Message Is From an External Sender This message came from outside your organization. |---! On Mon, Sep 30, 2024 at 07

Re: [PATCH 08/13] hw/xtensa/xtfpga: Replace memcpy()+tswap32() by stl_endian_p()

2024-10-03 Thread Pierrick Bouvier
On 10/3/24 13:48, Philippe Mathieu-Daudé wrote: On 3/10/24 18:04, Pierrick Bouvier wrote: On 10/3/24 09:02, Philippe Mathieu-Daudé wrote: On 30/9/24 16:32, Thomas Huth wrote: On 30/09/2024 09.34, Philippe Mathieu-Daudé wrote: Replace a pair of memcpy() + tswap32() by stl_endian_p(), which als

Re: [PATCH] hw/sd/sdcard: Fix handling of disabled boot partitions

2024-10-03 Thread Philippe Mathieu-Daudé
On 1/10/24 15:01, Peter Maydell wrote: On Mon, 30 Sept 2024 at 21:05, Jan Lübbe wrote: On Mon, 2024-09-30 at 15:18 +0100, Peter Maydell wrote: On Fri, 6 Sept 2024 at 17:51, Jan Luebbe wrote: The enable bits in the EXT_CSD_PART_CONFIG ext_csd register do *not* specify whether the boot parti

Re: [PATCH 01/13] qemu/bswap: Introduce ld/st_endian_p() API

2024-10-03 Thread Richard Henderson
On 10/3/24 13:50, Philippe Mathieu-Daudé wrote: On 30/9/24 09:34, Philippe Mathieu-Daudé wrote: Introduce the ld/st_endian_p() API, which takes an extra Alternatively we could use ld/st_te_p() since we already have ld/st_he_p() for host endianness. That's what ld/st_p are -- target-specific,

Re: [PATCH 08/13] hw/xtensa/xtfpga: Replace memcpy()+tswap32() by stl_endian_p()

2024-10-03 Thread Pierrick Bouvier
On 10/3/24 14:31, Pierrick Bouvier wrote: On 10/3/24 13:48, Philippe Mathieu-Daudé wrote: On 3/10/24 18:04, Pierrick Bouvier wrote: On 10/3/24 09:02, Philippe Mathieu-Daudé wrote: On 30/9/24 16:32, Thomas Huth wrote: On 30/09/2024 09.34, Philippe Mathieu-Daudé wrote: Replace a pair of memcpy

Re: [PATCH 01/13] qemu/bswap: Introduce ld/st_endian_p() API

2024-10-03 Thread Philippe Mathieu-Daudé
On 3/10/24 23:28, Richard Henderson wrote: On 10/3/24 13:50, Philippe Mathieu-Daudé wrote: On 30/9/24 09:34, Philippe Mathieu-Daudé wrote: Introduce the ld/st_endian_p() API, which takes an extra Alternatively we could use ld/st_te_p() since we already have ld/st_he_p() for host endianness.

Re: [PATCH 07/13] hw/xtensa/xtfpga: Remove TARGET_BIG_ENDIAN #ifdef'ry

2024-10-03 Thread Richard Henderson
On 9/30/24 00:34, Philippe Mathieu-Daudé wrote: Move code evaluation from preprocessor to compiler so both if() ladders are processed. Mostly style change. Signed-off-by: Philippe Mathieu-Daudé --- hw/xtensa/xtfpga.c | 12 +++- 1 file changed, 7 insertions(+), 5 deletions(-) diff --

Re: [PATCH 09/13] exec/memory_ldst_phys: Introduce ld/st_endian_phys() API

2024-10-03 Thread Richard Henderson
On 9/30/24 00:34, Philippe Mathieu-Daudé wrote: Introduce the ld/st_endian_phys() API, which takes an extra boolean argument to dispatch to ld/st_{be,le}_phys() methods. Signed-off-by: Philippe Mathieu-Daudé --- TODO: Update docstring regexp --- include/exec/memory_ldst_phys.h.inc | 66 ++

Re: [PATCH 01/13] qemu/bswap: Introduce ld/st_endian_p() API

2024-10-03 Thread Richard Henderson
On 10/3/24 14:34, Philippe Mathieu-Daudé wrote: On 3/10/24 23:28, Richard Henderson wrote: On 10/3/24 13:50, Philippe Mathieu-Daudé wrote: On 30/9/24 09:34, Philippe Mathieu-Daudé wrote: Introduce the ld/st_endian_p() API, which takes an extra Alternatively we could use ld/st_te_p() since we

Re: [PATCH 08/13] hw/xtensa/xtfpga: Replace memcpy()+tswap32() by stl_endian_p()

2024-10-03 Thread Philippe Mathieu-Daudé
On 3/10/24 23:34, Pierrick Bouvier wrote: On 10/3/24 14:31, Pierrick Bouvier wrote: On 10/3/24 13:48, Philippe Mathieu-Daudé wrote: On 3/10/24 18:04, Pierrick Bouvier wrote: On 10/3/24 09:02, Philippe Mathieu-Daudé wrote: On 30/9/24 16:32, Thomas Huth wrote: On 30/09/2024 09.34, Philippe Mat

Re: [PATCH 0/6] refactor RDMA live migration based on rsocket API

2024-10-03 Thread Peter Xu
On Thu, Oct 03, 2024 at 04:26:27PM -0500, Michael Galaxy wrote: > What about the testing solution that I mentioned? > > Does that satisfy your concerns? Or is there still a gap here that needs to > be met? I think such testing framework would be helpful, especially if we can kick it off in CI whe

Re: [PATCH 09/13] exec/memory_ldst_phys: Introduce ld/st_endian_phys() API

2024-10-03 Thread Richard Henderson
On 9/30/24 00:34, Philippe Mathieu-Daudé wrote: Introduce the ld/st_endian_phys() API, which takes an extra boolean argument to dispatch to ld/st_{be,le}_phys() methods. Signed-off-by: Philippe Mathieu-Daudé --- TODO: Update docstring regexp --- include/exec/memory_ldst_phys.h.inc | 66 ++

Re: [PATCH 01/13] qemu/bswap: Introduce ld/st_endian_p() API

2024-10-03 Thread Philippe Mathieu-Daudé
On 3/10/24 23:37, Richard Henderson wrote: On 10/3/24 14:34, Philippe Mathieu-Daudé wrote: On 3/10/24 23:28, Richard Henderson wrote: On 10/3/24 13:50, Philippe Mathieu-Daudé wrote: On 30/9/24 09:34, Philippe Mathieu-Daudé wrote: Introduce the ld/st_endian_p() API, which takes an extra Alte

Re: [PATCH v3 01/14] hw/display/apple-gfx: Introduce ParavirtualizedGraphics.Framework support

2024-10-03 Thread Akihiko Odaki
On 2024/10/02 22:33, Phil Dennis-Jordan wrote: Hi, Thanks for taking a close look at this. There are some further comments, explanations, and also a few questions inline below. Where I've not commented, I'll just go ahead and make the suggested change for v4. On Tue, 1 Oct 2024 at 11:40, Ak

[PATCH] MAINTAINERS: remove gensyscalls.sh from the linux-user section

2024-10-03 Thread Laurent Vivier
The file has been removed by c52e40596834 ("linux-user,loongarch: move to syscalltbl file"). Signed-off-by: Laurent Vivier --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index ffacd60f4075..4a6b6ce6006f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -

[PING PATCH v5 3/3] tests/qtest: Check STM32L4x5 clock connections

2024-10-03 Thread Inès Varhol
For USART, GPIO and SYSCFG devices, check that clock frequency before and after enabling the peripheral clock in RCC is correct. Signed-off-by: Inès Varhol Reviewed-by: Peter Maydell Reviewed-by: Luc Michel --- tests/qtest/stm32l4x5.h | 42 + tests/qtest

[PING PATCH v5 2/3] hw/clock: Expose 'qtest-clock-period' QOM property for QTests

2024-10-03 Thread Inès Varhol
Expose the clock period via the QOM 'qtest-clock-period' property so it can be used in QTests. This property is only accessible in QTests (not via HMP). Signed-off-by: Inès Varhol Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel --- docs/devel/clocks.rst | 6 ++ hw/core/clock.c

[PING PATCH v5 1/3] hw/misc: Create STM32L4x5 SYSCFG clock

2024-10-03 Thread Inès Varhol
This commit creates a clock in STM32L4x5 SYSCFG and wires it up to the corresponding clock from STM32L4x5 RCC. Signed-off-by: Inès Varhol Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel --- include/hw/misc/stm32l4x5_syscfg.h | 1 + hw/arm/stm32l4x5_soc.

Re: [PULL 0/5] Fix mips64el CI job + some other misc patches

2024-10-03 Thread Peter Maydell
On Wed, 2 Oct 2024 at 13:52, Thomas Huth wrote: > > The following changes since commit 718780d20470c66a3a36d036b29148d5809dc855: > > Merge tag 'pull-nvme-20241001' of https://gitlab.com/birkelund/qemu into > staging (2024-10-01 11:34:07 +0100) > > are available in the Git repository at: > > h

Re: [PATCH for-9.2 v6 03/12] hw/riscv: add RISC-V IOMMU base emulation

2024-10-03 Thread Andrew Jones
On Tue, Oct 01, 2024 at 09:05:52PM GMT, Daniel Henrique Barboza wrote: > > > On 10/1/24 8:28 PM, Tomasz Jeznach wrote: > > On Tue, Sep 3, 2024 at 4:46 AM Daniel Henrique Barboza > > wrote: > > > > > > > > > > > > On 8/26/24 11:18 PM, Tomasz Jeznach wrote: > > > > On Fri, Aug 23, 2024 at 5:42 

Re: Rust BoF and maintainer minutes and planning the roadmap to Rust

2024-10-03 Thread Warner Losh
On Thu, Oct 3, 2024, 3:53 AM Daniel P. Berrangé wrote: > On Thu, Oct 03, 2024 at 02:53:08AM -0600, Warner Losh wrote: > > On Thu, Sep 26, 2024 at 8:24 AM Alex Bennée > wrote: > > > > > One output from this discussion should be a clear statement that we are > > > going forward with this work and

Re: Rust BoF and maintainer minutes and planning the roadmap to Rust

2024-10-03 Thread Daniel P . Berrangé
On Thu, Oct 03, 2024 at 02:53:08AM -0600, Warner Losh wrote: > On Thu, Sep 26, 2024 at 8:24 AM Alex Bennée wrote: > > > One output from this discussion should be a clear statement that we are > > going forward with this work and the road map. A rough roadmap might > > look like: > > > > - 9.2

Re: [PATCH] hw/net/net_rx_pkt: Remove deadcode

2024-10-03 Thread Michael Tokarev
19.09.2024 01:51, d...@treblig.org wrote: From: "Dr. David Alan Gilbert" net_rx_pkt_get_l3_hdr_offset and net_rx_pkt_get_iovec_len haven't been used since they were added. Remove them. Applied to the trivial-patches tree, removing net_rx_pkt_get_l3_hdr_offset() prototype from hw/net/net_rx_p

Re: [PATCH v8 03/12] hw/riscv: add RISC-V IOMMU base emulation

2024-10-03 Thread Andrew Jones
On Tue, Oct 01, 2024 at 10:02:58PM GMT, Daniel Henrique Barboza wrote: ... > +/* > + * RISCV IOMMU Address Translation Lookup - Page Table Walk > + * > + * Note: Code is based on get_physical_address() from > target/riscv/cpu_helper.c > + * Both implementation can be merged into single helper func

Re: Rust BoF and maintainer minutes and planning the roadmap to Rust

2024-10-03 Thread Warner Losh
On Thu, Sep 26, 2024 at 8:24 AM Alex Bennée wrote: > One output from this discussion should be a clear statement that we are > going forward with this work and the road map. A rough roadmap might > look like: > > - 9.2 --enable-rust is available and developers can build with it. > r

[PING PATCH v5 0/3] Check clock connection between STM32L4x5 RCC and peripherals

2024-10-03 Thread Inès Varhol
Among implemented STM32L4x5 devices, USART, GPIO and SYSCFG have a clock source, but none has a corresponding test in QEMU. This patch makes sure that all 3 devices create a clock correctly, adds a QOM property to access clocks' periods from QTests, and adds QTests checking that clock enable in RC

Re: Rust BoF and maintainer minutes and planning the roadmap to Rust

2024-10-03 Thread Alex Bennée
Warner Losh writes: > On Thu, Oct 3, 2024 at 2:53 AM Warner Losh wrote: > > On Thu, Sep 26, 2024 at 8:24 AM Alex Bennée wrote: > > One output from this discussion should be a clear statement that we are > going forward with this work and the road map. A rough roadmap might > look like: > >

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