On 08/05/2024 05.11, Bibo Mao wrote:
On LoongArch system, there is only virt machine type now, name
LOONGARCH_MACHINE is confused, rename it with LOONGARCH_VIRT_MACHINE.
Machine name about Other real hw boards can be added in future.
Signed-off-by: Bibo Mao
---
...
diff --git a/hw/loongarch/v
Thomas Huth writes:
> On 08/05/2024 05.11, Bibo Mao wrote:
>> On LoongArch system, there is only virt machine type now, name
>> LOONGARCH_MACHINE is confused, rename it with LOONGARCH_VIRT_MACHINE.
>> Machine name about Other real hw boards can be added in future.
>> Signed-off-by: Bibo Mao
>> -
Alexandre Ratchov writes:
> On Tue, Sep 10, 2024 at 03:28:57PM +0100, Daniel P. Berrangé wrote:
>> >
>> > This is the single use of the ISC license in the more than 10k
>> > files in the repository. Just checking IIUC this document:
>> > https://www.gnu.org/licenses/quick-guide-gplv3.en.html
>>
During the process of hot-unplug in vhost-user-net NIC, vhost_user_cleanup
may add same rcu node to rcu list. Function calls are as follows:
vhost_user_cleanup
->vhost_user_host_notifier_remove
->call_rcu(n, vhost_user_host_notifier_free, rcu);
->g_free_rcu(n, rcu);
When this happ
Qeueued. I'm going to sit on it for a few more days in the hope of
getting PATCH 1+7 reviewed, too.
Queued.
Peter Maydell writes:
> On Tue, 3 Sept 2024 at 21:04, Philippe Mathieu-Daudé
> wrote:
>>
>> sd_set_cb() was only used by omap2_mmc_init() which
>> got recently removed. Time to remove it. For historical
>> background on the me_no_qdev_me_kill_mammoth_with_rocks
>> kludge, see commit 007d1dbf72
Daniil Tatianin writes:
> The 'reconnect' option only allows to specify the time in seconds,
> which is way too long for certain workflows.
>
> We have a lightweight disk backend server, which takes about 20ms to
> live update, but due to this limitation in QEMU, previously the guest
> disk contr
On 9/13/24 11:57 AM, Markus Armbruster wrote:
Daniil Tatianin writes:
The 'reconnect' option only allows to specify the time in seconds,
which is way too long for certain workflows.
We have a lightweight disk backend server, which takes about 20ms to
live update, but due to this limitation i
On 2024/9/10 下午8:18, Xianglai Li wrote:
Added pch_pic interrupt controller for kvm emulation.
The main process is to send the command word for
creating an pch_pic device to the kernel,
Delivers the pch pic interrupt controller configuration
register base address to the kernel.
When the VM is s
On Wed, 11 Sept 2024 at 14:51, Michael S. Tsirkin wrote:
>
> The following changes since commit a66f28df650166ae8b50c992eea45e7b247f4143:
>
> Merge tag 'migration-20240909-pull-request' of
> https://gitlab.com/peterx/qemu into staging (2024-09-10 11:19:22 +0100)
>
> are available in the Git rep
On 2024/9/13 下午4:02, Markus Armbruster wrote:
Thomas Huth writes:
On 08/05/2024 05.11, Bibo Mao wrote:
On LoongArch system, there is only virt machine type now, name
LOONGARCH_MACHINE is confused, rename it with LOONGARCH_VIRT_MACHINE.
Machine name about Other real hw boards can be added i
On Fri, 13 Sept 2024 at 09:28, Markus Armbruster wrote:
>
> Peter Maydell writes:
>
> > On Tue, 3 Sept 2024 at 21:04, Philippe Mathieu-Daudé
> > wrote:
> >>
> >> sd_set_cb() was only used by omap2_mmc_init() which
> >> got recently removed. Time to remove it. For historical
> >> background on t
Peter Maydell writes:
> On Fri, 13 Sept 2024 at 09:28, Markus Armbruster wrote:
>>
>> Peter Maydell writes:
>>
>> > On Tue, 3 Sept 2024 at 21:04, Philippe Mathieu-Daudé
>> > wrote:
>> >>
>> >> sd_set_cb() was only used by omap2_mmc_init() which
>> >> got recently removed. Time to remove it. F
The 'reconnect' option only allows to specify the time in seconds,
which is way too long for certain workflows.
We have a lightweight disk backend server, which takes about 20ms to
live update, but due to this limitation in QEMU, previously the guest
disk controller would hang for one second becau
The description about virt machine type is removed by mistake, add
new description here. Here is output result with command
"./qemu-system-loongarch64 -M help"
Supported machines are:
none empty machine
virt QEMU LoongArch Virtual Machine (default)
x-remote
Fabiano Rosas writes:
> Peter Maydell writes:
>
>> On Fri, 6 Sept 2024 at 09:14, Daniel P. Berrangé wrote:
>>>
>>> On Fri, Sep 06, 2024 at 08:16:31AM +0200, Thomas Huth wrote:
>>> > On 05/09/2024 23.03, Fabiano Rosas wrote:
>>> > > Hi,
>>> > >
>>> > > This series silences QEMU stderr unless the
Elisha Hollander writes:
> weird...
Richard has posted some patches:
Message-ID: <20240910212351.977753-1-richard.hender...@linaro.org>
Date: Tue, 10 Sep 2024 14:23:49 -0700
Subject: [PATCH 0/2] tcg: Fix branch/label link during plugin expansion
From: Richard Henderson
which work for
On Fri, 13 Sept 2024 at 11:02, Markus Armbruster wrote:
>
> Fabiano Rosas writes:
> > I could add error/warn variants that are noop in case qtest is
> > enabled. It would, however, lead to this pattern which is discouraged by
> > the error.h documentation (+Cc Markus for advice):
> >
> > before:
On Fri, 13 Sep 2024 07:20:25 +0200
Mauro Carvalho Chehab wrote:
> Em Thu, 12 Sep 2024 14:42:33 +0200
> Igor Mammedov escreveu:
>
> > On Wed, 11 Sep 2024 16:34:36 +0100
> > Jonathan Cameron wrote:
> >
> > > On Wed, 11 Sep 2024 15:21:32 +0200
> > > Igor Mammedov wrote:
> > >
> > > > On Su
On Thu, 12 Sep 2024 14:38:26 +0100
Alireza Sanaee wrote:
> This commit adds IsDefined flag to the object and this helps in avoiding
> extra checks for every single layer of caches in both x86 and ARM.
Hi Ali,
You mention x86 here, but no code changes to support that?
Jonathan
>
> Signed-off-b
Richard Henderson writes:
> On 9/10/24 14:23, Richard Henderson wrote:
>> With tcg_last_op(), we always get the last op of the stream.
>> With TCGContext.emit_before_op, the most recently emitted op
>> is no longer the last op.
>> Instead, pass the op being emitted back from the allocator so
>> t
Richard Henderson writes:
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
On 13/09/2024 11.52, Bibo Mao wrote:
The description about virt machine type is removed by mistake, add
new description here. Here is output result with command
"./qemu-system-loongarch64 -M help"
Supported machines are:
none empty machine
virt QEMU LoongArch Virt
On Thu, 12 Sept 2024 at 06:30, Alistair Francis wrote:
>
> The following changes since commit a4eb31c678400472de0b4915b9154a7c20d8332f:
>
> Merge tag 'pull-testing-gdbstub-oct-100924-1' of
> https://gitlab.com/stsquad/qemu into staging (2024-09-11 13:17:29 +0100)
>
> are available in the Git re
This options has been removed at cb771ac1f5 (meson: Split
--enable-sanitizers to --enable-{asan, ubsan}, 2024-08-13), so let's
update its last standing mention in the docs.
Signed-off-by: Matheus Tavares Bernardino
---
In v2: fixed grammar typo and s/use-after-frees/uses-after-free/
v1:
https://
Peter Maydell writes:
> On Fri, 13 Sept 2024 at 11:02, Markus Armbruster wrote:
>>
>> Fabiano Rosas writes:
>> > I could add error/warn variants that are noop in case qtest is
>> > enabled. It would, however, lead to this pattern which is discouraged by
>> > the error.h documentation (+Cc Marku
Harsh Prateek Bora writes:
> This fix was earlier introduced for do_lstxv_D form with 2cc0e449d173
> however got missed for _X form. This patch fixes the same.
>
> Cc: qemu-sta...@nongnu.org
> Suggested-by: Fabiano Rosas
> Fixes: 70426b5bb738 ("target/ppc: moved stxvx and lxvx from legacy to
>
On Fri, 13 Sept 2024 at 12:29, Markus Armbruster wrote:
>
> Peter Maydell writes:
> > Specifically, if you don't disable the error-exit when qtest
> > is in use, then the generic qom-test tests which say "can we
> > at least instantiate every machine?" will fail, because they
> > assume that "qem
On Fri, Sep 06, 2024 at 10:52:53AM +0100, Peter Maydell wrote:
> On Fri, 6 Sept 2024 at 09:14, Daniel P. Berrangé wrote:
> >
> > On Fri, Sep 06, 2024 at 08:16:31AM +0200, Thomas Huth wrote:
> > > On 05/09/2024 23.03, Fabiano Rosas wrote:
> > > > Hi,
> > > >
> > > > This series silences QEMU stderr
On 13/09/2024 13.46, Peter Maydell wrote:
On Fri, 13 Sept 2024 at 12:29, Markus Armbruster wrote:
Peter Maydell writes:
Specifically, if you don't disable the error-exit when qtest
is in use, then the generic qom-test tests which say "can we
at least instantiate every machine?" will fail, be
On Thu, 12 Sept 2024 at 16:10, Peter Maydell wrote:
>
> The cross-i686-tci CI job is persistently flaky with various tests
> hitting timeouts. One theory for why this is happening is that we're
> running too many tests in parallel and so sometimes a test gets
> starved of CPU and isn't able to co
On Fri, 13 Sep 2024 11:13:00 +0100
Jonathan Cameron wrote:
> On Fri, 13 Sep 2024 07:20:25 +0200
> Mauro Carvalho Chehab wrote:
>
> > Em Thu, 12 Sep 2024 14:42:33 +0200
> > Igor Mammedov escreveu:
> >
> > > On Wed, 11 Sep 2024 16:34:36 +0100
> > > Jonathan Cameron wrote:
> > >
> > > >
On Fri, 13 Sep 2024, Harsh Prateek Bora wrote:
hreg_compute_hflags_value already stores msr locally to be used in most
of the logic in the routine however some instances are still using
env->msr which is unnecessary. Use locally stored value as available.
Reviewed-by: Nicholas Piggin
Reviewed
On Wed, 11 Sep 2024 11:09:21 +0800
Bibo Mao wrote:
> Macro definition is added for acpi sleep control register, so that
> ged emulation driver can use this, also it can be used in FDT table if
> ged is exposed with FDT table.
>
> Signed-off-by: Bibo Mao
> ---
> hw/acpi/generic_event_device.c
On Fri, 13 Sep 2024, Harsh Prateek Bora wrote:
As previously done for arch specific handlers, simplify var usage in
ppc_next_unmasked_interrupt by caching the env->pending_interrupts and
env->spr[SPR_LPCR] in local vars and using it later at multiple places.
Signed-off-by: Harsh Prateek Bora
--
On Tue, 10 Sep 2024, Michael S. Tsirkin wrote:
On Sat, Jun 29, 2024 at 10:01:52PM +0200, BALATON Zoltan wrote:
This is an alternative appriach to solve the qemu_irq leak in
vt82c686. Allowing embedding an irq and init it in place like done
with other objects may allow cleaner fix for similar iss
On 9/12/24 22:50, Michael Kowal wrote:
Some the functions that have been created are specific to a ring or context.
Some
of these same functions are being changed to operate on any ring/context. This
will
simplify the next patch sets that are adding additional ring/context operations.
Signed-
On 9/12/24 22:50, Michael Kowal wrote:
From: Glenn Miles
Adds support for single byte writes to offset 0xC38 of the TIMA address
space. When this offset is written to, the hardware disables the thread
context and copies the current state information to the odd cache line of
the pair specified
The System Control and Management Interface is specific to arm
machines, so don't include this device in non-arm targets.
Signed-off-by: Thomas Huth
---
hw/virtio/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/virtio/Kconfig b/hw/virtio/Kconfig
index aa63ff7fd4..b
Peter Xu writes:
> On Thu, Sep 12, 2024 at 03:43:39PM -0300, Fabiano Rosas wrote:
>> Peter Xu writes:
>>
>> Hi Peter, sorry if I'm not very enthusiastic by this, I'm sure you
>> understand the rework is a little frustrating.
>
> That's OK.
>
> [For some reason my email sync program decided to g
On 12-09-2024 22:25, Cédric Le Goater wrote:
Chalapthi,
On 8/7/24 22:28, Philippe Mathieu-Daudé wrote:
v2:
- Cover PowerNV SSI in MAINTAINERS
- Use GLib API in pnv_spi_xfer_buffer_free()
- Simplify returning early
Supersedes: <20240806134829.351703-3-chalapath...@linux.ibm.com>
I was wonde
On Fri, 13 Sep 2024 07:44:35 +0200
Mauro Carvalho Chehab wrote:
> Em Wed, 11 Sep 2024 15:51:08 +0200
> Igor Mammedov escreveu:
>
> > On Sun, 25 Aug 2024 05:45:56 +0200
> > Mauro Carvalho Chehab wrote:
> >
> > > Store HEST table address at GPA, placing its content at
> > > hest_addr_le varia
On Sun, 25 Aug 2024 05:45:58 +0200
Mauro Carvalho Chehab wrote:
> Now that we have also have a file to store HEST data location,
> which is part of GHES, better name the file where CPER records
> are stored.
>
> No functional changes.
>
> Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Igor
On Fri, 13 Sep 2024 11:21:28 +0100
Jonathan Cameron wrote:
> On Thu, 12 Sep 2024 14:38:26 +0100
> Alireza Sanaee wrote:
>
> > This commit adds IsDefined flag to the object and this helps in
> > avoiding extra checks for every single layer of caches in both x86
> > and ARM.
> Hi Ali,
>
> You
On Sun, 25 Aug 2024 05:45:59 +0200
Mauro Carvalho Chehab wrote:
> The current function used to generate GHES data is specific for
> memory errors. Give a better name for it, as we now have a generic
> function as well.
>
> Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Igor Mammedov
> ---
On Fri, 13 Sept 2024 at 13:24, Peter Maydell wrote:
>
> On Thu, 12 Sept 2024 at 16:10, Peter Maydell wrote:
> >
> > The cross-i686-tci CI job is persistently flaky with various tests
> > hitting timeouts. One theory for why this is happening is that we're
> > running too many tests in parallel a
On Thu, 12 Sept 2024 at 06:30, Richard Henderson
wrote:
>
> The following changes since commit a4eb31c678400472de0b4915b9154a7c20d8332f:
>
> Merge tag 'pull-testing-gdbstub-oct-100924-1' of
> https://gitlab.com/stsquad/qemu into staging (2024-09-11 13:17:29 +0100)
>
> are available in the Git r
On Thu, 12 Sept 2024 at 14:09, Song Gao wrote:
>
> The following changes since commit 4b7ea33074450bc6148c8e1545d78f179e64adb4:
>
> Merge tag 'pull-request-2024-09-11' of https://gitlab.com/thuth/qemu into
> staging (2024-09-11 19:28:23 +0100)
>
> are available in the Git repository at:
>
> h
Hello,
On 9/13/24 15:24, Chalapathi V wrote:
On 12-09-2024 22:25, Cédric Le Goater wrote:
Chalapthi,
On 8/7/24 22:28, Philippe Mathieu-Daudé wrote:
v2:
- Cover PowerNV SSI in MAINTAINERS
- Use GLib API in pnv_spi_xfer_buffer_free()
- Simplify returning early
Supersedes: <20240806134829.3517
On Thu, Sep 12, 2024 at 5:56 PM Cédric Le Goater wrote:
>
> Hello Jim,
>
> On 9/12/24 08:36, Jim Shu wrote:
> > Hi Cédric,
> >
> > Thank you very much for the quick response!
> >
> > I have checked the error API again. It seems to be my porting issue of
> > set_iommu_device() callback.
>
> Are you
On 13/09/2024 15.31, Peter Maydell wrote:
On Fri, 13 Sept 2024 at 13:24, Peter Maydell wrote:
On Thu, 12 Sept 2024 at 16:10, Peter Maydell wrote:
The cross-i686-tci CI job is persistently flaky with various tests
hitting timeouts. One theory for why this is happening is that we're
running
On Fri, Sep 13, 2024 at 02:31:34PM +0100, Peter Maydell wrote:
> On Fri, 13 Sept 2024 at 13:24, Peter Maydell wrote:
> >
> > On Thu, 12 Sept 2024 at 16:10, Peter Maydell
> > wrote:
> > >
> > > The cross-i686-tci CI job is persistently flaky with various tests
> > > hitting timeouts. One theory
On Fri, Sep 13, 2024 at 10:21:39AM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > On Thu, Sep 12, 2024 at 03:43:39PM -0300, Fabiano Rosas wrote:
> >> Peter Xu writes:
> >>
> >> Hi Peter, sorry if I'm not very enthusiastic by this, I'm sure you
> >> understand the rework is a little frustr
On Fri, 13 Sept 2024 at 15:05, Daniel P. Berrangé wrote:
>
> On Fri, Sep 13, 2024 at 02:31:34PM +0100, Peter Maydell wrote:
> > On Fri, 13 Sept 2024 at 13:24, Peter Maydell
> > wrote:
> > >
> > > On Thu, 12 Sept 2024 at 16:10, Peter Maydell
> > > wrote:
> > > >
> > > > The cross-i686-tci CI jo
On Thu, 12 Sept 2024 at 07:53, Philippe Mathieu-Daudé wrote:
>
> v2:
> - Fill Pierrick's commit description suggested by Eric Blake
> - Include TMP105 fixes from Guenter
>
> The following changes since commit a4eb31c678400472de0b4915b9154a7c20d8332f:
>
> Merge tag 'pull-testing-gdbstub-oct-10092
Hello,
+Mark (for the Mac devices)
On 9/9/24 22:11, Peter Xu wrote:
From: Mattias Nissler
When DMA memory can't be directly accessed, as is the case when
running the device model in a separate process without shareable DMA
file descriptors, bounce buffering is used.
It is not uncommon for de
On Fri, Sep 13, 2024 at 04:35:32PM +0200, Cédric Le Goater wrote:
> Hello,
>
> +Mark (for the Mac devices)
>
> On 9/9/24 22:11, Peter Xu wrote:
> > From: Mattias Nissler
> >
> > When DMA memory can't be directly accessed, as is the case when
> > running the device model in a separate process wi
The pci-bridge device is not usable on s390x, so introduce a Kconfig
switch that allows to disable it.
Signed-off-by: Thomas Huth
---
hw/pci-bridge/Kconfig | 5 +
hw/pci-bridge/meson.build | 2 +-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/pci-bridge/Kconfig b/hw/pc
On Thu, Sep 12, 2024 at 07:52:48PM -0300, Fabiano Rosas wrote:
> Fabiano Rosas writes:
>
> > Peter Xu writes:
> >
> >> On Thu, Sep 12, 2024 at 09:13:16AM +0100, Peter Maydell wrote:
> >>> On Wed, 11 Sept 2024 at 22:26, Fabiano Rosas wrote:
> >>> > I don't think we're discussing total CI time at
On Thu, Sep 12, 2024 at 04:14:20PM +0100, Peter Maydell wrote:
> On Thu, 12 Sept 2024 at 16:09, Peter Xu wrote:
> >
> > On Thu, Sep 12, 2024 at 09:13:16AM +0100, Peter Maydell wrote:
> > > On Wed, 11 Sept 2024 at 22:26, Fabiano Rosas wrote:
> > > > I don't think we're discussing total CI time at
Peter Xu writes:
> On Fri, Sep 13, 2024 at 10:21:39AM -0300, Fabiano Rosas wrote:
>> Peter Xu writes:
>>
>> > On Thu, Sep 12, 2024 at 03:43:39PM -0300, Fabiano Rosas wrote:
>> >> Peter Xu writes:
>> >>
>> >> Hi Peter, sorry if I'm not very enthusiastic by this, I'm sure you
>> >> understand t
Peter Xu writes:
> On Thu, Sep 12, 2024 at 07:52:48PM -0300, Fabiano Rosas wrote:
>> Fabiano Rosas writes:
>>
>> > Peter Xu writes:
>> >
>> >> On Thu, Sep 12, 2024 at 09:13:16AM +0100, Peter Maydell wrote:
>> >>> On Wed, 11 Sept 2024 at 22:26, Fabiano Rosas wrote:
>> >>> > I don't think we're
Rename the DeviceClass::reset field to legacy_reset; this is helpful
both in flagging up that it's best not used in new code and in
making it easy to search for where it's being used still.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-i
There are no callers of device_class_set_parent_reset() left in the tree,
as they've all been converted to use three-phase reset and the
corresponding resettable_class_set_parent_phases() function.
Remove device_class_set_parent_reset().
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-
Currently we have transitional machinery between legacy reset
and three phase reset that works in two directions:
* if you invoke three phase reset on a device which has set
the DeviceClass::legacy_reset method, we detect this in
device_get_transitional_reset() and arrange that we call
th
From: Danny Canter
This addition will be necessary for some HVF related work to follow.
For HVF on ARM there exists a set of APIs in macOS 13 to be able to
adjust the IPA size for a given VM. This is useful as by default HVF
uses 36 bits as the IPA size, so to support guests with > 64GB of RAM
we
Now that all devices which still implement a the legacy reset method
register it via device_class_legacy_reset(), we can simplify the
handling of these devices. Instead of using the complex
Resettable::get_transitional_function machinery, we register a hold
phase method which invokes the DeviceCla
.git
tags/pull-target-arm-20240913
for you to fetch changes up to 110684c9a69a02cbabfbddcd3afa921826ad565c:
hw/intc/arm_gic: fix spurious level triggered interrupts (2024-09-13 15:31:50
+0100)
target-arm queue:
* s390: convert s
From: Francisco Iglesias
Signed-off-by: Francisco Iglesias
Message-id: 20240906181645.40359-4-francisco.igles...@amd.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b9812d46525..b05
From: Alireza Sanaee
This patch allows for easier manipulation of the cache description
register, CCSIDR. Which is helpful for testing as well. Currently,
numbers get hard-coded and might be prone to errors.
Therefore, this patch adds a wrapper for different types of CPUs
available in tcg to dec
From: Danny Canter
This is preliminary work to split up hv_vm_create
logic per platform so we can support creating VMs
with > 64GB of RAM on Apple Silicon machines. This
is done via ARM HVF's hv_vm_config_create() (and
other APIs that modify this config that will be
coming in future patches). Thi
From: Doug Brown
The read index should not be changed when storing a new message into the
RX or TX FIFO. Changing it at this point will cause the reader to get
out of sync. The wrapping of the read index is already handled by the
pre-write functions for the FIFO status registers anyway.
Addition
From: Johannes Stoelp
Change the data type of the ioctl _request_ argument from 'int' to
'unsigned long' for the various accel/kvm functions which are
essentially wrappers around the ioctl() syscall.
The correct type for ioctl()'s 'request' argument is confused:
* POSIX defines the request argu
Convert the TYPE_CCW_DEVICE to three-phase reset. This is a
device class which is subclassed, so it needs to be three-phase
before we can convert the subclass.
Signed-off-by: Peter Maydell
Reviewed-by: Nina Schoetterl-Glausch
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Thomas Huth
Message-id
We used to need the transitional_function machinery to handle bus
classes and device classes which still used their legacy reset
handling. We have now converted all bus classes to three phase
reset, and simplified the device class legacy reset so it is just an
adapting wrapper function around regi
From: Francisco Iglesias
Vikram's email is bouncing, pause his maintainership until a new email is
provided.
Signed-off-by: Francisco Iglesias
Message-id: 20240906181645.40359-2-francisco.igles...@amd.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
MAINTAINERS | 2 --
1 file
Convert the s390 CPU to the Resettable interface. This is slightly
more involved than the other CPU types were (see commits
9130cade5fc22..d66e64dd006df) because S390 has its own set of
different kinds of reset with different behaviours that it needs to
trigger.
We handle this by adding these res
From: Doug Brown
The interrupt level should be 0 or 1. The existing code was using the
interrupt flags to determine the level. In the only machine currently
supported (xlnx-versal-virt), the GICv3 was masking off all bits except
bit 0 when applying it, resulting in the IRQ never being delivered.
Em Wed, 11 Sep 2024 17:01:57 +0200
Igor Mammedov escreveu:
> On Sun, 25 Aug 2024 05:45:57 +0200
> Mauro Carvalho Chehab wrote:
>
> > The current logic is based on a lot of duct tape, with
> > offsets calculated based on one define with the number of
> > source IDs and an enum.
> >
> > Rewrite
From: Doug Brown
Add support for QEMU_CAN_FRMF_ESI and QEMU_CAN_FRMF_BRS flags, and
ensure frame->flags is always initialized to 0.
Note that the Xilinx IP core doesn't allow manually setting the ESI bit
during transmits, so it's only implemented for the receive case.
Signed-off-by: Doug Brown
From: Doug Brown
The endianness of the CAN data was backwards in each group of 4 bytes.
For example, the following data:
00 11 22 33 44 55 66 77
was showing up like this:
33 22 11 00 77 66 55 44
Fix both the TX and RX code to put the data in the correct order.
Signed-off-by: Doug Brown
Revi
From: Doug Brown
Use QEMU's helper functions can_dlc2len() and can_len2dlc() for
translating between the raw DLC value and the SocketCAN length value.
This also has the side effect of correctly handling received CAN FD
frames with a DLC of 0-8, which was broken previously.
Signed-off-by: Doug Br
From: Doug Brown
Previously the emulated CAN ID register was being set to the exact same
value stored in qemu_can_frame.can_id. This doesn't work correctly
because the Xilinx IP core uses a different bit arrangement than
qemu_can_frame for all of its ID registers. Correct this problem for
both RX
Convert the virtio-ccw code to three-phase reset. This allows us to
remove a call to device_class_set_parent_reset(), replacing it with
the three-phase equivalent resettable_class_set_parent_phases().
Removing all the device_class_set_parent_reset() uses will allow us
to remove some of the glue co
Fabiano Rosas writes:
> Peter Xu writes:
>
>> On Thu, Sep 12, 2024 at 07:52:48PM -0300, Fabiano Rosas wrote:
>>> Fabiano Rosas writes:
>>>
>>> > Peter Xu writes:
>>> >
>>> >> On Thu, Sep 12, 2024 at 09:13:16AM +0100, Peter Maydell wrote:
>>> >>> On Wed, 11 Sept 2024 at 22:26, Fabiano Rosas w
From: Jan Klötzke
On GICv2 and later, level triggered interrupts are pending when either
the interrupt line is asserted or the interrupt was made pending by a
GICD_ISPENDRn write. Making a level triggered interrupt pending by
software persists until either the interrupt is acknowledged or cleared
The Alpha and HPPA CPU class structs include a 'parent_reset'
field which is never used; delete them.
(These targets don't seem to implement reset at all; if they did they
should do it using the three-phase reset mechanism, which uses a
'ResettablePhases parent_phases' field instead of the old
'De
From: Danny Canter
This patch's main focus is to use the previously added
hvf_get_physical_address_range to inform VM creation
about the IPA size we need for the VM, so we can extend
the default 36b IPA size and support VMs with 64+GB of
RAM. This is done by freezing the memory map, computing
the
From: Doug Brown
When checking the QEMU_CAN_FRMF_TYPE_FD flag, we need to ignore other
potentially set flags. Before this change, received CAN FD frames from
SocketCAN weren't being recognized as CAN FD.
Signed-off-by: Doug Brown
Reviewed-by: Pavel Pisa
Reviewed-by: Francisco Iglesias
Message
Define a device_class_set_legacy_reset() function which
sets the DeviceClass::reset field. This serves two purposes:
* it makes it clearer to the person writing code that
DeviceClass::reset is now legacy and they should look for
the new alternative (which is Resettable)
* it makes it easier
From: Francisco Iglesias
Update my xilinx.com email address to my amd.com address.
Signed-off-by: Francisco Iglesias
Message-id: 20240906181645.40359-3-francisco.igles...@amd.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1
On Fri, Sep 13, 2024 at 12:04:00PM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > On Fri, Sep 13, 2024 at 10:21:39AM -0300, Fabiano Rosas wrote:
> >> Peter Xu writes:
> >>
> >> > On Thu, Sep 12, 2024 at 03:43:39PM -0300, Fabiano Rosas wrote:
> >> >> Peter Xu writes:
> >> >>
> >> >> Hi P
On 9/13/2024 6:19 AM, Matheus Tavares Bernardino wrote:
This options has been removed at cb771ac1f5 (meson: Split
--enable-sanitizers to --enable-{asan, ubsan}, 2024-08-13), so let's
update its last standing mention in the docs.
Signed-off-by: Matheus Tavares Bernardino
---
In v2: fixed gramm
On Fri, Sep 13, 2024 at 12:17:40PM -0300, Fabiano Rosas wrote:
> Fabiano Rosas writes:
>
> > Peter Xu writes:
> >
> >> On Thu, Sep 12, 2024 at 07:52:48PM -0300, Fabiano Rosas wrote:
> >>> Fabiano Rosas writes:
> >>>
> >>> > Peter Xu writes:
> >>> >
> >>> >> On Thu, Sep 12, 2024 at 09:13:16AM
On 9/13/2024 8:10 AM, Cédric Le Goater wrote:
On 9/12/24 22:50, Michael Kowal wrote:
Some the functions that have been created are specific to a ring or
context. Some
of these same functions are being changed to operate on any
ring/context. This will
simplify the next patch sets that are add
On Thu, Sep 12, 2024 at 03:27:55PM +0100, Peter Maydell wrote:
> On Mon, 19 Aug 2024 at 14:56, Mattias Nissler wrote:
> >
> > When DMA memory can't be directly accessed, as is the case when
> > running the device model in a separate process without shareable DMA
> > file descriptors, bounce buffer
In XIVE Gen 2 there are many operations that were not modeled and are
needed for PowerVM. These changes are associated with the following Thread
Interrupt Management Area subjects:
- OS context
- Thread context
- Pulling contexts to 'cache lines'
- Pool targets
- Enhaced trace data for XIVE G
Some the functions that have been created are specific to a ring or context.
Some
of these same functions are being changed to operate on any ring/context. This
will
simplify the next patch sets that are adding additional ring/context operations.
Signed-off-by: Michael Kowal
---
include/hw/pp
From: Glenn Miles
Adds support for single byte writes to offset 0x15 of the TIMA address
space. This offset holds the Logical Server Group Size (LGS) field.
The field is used to evenly distribute the interrupt load among the
members of a group, but is unused in the current implementation so we
j
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