On 2024/9/5 12:05, Richard Henderson wrote:
On 9/4/24 07:27, LIU Zhiwei wrote:
From: Swung0x48
The RISC-V vector instruction set utilizes the LMUL field to group
multiple registers, enabling variable-length vector registers. This
implementation uses only the first register number of each gro
On Mon, Sep 9, 2024 at 6:33 PM Andrew Jones wrote:
>
> C doesn't extend the sign bit for unsigned types since there isn't a
> sign bit to extend. This means a promotion of a u32 to a u64 results
> in the upper 32 bits of the u64 being zero. If that result is then
> used as a mask on another u64 th
On 2024/9/5 14:39, Richard Henderson wrote:
On 9/4/24 07:27, LIU Zhiwei wrote:
@@ -811,31 +849,52 @@ static void tcg_out_extrl_i64_i32(TCGContext
*s, TCGReg ret, TCGReg arg)
tcg_out_ext32s(s, ret, arg);
}
-static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data,
-
On 2024/9/6 7:46, Alistair Francis wrote:
On Thu, Sep 5, 2024 at 12:29 AM LIU Zhiwei wrote:
From: TANG Tiancheng
Can you please mention RISC-V in the cover letter title. Otherwise
it's not obvious that this is RISC-V specific
Sorry. I miss it.
Thanks,
Zhiwei
Alistair
This patch set i
Hi Jason,
It seems this series wasn't applied successfully, I still cannot see it
from the latest tree. Any idea?
In any case the fix LGTM.
Reviewed-by: Si-Wei Liu
Thanks,
-Siwei
On 1/31/2024 9:43 PM, Jason Wang wrote:
On Mon, Jan 29, 2024 at 9:24 PM Eugenio Pérez wrote:
Commit a0d7215e
On Mon, Sep 9, 2024 at 6:33 PM Andrew Jones wrote:
>
> C doesn't extend the sign bit for unsigned types since there isn't a
> sign bit to extend. This means a promotion of a u32 to a u64 results
> in the upper 32 bits of the u64 being zero. If that result is then
> used as a mask on another u64 th
On Tue, Sep 10, 2024 at 11:41 AM Si-Wei Liu wrote:
>
> Hi Jason,
>
> It seems this series wasn't applied successfully, I still cannot see it
> from the latest tree. Any idea?
It breaks make check.
Eugenio, would you want to fix and resend the series?
Thanks
>
> In any case the fix LGTM.
>
> Re
[rth@cfarm120 bld]$ make check-functional
[1/2] Generating tests/functional/func-precache-m68k-m68k_nextcube with a custom command
(wrapped by meson to set env)
FAILED: tests/functional/m68k-m68k_nextcube.tstamp
env QEMU_TEST_PRECACHE=/home/rth/qemu/bld/tests/functional/m68k-m68k_nextcube.tstamp
When a new listener for an address space is registered, the hypervisor must be
informed of all existing eventfds for that address space by calling
eventfd_add() for that listener. Similarly, when a listener is de-registered
from an address space, the hypervisor must be informed of all existing even
On 2024/09/09 23:18, Joelle van Dyne wrote:
On Mon, Sep 9, 2024 at 12:36 AM Akihiko Odaki wrote:
On 2024/09/09 10:58, Joelle van Dyne wrote:
New optional argument for 'blockdev-change-medium' QAPI command to allow
the caller to specify if they wish to enable file locking.
Signed-off-by: Joel
On 9/9/24 19:46, LIU Zhiwei wrote:
lmul = type - riscv_lg2_vlenb;
if (lmul < -3) {
/* Host VLEN >= 1024 bits. */
vlmul = VLMUL_M1;
I am not sure if we should use VLMUL_MF8,
Perhaps. See below.
} else if (lmul < 3) {
/* 1/8 ... 1 ... 8 */
vlmul = l
On 9/9/24 10:40, Philippe Mathieu-Daudé wrote:
> Hi,
>
> (Cc'ing Arnaud & Inès who are listed as maintainers)
>
> On 6/9/24 18:12, Peter Maydell wrote:
>> On Mon, 2 Sept 2024 at 14:38, Jacob Abrams wrote:
>>>
>>> These changes allow the official STM32L4xx HAL UART driver to function
>>> prope
The current approach of using qemu_chr_fe_write() and ignoring the
return values results in dropped characters [1]. Ideally we want to
report FIFO status to the guest, but the HTIF isn't a real UART, so we
don't really have a way to do that.
Instead let's just use qemu_chr_fe_write_all() so at lea
This series fixes: https://gitlab.com/qemu-project/qemu/-/issues/2114
This converts the RISC-V charecter device callers of qemu_chr_fe_write()
to either use qemu_chr_fe_write_all() or to call qemu_chr_fe_write() async
and act on the return value.
v4:
- Drop the unused char_tx_time
- Update the
The current approach of using qemu_chr_fe_write() and ignoring the
return values results in dropped characters [1].
Let's update the SiFive UART to use a async sifive_uart_xmit() function
to transmit the characters and apply back pressure to the guest with
the SIFIVE_UART_TXFIFO_FULL status.
This
On Fri, Sep 6, 2024 at 7:50 PM Thomas Huth wrote:
>
> If QEMU has been configured with "--without-default-devices", the build
> is currently failing with:
>
> /usr/bin/ld: libqemu-riscv32-softmmu.a.p/target_riscv_cpu_helper.c.o:
> in function `riscv_cpu_do_interrupt':
> .../qemu/target/riscv/c
On Sat, Sep 7, 2024 at 6:24 AM Tomasz Jeznach wrote:
>
> The IMSIC state variable eistate[] is modified by CSR instructions
> within a range dedicated to the local CPU and by MMIO writes from any CPU.
> Access to eistate from MMIO accessors is protected by the BQL, but
> read-modify-write (RMW) se
Sorry for the delayed response, it seems I missed the email reply for
some reason during the long weekend.
On 9/2/2024 4:09 AM, Eugenio Perez Martin wrote:
On Fri, Aug 30, 2024 at 11:05 PM Si-Wei Liu wrote:
On 8/30/2024 1:05 AM, Eugenio Perez Martin wrote:
On Fri, Aug 30, 2024 at 6:20 AM S
GitHub's CodeQL reports four critical errors which are fixed by this commit:
Unsigned difference expression compared to zero
An expression (u - v > 0) with unsigned values u, v is only false if u == v,
so all changed expressions did not work as expected.
Signed-off-by: Stefan Weil
---
I do
On Tue, Sep 10, 2024 at 5:30 AM Peter Xu wrote:
> On Mon, Sep 09, 2024 at 10:25:36PM +0800, Hyman Huang wrote:
> > To activate the periodic CPU throttleing feature, introduce
> > the cpu-periodic-throttle.
> >
> > To control the frequency of throttling, introduce the
> > cpu-periodic-throttle-int
In order to reduce the maintenance work of QMP.
Given that the focus of this patchset is huge VM migration, is
it possible to enable or disable these two features with a single
parameter, such as "cpu-aggressive-throttle"?
Yong
On Mon, Sep 9, 2024 at 10:26 PM Hyman Huang wrote:
> To enable the
On Tue, Sep 10, 2024 at 7:30 AM Si-Wei Liu wrote:
>
> Sorry for the delayed response, it seems I missed the email reply for
> some reason during the long weekend.
>
> On 9/2/2024 4:09 AM, Eugenio Perez Martin wrote:
> > On Fri, Aug 30, 2024 at 11:05 PM Si-Wei Liu wrote:
> >>
> >>
> >> On 8/30/202
Hi Jacob,
On 10/9/24 06:34, Jacob Abrams wrote:
On 9/9/24 10:40, Philippe Mathieu-Daudé wrote:
Hi,
(Cc'ing Arnaud & Inès who are listed as maintainers)
On 6/9/24 18:12, Peter Maydell wrote:
On Mon, 2 Sept 2024 at 14:38, Jacob Abrams wrote:
These changes allow the official STM32L4xx HAL UA
On 10/9/24 05:58, Richard Henderson wrote:
[rth@cfarm120 bld]$ make check-functional
[1/2] Generating tests/functional/func-precache-m68k-m68k_nextcube with
a custom command (wrapped by meson to set env)
FAILED: tests/functional/m68k-m68k_nextcube.tstamp
env
QEMU_TEST_PRECACHE=/home/rth/qemu/b
Hi Zhou,
On 9/10/24 03:24, Zhou Wang via wrote:
> On 2024/9/9 22:31, Peter Maydell wrote:
>> On Mon, 9 Sept 2024 at 15:22, Zhou Wang via wrote:
>>> Hi All,
>>>
>>> When I tested mainline qemu(commit 7b87a25f49), it reports smmuv3 event 0x10
>>> during kernel booting up.
>> Does it still do this if
On 8/9/24 04:26, Richard Henderson wrote:
From: TANG Tiancheng
The loop in the 32-bit case of the vector compare operation
was incorrectly incrementing by 8 bytes per iteration instead
of 4 bytes. This caused the function to process only half of
the intended elements.
Cc: qemu-sta...@nongnu.or
On 8/9/24 04:26, Richard Henderson wrote:
Add declaration to tcg-internal.h, making it available for
use from tcg backend vector expanders.
Signed-off-by: Richard Henderson
---
tcg/tcg-internal.h | 2 ++
tcg/tcg-op-vec.c | 4 ++--
2 files changed, 4 insertions(+), 2 deletions(-)
Reviewe
On 8/9/24 04:26, Richard Henderson wrote:
Helper function to handle setting of VEXL based
on the type of the operation.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 38 +++---
1 file changed, 15 insertions(+), 23 deletions(-)
Reviewed-by:
301 - 328 of 328 matches
Mail list logo
