On 3/9/24 18:07, Peter Maydell wrote:
The omap_tap device is OMAP2 only, and we are removing it.
Signed-off-by: Peter Maydell
---
include/hw/arm/omap.h | 3 --
hw/misc/omap_tap.c| 117 --
hw/misc/meson.build | 1 -
3 files changed, 121 dele
On 3/9/24 18:07, Peter Maydell wrote:
The omap_l4 device is OMAP2 only, so we can remove it.
Signed-off-by: Peter Maydell
---
include/hw/arm/omap.h | 42 ---
hw/misc/omap_l4.c | 162 --
hw/misc/meson.build | 1 -
3 files changed, 205
On 3/9/24 18:07, Peter Maydell wrote:
The omap_dma4 device was only used in the OMAP2 SoC, which has
been removed.
Signed-off-by: Peter Maydell
---
include/hw/arm/omap.h | 1 -
hw/dma/omap_dma.c | 451 +-
2 files changed, 3 insertions(+), 449 de
On 3/9/24 18:07, Peter Maydell wrote:
Remove some defines and enums that are OMAP2 specific and
no longer used anywhere.
Signed-off-by: Peter Maydell
---
include/hw/arm/omap.h | 207 --
1 file changed, 207 deletions(-)
Reviewed-by: Philippe Mathieu-D
On Thu, Sep 05, 2024 at 04:45:48PM +0300, Avihai Horon wrote:
>
> On 27/08/2024 20:54, Maciej S. Szmigiero wrote:
> > External email: Use caution opening links or attachments
> >
> >
> > From: "Maciej S. Szmigiero"
> >
> > These SaveVMHandlers help device provide its own asynchronous
> > trans
On 3/9/24 18:07, Peter Maydell wrote:
Remove the OMAP2 specific code from omap_intc.c.
Signed-off-by: Peter Maydell
---
hw/intc/omap_intc.c | 276
1 file changed, 276 deletions(-)
-static const TypeInfo omap2_intc_info = {
-.name
On 5.09.2024 15:45, Avihai Horon wrote:
On 27/08/2024 20:54, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
From: "Maciej S. Szmigiero"
These SaveVMHandlers help device provide its own asynchronous
transmission of the remaining data at the end of a preco
On 5.09.2024 16:15, Avihai Horon wrote:
On 27/08/2024 20:54, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
From: "Maciej S. Szmigiero"
qemu_loadvm_load_state_buffer() and its load_state_buffer
SaveVMHandler allow providing device state buffer to explici
On 5.09.2024 15:08, Avihai Horon wrote:
Hi Maciej,
On 27/08/2024 20:54, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
From: "Maciej S. Szmigiero"
This way both the start and end points of migrating a particular VFIO
device are known.
Add also a vfio_sa
On 5.09.2024 17:13, Avihai Horon wrote:
On 27/08/2024 20:54, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
From: "Maciej S. Szmigiero"
load_finish SaveVMHandler allows migration code to poll whether
a device-specific asynchronous device state loading op
On 5.09.2024 18:47, Avihai Horon wrote:
On 27/08/2024 20:54, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
From: "Maciej S. Szmigiero"
Add a basic support for receiving device state via multifd channels -
channels that are shared with RAM transfers.
To
On 9.09.2024 10:55, Avihai Horon wrote:
On 27/08/2024 20:54, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
From: "Maciej S. Szmigiero"
The multifd received data needs to be reassembled since device state
packets sent via different multifd channels can a
From: Carl Hauser
Add support for, and migrate, a single-entry fp
instruction queue for sparc32.
Signed-off-by: Carl Hauser
[rth: Split from a larger patch;
adjust representation with union;
add migration state]
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Changes for v5:
- Fix stdfq advance_pc.
r~
Carl Hauser (2):
target/sparc: Add FQ and FSR.QNE
target/sparc: Populate sparc32 FQ when raising fp exception
Richard Henderson (3):
target/sparc: Add FSR_QNE to tb_flags
target/sparc: Implement STDFQ
target/sparc: Add gen_trap_if_nofpu_fpex
Signed-off-by: Richard Henderson
---
target/sparc/cpu.h | 8 +++-
target/sparc/translate.c | 10 +++---
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 9f2bc44722..f517e5a383 100644
--- a/target/sparc/cpu.h
+++ b/target/
From: Carl Hauser
Implement a single instruction floating point queue,
populated while delivering an fp exception.
Signed-off-by: Carl Hauser
[rth: Split from a larger patch]
Signed-off-by: Richard Henderson
---
target/sparc/int32_helper.c | 40 +++--
1 file ch
Invalid encoding of addr should raise TT_ILL_INSN, so
check before supervisor, which might raise TT_PRIV_INSN.
Clear QNE after execution.
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 28 ++--
target/sparc/insns.decode | 2 +-
2 files changed, 27 inser
Model fp_exception state, in which only fp stores are allowed
until such time as the FQ has been flushed.
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 90 +++-
1 file changed, 61 insertions(+), 29 deletions(-)
diff --git a/target/sparc/tran
On 9.09.2024 13:41, Avihai Horon wrote:
On 27/08/2024 20:54, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
From: "Maciej S. Szmigiero"
Implement the multifd device state transfer via additional per-device
thread inside save_live_complete_precopy_thread
On 9/9/24 02:53, Philippe Mathieu-Daudé wrote:
@@ -3145,6 +3153,13 @@ static void tcg_out_cmp_vec_k1(TCGContext *s, TCGType type,
unsigned vece,
{ OPC_VPCMPB, OPC_VPCMPW, OPC_VPCMPD, OPC_VPCMPQ },
{ OPC_VPCMPUB, OPC_VPCMPUW, OPC_VPCMPUD, OPC_VPCMPUQ }
};
+ static con
On Mon, 9 Sept 2024 at 18:25, Philippe Mathieu-Daudé wrote:
>
> Hi Peter,
>
> On 9/9/24 15:44, Peter Maydell wrote:
> > On Mon, 9 Sept 2024 at 14:41, Philippe Mathieu-Daudé
> > wrote:
> >>
> >> Hi,
> >>
> >> On 3/9/24 18:06, Peter Maydell wrote:
> >>> This patchset removes the various Arm machin
On 9.09.2024 19:59, Peter Xu wrote:
On Thu, Sep 05, 2024 at 04:45:48PM +0300, Avihai Horon wrote:
On 27/08/2024 20:54, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
From: "Maciej S. Szmigiero"
These SaveVMHandlers help device provide its own asynchrono
On 9.09.2024 18:45, Peter Xu wrote:
Hi, Stefan, Maciej,
Sorry to be slow on responding.
On Tue, Sep 03, 2024 at 03:04:54PM -0400, Stefan Hajnoczi wrote:
On Tue, 3 Sept 2024 at 12:54, Maciej S. Szmigiero
wrote:
On 3.09.2024 15:55, Stefan Hajnoczi wrote:
On Tue, 27 Aug 2024 at 13:58, Maciej
On 9/9/24 03:00, Alex Bennée wrote:
Pierrick Bouvier writes:
On 9/5/24 08:21, Alex Bennée wrote:
Pierrick Bouvier writes:
This series allows plugins to know which value is read/written during a memory
access.
For every memory access, we know copy this value before calling mem callbacks,
a
On Mon, Sep 09, 2024 at 08:32:45PM +0200, Maciej S. Szmigiero wrote:
> On 9.09.2024 19:59, Peter Xu wrote:
> > On Thu, Sep 05, 2024 at 04:45:48PM +0300, Avihai Horon wrote:
> > >
> > > On 27/08/2024 20:54, Maciej S. Szmigiero wrote:
> > > > External email: Use caution opening links or attachments
On Mon, Sep 09, 2024 at 08:38:45PM +0200, Maciej S. Szmigiero wrote:
> On 9.09.2024 18:45, Peter Xu wrote:
> > Hi, Stefan, Maciej,
> >
> > Sorry to be slow on responding.
> >
> > On Tue, Sep 03, 2024 at 03:04:54PM -0400, Stefan Hajnoczi wrote:
> > > On Tue, 3 Sept 2024 at 12:54, Maciej S. Szmigie
On 9.09.2024 21:12, Peter Xu wrote:
On Mon, Sep 09, 2024 at 08:38:45PM +0200, Maciej S. Szmigiero wrote:
On 9.09.2024 18:45, Peter Xu wrote:
Hi, Stefan, Maciej,
Sorry to be slow on responding.
On Tue, Sep 03, 2024 at 03:04:54PM -0400, Stefan Hajnoczi wrote:
On Tue, 3 Sept 2024 at 12:54, Maci
On Mon, Sep 09, 2024 at 09:16:32PM +0200, Maciej S. Szmigiero wrote:
> So, if I understand your design correctly, you want to basically wrap
> the Glib's GThreadPool into some QEMU GenericThreadPool and then use the
> later in multifd code, right?
Yes. I didn't have an explicit picture yet in min
On Mon, Sep 09, 2024 at 03:08:40PM -0400, Peter Xu wrote:
> On Mon, Sep 09, 2024 at 08:32:45PM +0200, Maciej S. Szmigiero wrote:
> > On 9.09.2024 19:59, Peter Xu wrote:
> > > On Thu, Sep 05, 2024 at 04:45:48PM +0300, Avihai Horon wrote:
> > > >
> > > > On 27/08/2024 20:54, Maciej S. Szmigiero wrot
Am 09.09.24 um 09:26 schrieb Marc-André Lureau:
> Hi
>
> On Mon, Sep 9, 2024 at 10:22 AM Volker Rümelin wrote:
>> Windows only:
>>
>> The libSDL2 Windows message loop needs the libSDL2 Windows low
>> level keyboard hook procedure to grab the left and right Windows
>> keys correctly. Reenable the S
On Fri, Aug 30, 2024 at 10:02:40AM -0300, Fabiano Rosas wrote:
> >>> @@ -397,20 +404,16 @@ bool multifd_send(MultiFDSendData **send_data)
> >>>
> >>> p = &multifd_send_state->params[i];
> >>> /*
> >>> - * Lockless read to p->pending_job is safe, because only multifd
>
On Mon, Sep 02, 2024 at 10:12:01PM +0200, Maciej S. Szmigiero wrote:
> > > diff --git a/migration/multifd.h b/migration/multifd.h
> > > index a3e35196d179..a8f3e4838c01 100644
> > > --- a/migration/multifd.h
> > > +++ b/migration/multifd.h
> > > @@ -45,6 +45,12 @@ MultiFDRecvData *multifd_get_recv_
On Tue, Aug 27, 2024 at 07:54:27PM +0200, Maciej S. Szmigiero wrote:
> From: "Maciej S. Szmigiero"
>
> load_finish SaveVMHandler allows migration code to poll whether
> a device-specific asynchronous device state loading operation had finished.
>
> In order to avoid calling this handler needless
From: Bryan Zhang
Adds an integration test for 'qatzip'.
Reviewed-by: Fabiano Rosas
Signed-off-by: Bryan Zhang
Signed-off-by: Hao Xiang
Signed-off-by: Yichen Wang
Link: https://lore.kernel.org/r/20240830232722.58272-6-yichen.w...@bytedance.com
Signed-off-by: Peter Xu
---
tests/qtest/migrat
From: Bryan Zhang
Add a 'qatzip' feature, which is automatically disabled, and which
depends on the QATzip library if enabled.
Reviewed-by: Fabiano Rosas
Signed-off-by: Bryan Zhang
Signed-off-by: Hao Xiang
Signed-off-by: Yichen Wang
Link: https://lore.kernel.org/r/20240830232722.58272-3-yich
From: David Hildenbrand
As reported by Peter, we might be leaking memory when removing the
highest RAMBlock (in the weird ram_addr_t space), and adding a new one.
We will fail to realize that we already allocated bitmaps for more
dirty memory blocks, and effectively discard the pointers to them.
From: Yuan Liu
add Intel QATzip compression method introduction
Reviewed-by: Nanhai Zou
Reviewed-by: Peter Xu
Reviewed-by: Fabiano Rosas
Signed-off-by: Yuan Liu
Signed-off-by: Yichen Wang
Link: https://lore.kernel.org/r/20240830232722.58272-2-yichen.w...@bytedance.com
Signed-off-by: Peter X
The following changes since commit f2aee60305a1e40374b2fc1093e4d04404e780ee:
Merge tag 'pull-request-2024-09-08' of https://gitlab.com/huth/qemu into
staging (2024-09-09 10:47:24 +0100)
are available in the Git repository at:
https://gitlab.com/peterx/qemu.git tags/migration-202
From: "Denis V. Lunev"
Right now migration_throttle() tracepoint lacks very important
important information, i.e. no one could easily say how much the guest
is throttled. This makes difficult to debug guest quality of service
during migration.
This patch adds one more tracepoint into cpu_throttl
From: Bryan Zhang
Adds support for 'qatzip' as an option for the multifd compression
method parameter, and implements using QAT for 'qatzip' compression and
decompression.
Acked-by: Markus Armbruster
Reviewed-by: Fabiano Rosas
Reviewed-by: Prasad Pandit
Signed-off-by: Bryan Zhang
Signed-off-
From: Mattias Nissler
When DMA memory can't be directly accessed, as is the case when
running the device model in a separate process without shareable DMA
file descriptors, bounce buffering is used.
It is not uncommon for device models to request mapping of several DMA
regions at the same time.
From: Fabiano Rosas
The vmstate-checker-script test has a bug that makes it flaky. It was
also committed by mistake and will be removed.
Since the migration-compat job takes the tests from the build-previous
job instead of the current HEAD, neither a fix or a removal of the
test will take effect
From: Bryan Zhang
Adds support for migration parameters to control QATzip compression
level.
Acked-by: Markus Armbruster
Signed-off-by: Bryan Zhang
Signed-off-by: Hao Xiang
Signed-off-by: Yichen Wang
Reviewed-by: Fabiano Rosas
Reviewed-by: Prasad Pandit
Link: https://lore.kernel.org/r/2024
On Mon, Sep 09, 2024 at 07:34:45PM +0800, Changqi Lu wrote:
> +static int coroutine_fn GRAPH_RDLOCK
> +raw_co_pr_register(BlockDriverState *bs, uint64_t old_key,
> + uint64_t new_key, BlockPrType type,
> + bool ptpl, bool ignore_key)
> +{
> +return bdrv_co_pr
Pierrick Bouvier writes:
> On 9/9/24 03:00, Alex Bennée wrote:
>> Pierrick Bouvier writes:
>>
>>> On 9/5/24 08:21, Alex Bennée wrote:
Pierrick Bouvier writes:
> This series allows plugins to know which value is read/written during a
> memory
> access.
>
> For eve
GitHub's CodeQL reports a critical error which is fixed by using the MIN macro:
Unsigned difference expression compared to zero
Signed-off-by: Stefan Weil
---
net/colo-compare.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/net/colo-compare.c b/net/colo-compare.c
ind
From: Frederic Barrat
Adds support for single byte writes to offset 0xC18 of the TIMA address
space. When this offset is written to, the hardware disables the OS
context and copies the current state information to the odd cache line
of the pair specified by the NVT structure indexed by the OS CA
From: Frederic Barrat
The 'PGoFirst' field of a Notify Virtual Processor tells if the NVP
belongs to a VP group.
Also, print the Reporting Cache Line address, if defined.
Signed-off-by: Frederic Barrat
Signed-off-by: Michael Kowal
---
include/hw/ppc/xive2_regs.h | 1 +
hw/intc/xive2.c
From: Michael Kowal
Making some pre-requisite alignment changes ahead of the following patch
sets. Making these changes now will ease the review of the patch sets.
Checkpatch wants the closing comment '*/' on a separate line, unless it is
on the same line as the starting comment '/*'.
There ar
From: Frederic Barrat
The 'info pic' HMP command dumps the state of the interrupt controller.
Add the dump of the NVG and NVC tables to its output to ease debug.
Signed-off-by: Frederic Barrat
Signed-off-by: Michael Kowal
---
include/hw/ppc/xive2.h | 12
include/hw/ppc/xive2_reg
From: Glenn Miles
Adds support for single byte read of offset 0x838 of the TIMA address
space. According to the XIVE2 Specification, this causes the hardware
to atomically:
1. Read the number of bytes requested (lbz or lhz are supported).
2. Reset the valid bit of the thread context.
3. Re
Some the functions that have been created are specific to a ring or context.
Some
of these same functions are being changed to operate on any ring/context. This
will
simplify the next patch sets that are adding additional ring/context operations.
Signed-off-by: Michael Kowal
---
include/hw/pp
From: Glenn Miles
When running PowerVM, the console is littered with XIVE traces regarding
invalid writes to TIMA address 0x100b6 due to a lack of support for writes
to the "TARGET" field which was added for XIVE GEN2. To fix this, we add
special op support for 1-byte writes to this field.
Sign
From: Glenn Miles
Hypervisor "pool" targets do not get their own interrupt line and instead
must share an interrupt line with the hypervisor "physical" targets.
This also means that the pool ring must use some of the registers from the
physical ring in the TIMA. Specifically, the NSR, PIPR and C
From: Glenn Miles
PHYP uses 8-byte writes to the 2nd doubleword of the OS context
line when dispatching an OS level virtual processor. This
support was not used by OPAL/Linux and so was never added.
Without this support, the XIVE code doesn't notice that a new
context is being pushed and fails
In XIVE Gen 2 there are many operations that were not modeled and are
needed for PowerVM. These changes are associated with the following Thread
Interrupt Management Area subjects:
- OS context
- Thread context
- Pulling contexts to 'cache lines'
- Pool targets
- Enhaced trace data for XIVE G
Some of the TIMA Special CI operations perform the same operation at
alternative byte offsets and lengths. The following
xive2_tm_opertions[] table entries are missing when they exist for
other offsets/sizes and have been added:
- lwz@0x810 Pull/Invalidate O/S Context to registeradded
lwz@0x
From: Frederic Barrat
The OGEN field at offset 0x1F is a new field for Gen2 TIMA. This
patch defines it.
Signed-off-by: Frederic Barrat
Signed-off-by: Michael Kowal
Reviewed-by: Cédric Le Goater
---
include/hw/ppc/xive_regs.h | 1 +
hw/intc/xive.c | 4
2 files changed, 5 ins
From: Glenn Miles
Adds support for single byte writes to offset 0x15 of the TIMA address
space. This offset holds the Logical Server Group Size (LGS) field.
The field is used to evenly distribute the interrupt load among the
members of a group, but is unused in the current implementation so we
j
From: Glenn Miles
Current code was updating the PIPR inside the xive_tctx_accept() function
instead of the xive_tctx_set_cppr function, which is where the HW would
have it updated.
Moved the update to the xive_tctx_set_cppr function which required
additional support for pool interrupts.
Fixes:
From: Glenn Miles
Adds support for single byte writes to offset 0xC38 of the TIMA address
space. When this offset is written to, the hardware disables the thread
context and copies the current state information to the odd cache line of
the pair specified by the NVT structure indexed by the THREA
On Mon, Sep 09, 2024 at 10:25:36PM +0800, Hyman Huang wrote:
> To activate the periodic CPU throttleing feature, introduce
> the cpu-periodic-throttle.
>
> To control the frequency of throttling, introduce the
> cpu-periodic-throttle-interval.
>
> Signed-off-by: Hyman Huang
Considering that I w
On 9/9/24 13:21, Alex Bennée wrote:
Pierrick Bouvier writes:
On 9/9/24 03:00, Alex Bennée wrote:
Pierrick Bouvier writes:
On 9/5/24 08:21, Alex Bennée wrote:
Pierrick Bouvier writes:
This series allows plugins to know which value is read/written during a memory
access.
For every memor
Peter Xu writes:
> On Mon, Sep 09, 2024 at 03:02:57PM +0100, Peter Maydell wrote:
>> On Mon, 9 Sept 2024 at 14:51, Hyman Huang wrote:
>> >
>> > Despite the fact that the responsive CPU throttle is enabled,
>> > the dirty sync count may not always increase because this is
>> > an optimization tha
On 9/9/24 20:07, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/sparc/cpu.h | 8 +++-
target/sparc/translate.c | 10 +++---
2 files changed, 14 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 9/9/24 19:28, Richard Henderson wrote:
Call cpu_m68k_set_fpcr to make sure softfloat internals
are up-to-date with the restored FPCR.
Signed-off-by: Richard Henderson
---
target/m68k/cpu.c | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Philippe Mathieu-Daudé
On 9/9/24 19:28, Richard Henderson wrote:
This will enable further cleanups further down the call chain.
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 24 ++--
1 file changed, 10 insertions(+), 14 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 9/9/24 19:28, Richard Henderson wrote:
The mode argument is extracted from 3 bits, and all cases are covered.
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 9/9/24 19:28, Richard Henderson wrote:
Use the env pointer in DisasContext.
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 9/9/24 19:28, Richard Henderson wrote:
Use the env pointer in DisasContext.
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 9/9/24 19:28, Richard Henderson wrote:
Use the env pointer in DisasContext.
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 23 +++
1 file changed, 11 insertions(+), 12 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 9/9/24 19:28, Richard Henderson wrote:
Use the env pointer in DisasContext.
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 31 ---
1 file changed, 12 insertions(+), 19 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 9/9/24 19:28, Richard Henderson wrote:
Use the env pointer in DisasContext.
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 21 ++---
1 file changed, 10 insertions(+), 11 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 9/9/24 19:28, Richard Henderson wrote:
Replace with gen_load_mode_fp and gen_store_mode_fp.
Return bool for success from the new functions.
Remove gen_ldst_fp and ea_what as unused.
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 125 +---
On 9/9/24 19:28, Richard Henderson wrote:
Move the exception to be raised into the helpers.
This in preparation for raising other exceptions,
and still wanting to return failure.
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 10 ++
1 file changed, 6 insertions(+), 4
On 9/9/24 19:28, Richard Henderson wrote:
This enables the exceptions raised by the actual load
to be reflected as a failure.
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 104
1 file changed, 51 insertions(+), 53 deletions(-)
Revie
On 9/9/24 19:28, Richard Henderson wrote:
This enables the exceptions raised by the actual store
to be reflected as a failure.
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 107
1 file changed, 53 insertions(+), 54 deletions(-)
Revi
On 9/9/24 19:28, Richard Henderson wrote:
These need not be exported beyond cpu.c.
Fix a typo in vmstate_fpu.
Signed-off-by: Richard Henderson
---
target/m68k/cpu.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 9/9/24 18:22, Richard Henderson wrote:
The extract2 tcg op performs the same operation
as the do_ext64 function.
I remember this one:
https://lore.kernel.org/qemu-devel/60f76a76-709a-4f32-974c-c771a724d...@linaro.org/
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
targ
On 9/9/24 18:22, Richard Henderson wrote:
Pre-reviewed:
https://lore.kernel.org/qemu-devel/10eb7805-6de3-45ec-8d2a-f5af5f635...@linaro.org/
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 121 +
target/arm/tcg
Reviewed:
https://lore.kernel.org/qemu-devel/37096dc8-7827-4a4c-a27b-4f8343aa9...@linaro.org/
On 9/9/24 18:22, Richard Henderson wrote:
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 47 ++
target/arm/tcg/a64.
On 9/9/24 18:22, Richard Henderson wrote:
Reviewed-by: Peter Maydell
I wonder, maybe you mispasted my previous R-b tags
with Peter's?
https://lore.kernel.org/qemu-devel/37096dc8-7827-4a4c-a27b-4f8343aa9...@linaro.org/
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 7
Nicholas Piggin writes:
> The move to decodetree flipped the inequality test for the VEC / VSX
> MSR facility check.
>
> This caused application crashes under Linux, where these facility
> unavailable interrupts are used for lazy-switching of VEC/VSX register
> sets. Getting the incorrect interru
From: Richard Henderson
To simplify the following commits, rename 't' as 't2'.
Signed-off-by: Richard Henderson
Message-ID: <20240605215739.4758-7-richard.hender...@linaro.org>
[PMD: Split patch, part 1/4]
Signed-off-by: Philippe Mathieu-Daudé
---
target/s390x/tcg/translate.c | 21 +++
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID: <20240605215739.4758-7-richard.hender...@linaro.org>
[PMD: Split patch, part 3/4]
Signed-off-by: Philippe Mathieu-Daudé
---
target/s390x/tcg/translate.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --gi
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID: <20240605215739.4758-7-richard.hender...@linaro.org>
[PMD: Split patch, part 4/4]
Signed-off-by: Philippe Mathieu-Daudé
---
target/s390x/tcg/translate.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff -
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID: <20240605215739.4758-7-richard.hender...@linaro.org>
[PMD: Split patch, part 2/4]
Signed-off-by: Philippe Mathieu-Daudé
---
target/s390x/tcg/translate.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff
On Wed, Jul 17, 2024 at 7:41 AM Fabiano Rosas wrote:
>
> Yichen Wang writes:
>
> > From: Hao Xiang
> >
> > Multifd sender path gets an array of pages queued by the migration
> > thread. It performs zero page checking on every page in the array.
> > The pages are classfied as either a zero page o
On 9/7/24 19:26, Richard Henderson wrote:
In order for that to happen, the tcg/i386 backend must be changed
so that it does not rely upon choices that it made during early
expansion, before optimization changes things.
FYI, tcg/ppc and tcg/s390x need similar changes.
But that doesn't affect rev
On 9/9/24 16:19, Philippe Mathieu-Daudé wrote:
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID: <20240605215739.4758-7-richard.hender...@linaro.org>
[PMD: Split patch, part 2/4]
Signed-off-by: Philippe Mathieu-Daudé
---
target/s390x/tcg/translate.c | 12
1
On 9/9/24 16:19, Philippe Mathieu-Daudé wrote:
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID: <20240605215739.4758-7-richard.hender...@linaro.org>
[PMD: Split patch, part 3/4]
Signed-off-by: Philippe Mathieu-Daudé
---
target/s390x/tcg/translate.c | 8 +---
1 file
On 2024/9/5 14:56, Richard Henderson wrote:
On 9/4/24 07:27, LIU Zhiwei wrote:
@@ -698,6 +704,21 @@ static bool tcg_out_mov(TCGContext *s, TCGType
type, TCGReg ret, TCGReg arg)
case TCG_TYPE_I64:
tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0);
break;
+ case TCG_TYPE_V6
On 2024/9/5 15:12, Richard Henderson wrote:
On 9/4/24 07:27, LIU Zhiwei wrote:
@@ -2322,6 +2411,51 @@ static void tcg_out_vec_op(TCGContext *s,
TCGOpcode opc,
riscv_set_vec_config_vl(s, type);
tcg_out_opc_vi(s, OPC_VXOR_VI, a0, a1, -1, true);
break;
+ case IND
On 2024/9/9 22:31, Peter Maydell wrote:
> On Mon, 9 Sept 2024 at 15:22, Zhou Wang via wrote:
>>
>> Hi All,
>>
>> When I tested mainline qemu(commit 7b87a25f49), it reports smmuv3 event 0x10
>> during kernel booting up.
>
> Does it still do this if you either:
> (1) use the v9.1.0 release (commit
On 2024/9/9 22:47, Mostafa Saleh wrote:
> Hi Zhou,
>
> On Mon, Sep 9, 2024 at 3:22 PM Zhou Wang via wrote:
>>
>> Hi All,
>>
>> When I tested mainline qemu(commit 7b87a25f49), it reports smmuv3 event 0x10
>> during kernel booting up.
>>
>> qemu command which I use is as below:
>>
>> qemu-system-aa
On 9/10/24 04:18, Keith Busch wrote:
On Mon, Sep 09, 2024 at 07:34:45PM +0800, Changqi Lu wrote:
+static int coroutine_fn GRAPH_RDLOCK
+raw_co_pr_register(BlockDriverState *bs, uint64_t old_key,
+ uint64_t new_key, BlockPrType type,
+ bool ptpl, bool ignore
On 2024/9/9 下午9:13, gaosong wrote:
在 2024/9/9 下午7:52, gaosong 写道:
在 2024/9/4 下午2:18, Bibo Mao 写道:
Six registers scr0 - scr3, eflags and ftop are added in percpu vmstate.
And two functions kvm_loongarch_get_lbt/kvm_loongarch_put_lbt are added
to save/restore lbt registers.
Signed-off-by: B
> -Original Message-
> From: Stefan Weil
> Sent: Tuesday, September 10, 2024 4:43 AM
> To: Zhang, Chen ; Li Zhijian ;
> Jason Wang
> Cc: qemu-devel@nongnu.org; Stefan Weil
> Subject: [PATCH] Fix calculation of minimum in colo_compare_tcp
>
> GitHub's CodeQL reports a critical error w
On 2024/9/5 14:03, Richard Henderson wrote:
On 9/4/24 07:27, LIU Zhiwei wrote:
From: TANG Tiancheng
In RISC-V, vector operations require initial configuration using
the vset{i}vl{i} instruction.
This instruction:
1. Sets the vector length (vl) in bytes
2. Configures the vtype register
On 2024/9/9 23:45, Richard Henderson wrote:
On 9/9/24 00:18, LIU Zhiwei wrote:
On 2024/9/5 11:34, Richard Henderson wrote:
On 9/4/24 07:27, LIU Zhiwei wrote:
+ if (info & CPUINFO_ZVE64X) {
+ /*
+ * Get vlenb for Vector: vsetvli rd, x0, e64.
+ * VLMAX = LMUL * VLEN
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