Before seeing Alex's suggestion, I didn't realize that we could use the
existing injection mechanism to enable plugins to count instructions
accurately.
Now, I also agree that the new API introduced by this patch for the
plugin subsystem could make the plugin API overly complex.
Many thanks
Sure!
`build/qemu-system-i386 -plugin build/contrib/plugins/libips.so,ips=1
-display curses -bios bios.raw`
Also, I just tested with 9.1.0-rc4 and it resulted with
`tcg.c:3167:remove_label_use: code should not be reached`
On Mon, Sep 2, 2024, 16:08 Alex Bennée wrote:
> Elisha Hollander writes
On 9/3/24 05:06, Jamin Lin wrote:
Hi Cedric,
Subject: Re: [PATCH v2 07/11] hw/i2c/aspeed: support high part dram offset for
DMA 64 bits
Jamin,
Please adjust commit title
What do you think if I change the commit title as following.
hw/i2c/aspeed: Add support for dma_dram_offset attribute bi
Hi Cedric,
> Subject: Re: [PATCH v2 07/11] hw/i2c/aspeed: support high part dram offset for
> DMA 64 bits
>
> On 9/3/24 05:06, Jamin Lin wrote:
> > Hi Cedric,
> >
> >> Subject: Re: [PATCH v2 07/11] hw/i2c/aspeed: support high part dram
> >> offset for DMA 64 bits
> >>
> >> Jamin,
> >>
> >> Please
On Tue, Aug 6, 2024 at 5:09 AM Octavian Purdila wrote:
> Add path option to the pty char backend which will create a symbolic
> link to the given path that points to the allocated PTY.
>
> This avoids having to make QMP or HMP monitor queries to find out what
> the new PTY device path is.
>
> Bas
is_host_cpu_intel() returns TRUE if the host cpu in Intel based. RAPL needs
Intel host cpus. If the host CPU is not Intel baseed, we should report error.
Fix the check accordingly.
Signed-off-by: Ani Sinha
---
target/i386/kvm/kvm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --gi
On 9/3/24 09:19, Ani Sinha wrote:
is_host_cpu_intel() returns TRUE if the host cpu in Intel based. RAPL needs
Intel host cpus. If the host CPU is not Intel baseed, we should report error.
Fix the check accordingly.
Signed-off-by: Ani Sinha
It's the function that is returning the incorrect val
On 02/09/2024 21:38, Philippe Mathieu-Daudé wrote:
> On 30/8/24 13:57, Clément Léger wrote:
>> On 30/08/2024 13:31, Michael Tokarev wrote:
>>> 30.08.2024 14:14, Clément Léger wrote:
On some systems (MacOS for instance), sysconf(_SC_OPEN_MAX) can return
-1. In that case we should fallba
is_host_cpu_intel() should return TRUE if the host cpu in Intel based, otherwise
it should return FALSE. Currently, it returns zero (FALSE) when the host CPU
is INTEL and non-zero otherwise. Fix the function so that it agrees more with
the semantics. Adjust the calling logic accordingly. RAPL needs
> On 3 Sep 2024, at 1:13 PM, Paolo Bonzini wrote:
>
> On 9/3/24 09:19, Ani Sinha wrote:
>> is_host_cpu_intel() returns TRUE if the host cpu in Intel based. RAPL needs
>> Intel host cpus. If the host CPU is not Intel baseed, we should report error.
>> Fix the check accordingly.
>> Signed-off-by
Introduce a new ast2700 class to support AST2700.
The I2C bus register memory regions and
I2C bus pool buffer memory regions are discontinuous
and they do not back compatible AST2600.
Add a new ast2700 i2c class init function to match the
address of I2C bus register and pool buffer from the datash
v1:
- support I2C for AST2700
v2:
- fix review issues and add reviewer suggestion
- update avocado test case for AST2700 I2C
- support i2c bus pool
v3:
- update commit messages and commit title
- update API to get the device irq
Jamin Lin (11):
hw/i2c/aspeed: Support discontinuous register mem
This patch allows for easier manipulation of the cache description
register, CCSIDR. Which is helpful for testing as well. Currently,
numbers get hard-coded and might be prone to errors.
Therefore, this patch adds a wrapper for different types of CPUs
available in tcg to decribe caches. One functi
The "Current DMA Operating Address Status(0x50)" register of
I2C new mode has been removed in AST2700.
This register is used for debugging and it is a read only register.
To support AST2700 DMA mode, introduce a new
dma_dram_offset class attribute in AspeedI2Cbus to save the
current DMA operating
It only support continuous pool buffer memory region for all I2C bus.
However, the pool buffer address of all I2c bus are discontinuous
for AST2700.
Ex: the pool buffer address of I2C bus for ast2700 as following.
0x1A0 - 0x1BF: Device 0 buffer
0x2A0 - 0x2BF: Device 1 buffer
0x3A0 - 0x3BF: Device
ASPEED SDK add lm75 in i2c bus 0 for AST2700.
LM75 is compatible with TMP105 driver.
Introduce a new i2c init function and
add tmp105 device model in i2c bus 0.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed.c | 10 ++
1 file changed, 10 insertions(+)
diff --
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35)
and the base address of dram is "0x4 " which
is 64bits address.
It has "Master DMA Mode Tx Buffer Base Address[39:32](0x60)"
and "Master DMA Mode Rx Buffer Base Address[39:32](0x64)"
registers to save the high part physical addres
According to the datasheet of ASPEED SOCs,
each I2C bus has their own pool buffer since AST2500.
Only AST2400 utilized a pool buffer share to all I2C bus.
Besides, using a share pool buffer only support
pool buffer memory regions are continuous for all I2C bus.
To make this model more readable and
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35)
and the base address of dram is "0x4 " which
is 64bits address.
The AST2700 support the maximum DRAM size is 8 GB.
The DRAM physical address range is from "0x4__" to
"0x5__".
The DRAM offset range is from "0x0_000
It only support continuous register memory region for all I2C bus.
However, the register address of all I2c bus are discontinuous
for AST2700.
Ex: the register address of I2C bus for ast2700 as following.
0x100 - 0x17F: Device 0
0x200 - 0x27F: Device 1
0x300 - 0x37F: Device 2
0x400 - 0x47F: Device
Add I2C model for AST2700 I2C support.
The I2C controller registers base address is start at
0x14C0_F000 and its address space is 0x2000.
The AST2700 I2C controller has one source INTC per bus.
I2C buses interrupt are connected to GICINT130_INTC
from bit 0 to bit 15.
I2C bus 0 is connected to GICI
Currently, users can set the INTC mapping table with
enumerated device id and device irq to get the INTC orgate
input pins. However, some devices use the continuous source numbers in the
same INTC orgate. To reduce the enumerated device id definition,
create a new API to get the INTC orgate input p
Update test case to test lm75 temperature sensor.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
tests/avocado/machine_aspeed.py | 16
1 file changed, 16 insertions(+)
diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
index c0b01e8f1f..
On Tue, 3 Sep 2024 00:11:04 +0200
Philippe Mathieu-Daudé wrote:
> Hi Alireza,
>
> On 2/9/24 22:32, Alireza Sanaee wrote:
> > This patch allows for easier manipulation of the cache description
> > register, CCSIDR. Which is helpful for testing as well. Currently,
> > numbers get hard-coded and mi
Hello all,
Sorry, I have been a bit disconnected from this thread as I was on
vacations and then had to switch tasks for a while.
I will try to go through all comments and address them for the first
non-RFC drop of this patch series.
But I was discussing with some colleagues on this. So turns ou
On 9/3/24 10:35, Jamin Lin wrote:
Currently, users can set the INTC mapping table with
enumerated device id and device irq to get the INTC orgate
input pins. However, some devices use the continuous source numbers in the
same INTC orgate. To reduce the enumerated device id definition,
create a ne
On 9/3/24 10:35, Jamin Lin wrote:
Add I2C model for AST2700 I2C support.
The I2C controller registers base address is start at
0x14C0_F000 and its address space is 0x2000.
The AST2700 I2C controller has one source INTC per bus.
I2C buses interrupt are connected to GICINT130_INTC
from bit 0 to bi
On Mon, 2 Sept 2024 at 21:00, Philippe Mathieu-Daudé wrote:
>
> On 2/9/24 21:55, Philippe Mathieu-Daudé wrote:
> > Hi Changbin,
> >
> > On 30/8/24 12:53, Changbin Du via wrote:
> >> Print errors before exit. Do not exit silently.
> >>
> >> Signed-off-by: Changbin Du
> >>
> >> ---
> >> v2: remove
You have been subscribed to a public bug:
jammy:linux-lowlatency-hwe-6.8 6.8.0-44.44.1~22.04.1 qemu-x86 QEMU
Standard PC (i440FX + PIIX, 1996)
Recently (2024.08.05), I have been seeing this issue with
ADT:systemd:upstream-1/2 test in which kernel panics/prints a stack. I have
seen this with ja
jammy:linux-lowlatency-hwe-6.8 6.8.0-44.44.1~22.04.1 qemu-x86 QEMU
Standard PC (i440FX + PIIX, 1996) -> ADT:systemd:upstream-1
2564s --x-- Running TEST-13-NSPAWN-SMOKE --x--
2564s make: Entering directory
'/tmp/autopkgtest.Nji8tC/build.UBO/src/test/TEST-13-NSPAWN-SMOKE'
2564s Specify build direc
Only seen this with x86.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/2078790
Title:
jammy qemu x86 int3: [#1] SMP NOPTI
Status in linux-lowlatency-hwe-6.8 package in Ubuntu:
New
Status in
Only happens
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/2078790
Title:
jammy qemu x86 int3: [#1] SMP NOPTI
Status in linux-lowlatency-hwe-6.8 package in Ubuntu:
New
Status in qemu packag
** Project changed: qemu => qemu (Ubuntu)
--
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devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/2078790
Title:
jammy qemu x86 int3: [#1] SMP NOPTI
Status in linux-lowlatency-hwe-6.8 package in Ubuntu
On Thu, Jul 11, 2024 at 9:45 AM Stefan Hajnoczi wrote:
> On Fri, Jun 28, 2024 at 04:57:06PM +0200, Albert Esteve wrote:
> > Add SHMEM_MAP/UNMAP requests to vhost-user to
> > handle VIRTIO Shared Memory mappings.
> >
> > This request allows backends to dynamically map
> > fds into a VIRTIO Shared
On Wed, Aug 28, 2024 at 02:50:57PM GMT, Zhenguo Yao wrote:
I am very sorry that my previous description was not accurate. Below I
will describe the steps to reproduce this problem and my analysis in
detail.The conditions for reproducing this problem are quite
demanding. First, let me introduce my
On Thu, Aug 29, 2024 at 01:13:43PM GMT, Gao,Shiyuan wrote:
>--- a/hw/virtio/virtio-pci.c
>+++ b/hw/virtio/virtio-pci.c
>@@ -610,19 +610,29 @@ static MemoryRegion
*virtio_address_space_lookup(VirtIOPCIProxy *proxy,
> {
> int i;
> VirtIOPCIRegion *reg;
>+ MemoryRegion *mr = NULL;
`mr`
While adding hppa64 support, the psw_v variable got extended from 32 to 64
bits. So, when packaging the PSW-V bit from the psw_v variable for interrupt
processing, check bit 31 instead the 63th (sign) bit.
This fixes a hard to find Linux kernel boot issue where the loss of the PSW-V
bit due to an
Alex Bennée writes:
> Elisha Hollander writes:
>
>> Sure!
>>
>> `build/qemu-system-i386 -plugin build/contrib/plugins/libips.so,ips=1
>> -display curses -bios bios.raw`
>>
>> Also, I just tested with 9.1.0-rc4 and it resulted with
>> `tcg.c:3167:remove_label_use: code should not be reached`
>
>
kvm_arch_init() enables a lot of vm capabilities. Refactor them into separate
smaller functions. Energy MSR related operations also moved to its own
function. There should be no functional impact.
Signed-off-by: Ani Sinha
---
target/i386/kvm/kvm.c | 337 ++
On 8/26/24 11:18 PM, Tomasz Jeznach wrote:
On Fri, Aug 23, 2024 at 5:42 AM Daniel Henrique Barboza
wrote:
On 8/20/24 12:16 PM, Jason Chien wrote:
Hi Daniel,
On 2024/8/1 下午 11:43, Daniel Henrique Barboza wrote:
From: Tomasz Jeznach
The RISC-V IOMMU specification is now ratified as-per
The test_vcpu_dirty_limit is the only test that does not check for the
availability of the machine before starting the test, so it fails when
QEMU has been configured with --without-default-devices. Add a check for
the "pc" machine type to fix it.
Signed-off-by: Thomas Huth
---
tests/qtest/migra
Hi,
The KVM/QEMU community call is at:
https://meet.jit.si/kvmcallmeeting
@
03/09/2024 14:00 UTC
Are there any agenda items for the sync-up?
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
On Tue, Sep 3, 2024 at 11:54 AM Albert Esteve wrote:
>
>
> On Thu, Jul 11, 2024 at 9:45 AM Stefan Hajnoczi
> wrote:
>
>> On Fri, Jun 28, 2024 at 04:57:06PM +0200, Albert Esteve wrote:
>> > Add SHMEM_MAP/UNMAP requests to vhost-user to
>> > handle VIRTIO Shared Memory mappings.
>> >
>> > This req
When configuring QEMU with the --without-default-devices switch, these
tests are currently failing since they assume that the "pc" and "q35"
machines are always available. Add some proper checks to make the test
work without these machines, too.
Signed-off-by: Thomas Huth
---
tests/qtest/cdrom-t
Now virtio_address_space_lookup only lookup common/isr/device/notify
MR and exclude their subregions.
When VHOST_USER_PROTOCOL_F_HOST_NOTIFIER enable, the notify MR has
host-notifier subregions and we need use host-notifier MR to
notify the hardware accelerator directly instead of eventfd notify.
On 3.09.2024 00:07, Fabiano Rosas wrote:
"Maciej S. Szmigiero" writes:
From: "Maciej S. Szmigiero"
Migration code wants to manage device data sending threads in one place.
QEMU has an existing thread pool implementation, however it was limited
to queuing AIO operations only and essentially
Hi Steve,
On 30/08/2024 12:56, Steve Sistare wrote:
This reverts commit e6383293eb01928692047e617665a742cca87e23.
The reset function is needed for CPR.
Signed-off-by: Steve Sistare
---
hw/virtio/vhost-backend.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/virtio/vhost-backen
On 03/09/2024 02:33, Carl Hauser via wrote:
Well, I was wrong -- it is sending a duplicate mouse packets when the mouse wheel is
rotated. The packets correctly represent the mouse buttons state. I just now
discovered that one of my Logitech mice sends continuous mouse events when the wheel
is
On Tue, Aug 20, 2024 at 07:56:31PM +0800, Gao Shiyuan wrote:
> When VHOST_USER_PROTOCOL_F_HOST_NOTIFIER feature negotiated and
> virtio_queue_set_host_notifier_mr success on system blk
> device's queue, the VM can't load MBR if the notify region's
> address above 4GB.
>
> Assign the address of not
Elisha Hollander writes:
> Sure!
>
> `build/qemu-system-i386 -plugin build/contrib/plugins/libips.so,ips=1
> -display curses -bios bios.raw`
>
> Also, I just tested with 9.1.0-rc4 and it resulted with
> `tcg.c:3167:remove_label_use: code should not be reached`
I can replicate but it seems to be
On Fri, 2024-08-30 at 15:58 +0100, Peter Maydell wrote:
> Convert the TYPE_CCW_DEVICE to three-phase reset. This is a
> device class which is subclassed, so it needs to be three-phase
> before we can convert the subclass.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Nina Schoetterl-Glausch
>
kvm_arch_init() enables a lot of vm capabilities. Refactor them into separate
smaller functions. Energy MSR related operations also moved to its own
function. There should be no functional impact.
Signed-off-by: Ani Sinha
---
target/i386/kvm/kvm.c | 337 ++
identity_base variable is first initialzied to address 0xfffbc000 and then
kvm_vm_set_identity_map_addr() overrides this value to address 0xfeffc000.
The initial address to which the variable was initialized was never used. Clean
it up.
Signed-off-by: Ani Sinha
---
target/i386/kvm/kvm.c | 2 +-
Some cleanups. Should be no functional impact.
CC: Paolo Bonzini
CC: Marcelo Tosatti
CC: k...@vger.kernel.org
CC: qemu-devel@nongnu.org
Ani Sinha (2):
kvm/i386: refactor kvm_arch_init and split it into smaller functions
kvm/i386: do not initialize identity_base variable
target/i386/kvm/kv
KVM_CAP_READONLY_MEM used to be a global capability, but with the
introduction of AMD SEV-SNP confidential VMs, this extension is not
always available on all VM types [1,2].
Query the extension on the VM level instead of on the KVM level.
[1]
https://patchwork.kernel.org/project/kvm/patch/202408
On 8/1/24 12:43 PM, Daniel Henrique Barboza wrote:
Add a simple guideline to use the existing RISC-V IOMMU support we just
added.
This doc will be updated once we add the riscv-iommu-sys device.
Signed-off-by: Daniel Henrique Barboza
---
docs/specs/index.rst | 1 +
docs/specs/risc
Thomas Huth writes:
> The test_vcpu_dirty_limit is the only test that does not check for the
> availability of the machine before starting the test, so it fails when
> QEMU has been configured with --without-default-devices. Add a check for
> the "pc" machine type to fix it.
>
> Signed-off-by: Th
On 3/9/24 13:34, Ani Sinha wrote:
kvm_arch_init() enables a lot of vm capabilities. Refactor them into separate
smaller functions. Energy MSR related operations also moved to its own
function. There should be no functional impact.
Signed-off-by: Ani Sinha
---
target/i386/kvm/kvm.c | 337 +
On 3/9/24 10:35, Alireza Sanaee wrote:
This patch allows for easier manipulation of the cache description
register, CCSIDR. Which is helpful for testing as well. Currently,
numbers get hard-coded and might be prone to errors.
Therefore, this patch adds a wrapper for different types of CPUs
avail
On 3/9/24 08:50, Ani Sinha wrote:
kvm_filer_msr() is only used from i386 kvm module. Make it static so that its
easy for developers to understand that its not used anywhere else.
Signed-off-by: Ani Sinha
---
target/i386/kvm/kvm.c | 4 +++-
target/i386/kvm/kvm_i386.h | 3 ---
2 files ch
On 3/9/24 09:53, Clément Léger wrote:
On 02/09/2024 21:38, Philippe Mathieu-Daudé wrote:
On 30/8/24 13:57, Clément Léger wrote:
On 30/08/2024 13:31, Michael Tokarev wrote:
30.08.2024 14:14, Clément Léger wrote:
On some systems (MacOS for instance), sysconf(_SC_OPEN_MAX) can return
-1. In that
Let's make sure that we always pass a machine name to the test_boot_orders()
function, so we can check whether the machine is available in the binary
and skip the test in case it is not included in the build.
Signed-off-by: Thomas Huth
---
tests/qtest/boot-order-test.c | 4 ++--
1 file changed,
On Mon, Sep 02, 2024 at 09:55:19PM +0200, Philippe Mathieu-Daudé wrote:
> Hi Changbin,
>
> On 30/8/24 12:53, Changbin Du via wrote:
> > Print errors before exit. Do not exit silently.
> >
> > Signed-off-by: Changbin Du
> >
> > ---
> > v2: remove msg for arm_load_dtb.
> > ---
> > hw/arm/boot.c
kvm_filer_msr() is only used from i386 kvm module. Make it static so that its
easy for developers to understand that its not used anywhere else.
Same for QEMURDMSRHandler, QEMUWRMSRHandler and KVMMSRHandlers defintions.
CC: phi...@linaro.org
Signed-off-by: Ani Sinha
---
target/i386/kvm/kvm.c
On 3/9/24 15:44, Ani Sinha wrote:
kvm_filer_msr() is only used from i386 kvm module. Make it static so that its
easy for developers to understand that its not used anywhere else.
Same for QEMURDMSRHandler, QEMUWRMSRHandler and KVMMSRHandlers defintions.
"definitions".
CC: phi...@linaro.org
S
On 3/9/24 15:39, Changbin Du wrote:
Print errors before exit. Do not exit silently.
Cc: Philippe Mathieu-Daudé
Signed-off-by: Changbin Du
---
v3: use load_elf_strerror() to format errno.
v2: remove msg for arm_load_dtb.
---
hw/arm/boot.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
On 30/8/24 15:38, Thomas Huth wrote:
From: Philippe Mathieu-Daudé
Straight forward conversion. Since SBSA_FLASH files are not
tarballs, use lzma_uncompress() method.
Avocado used to set a timeout of 11 tests * 180s = 1980s.
Hopefully 600s should be sufficient.
Running on macOS Sonoma / Apple
Print errors before exit. Do not exit silently.
Cc: Philippe Mathieu-Daudé
Signed-off-by: Changbin Du
---
v3: use load_elf_strerror() to format errno.
v2: remove msg for arm_load_dtb.
---
hw/arm/boot.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index d4
On 3/9/24 11:20, Peter Maydell wrote:
On Mon, 2 Sept 2024 at 21:00, Philippe Mathieu-Daudé wrote:
On 2/9/24 21:55, Philippe Mathieu-Daudé wrote:
Hi Changbin,
On 30/8/24 12:53, Changbin Du via wrote:
Print errors before exit. Do not exit silently.
Signed-off-by: Changbin Du
---
v2: remove
kvm_filer_msr() is only used from i386 kvm module. Make it static so that its
easy for developers to understand that its not used anywhere else.
Same for QEMURDMSRHandler, QEMUWRMSRHandler and KVMMSRHandlers definitions.
CC: phi...@linaro.org
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Ani
On 9/3/24 10:35, Jamin Lin wrote:
v1:
- support I2C for AST2700
v2:
- fix review issues and add reviewer suggestion
- update avocado test case for AST2700 I2C
- support i2c bus pool
v3:
- update commit messages and commit title
- update API to get the device irq
Jamin Lin (11):
hw/i2c/aspee
On 3/9/24 15:45, Philippe Mathieu-Daudé wrote:
On 2/9/24 12:23, Thomas Huth wrote:
On 02/09/2024 11.48, Philippe Mathieu-Daudé wrote:
On 30/8/24 15:38, Thomas Huth wrote:
Nothing thrilling in here, it's just a straight forward conversion.
Signed-off-by: Thomas Huth
---
tests/functional/mes
On 8/23/24 12:09, David Woodhouse wrote:
diff --git a/drivers/ptp/Kconfig b/drivers/ptp/Kconfig
index 604541dcb320..e98c9767e0ef 100644
--- a/drivers/ptp/Kconfig
+++ b/drivers/ptp/Kconfig
@@ -131,6 +131,19 @@ config PTP_1588_CLOCK_KVM
To compile this driver as a module, choose M here: t
On 03/09/2024 15:34, Philippe Mathieu-Daudé wrote:
> On 3/9/24 09:53, Clément Léger wrote:
>> On 02/09/2024 21:38, Philippe Mathieu-Daudé wrote:
>>> On 30/8/24 13:57, Clément Léger wrote:
On 30/08/2024 13:31, Michael Tokarev wrote:
> 30.08.2024 14:14, Clément Léger wrote:
>> On some
On 9/3/24 03:28, Helge Deller wrote:
While adding hppa64 support, the psw_v variable got extended from 32 to 64
bits. So, when packaging the PSW-V bit from the psw_v variable for interrupt
processing, check bit 31 instead the 63th (sign) bit.
This fixes a hard to find Linux kernel boot issue wh
On 2/9/24 12:23, Thomas Huth wrote:
On 02/09/2024 11.48, Philippe Mathieu-Daudé wrote:
On 30/8/24 15:38, Thomas Huth wrote:
Nothing thrilling in here, it's just a straight forward conversion.
Signed-off-by: Thomas Huth
---
tests/functional/meson.build | 1 +
tests/{avo
In case QEMU has been configured with "--without-default-devices", the
"pc" machine type might be missing in the binary. We should check for
its availability before using it.
Signed-off-by: Thomas Huth
---
tests/qtest/hd-geo-test.c | 71 +--
1 file changed, 38
"Maciej S. Szmigiero" writes:
> On 3.09.2024 00:07, Fabiano Rosas wrote:
>> "Maciej S. Szmigiero" writes:
>>
>>> From: "Maciej S. Szmigiero"
>>>
>>> Migration code wants to manage device data sending threads in one place.
>>>
>>> QEMU has an existing thread pool implementation, however it was
On Tue, 27 Aug 2024 at 13:58, Maciej S. Szmigiero
wrote:
>
> From: "Maciej S. Szmigiero"
>
> Migration code wants to manage device data sending threads in one place.
>
> QEMU has an existing thread pool implementation, however it was limited
> to queuing AIO operations only and essentially had a
Pass the port range as argument. In order to reduce races
when looking for free ports, use a per-target per-process
base port (based on the target built-in hash).
Signed-off-by: Philippe Mathieu-Daudé
---
Based-on: <20240830133841.142644-33-th...@redhat.com>
---
tests/functional/test_vnc.py | 12
If the file is not an ELF file, arm_setup_direct_kernel_boot()
falls back to try it as a uimage or an AArch64 Image file or as
last resort a bare raw binary. We can discard load_elf_hdr()
error and silently return.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/boot.c | 8 ++--
1 file chan
"Maciej S. Szmigiero" writes:
> On 30.08.2024 22:22, Fabiano Rosas wrote:
>> "Maciej S. Szmigiero" writes:
>>
>>> From: "Maciej S. Szmigiero"
>>>
>>> Add a basic support for receiving device state via multifd channels -
>>> channels that are shared with RAM transfers.
>>>
>>> To differentiate
On 30/8/24 16:58, Peter Maydell wrote:
The Alpha and HPPA CPU class structs include a 'parent_reset'
field which is never used; delete them.
(These targets don't seem to implement reset at all; if they did they
should do it using the three-phase reset mechanism, which uses a
'ResettablePhases pa
This patch allows for easier manipulation of the cache description
register, CCSIDR. Which is helpful for testing as well. Currently,
numbers get hard-coded and might be prone to errors.
Therefore, this patch adds a wrapper for different types of CPUs
available in tcg to decribe caches. One functi
On Tue, Sep 03, 2024 at 04:35:53PM +0200, Philippe Mathieu-Daudé wrote:
> Pass the port range as argument. In order to reduce races
> when looking for free ports, use a per-target per-process
> base port (based on the target built-in hash).
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> Based-
On 9/2/24 23:45, Richard Henderson wrote:
I think the first implementation should be simpler:
CONST('C', TCG_CT_CONST_CMP_VI)
tcg_target_const_match()
{
...
if ((ct & TCG_CT_CONST_CMP_VI) &&
val >= tcg_cmpcond_to_rvv_vi[cond].min &&
val <= tcg_cmpcond_to_rvv_vi[cond]
On 8/29/24 23:16, LIU Zhiwei wrote:
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tcg/riscv/tcg-target.c.inc | 8
tcg/riscv/tcg-target.h | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 30/8/24 16:58, Peter Maydell wrote:
We used to need the transitional_function machinery to handle bus
classes and device classes which still used their legacy reset
handling. We have now converted all bus classes to three phase
reset, and simplified the device class legacy reset so it is just
On 8/29/24 23:16, LIU Zhiwei wrote:
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tcg/riscv/tcg-target.c.inc | 36
tcg/riscv/tcg-target.h | 4 ++--
2 files changed, 38 insertions(+), 2 deletions(-)
Reviewed-by: Rich
On 8/29/24 23:16, LIU Zhiwei wrote:
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tcg/riscv/tcg-target.c.inc | 29 +
tcg/riscv/tcg-target.h | 2 +-
2 files changed, 30 insertions(+), 1 deletion(-)
Reviewed-by: Richard Hender
On 30/8/24 16:58, Peter Maydell wrote:
Convert the TYPE_CCW_DEVICE to three-phase reset. This is a
device class which is subclassed, so it needs to be three-phase
before we can convert the subclass.
Signed-off-by: Peter Maydell
---
hw/s390x/ccw-device.c | 7 ---
1 file changed, 4 inserti
On 30/8/24 16:58, Peter Maydell wrote:
Now that all devices which still implement a the legacy reset method
register it via device_class_legacy_reset(), we can simplify the
handling of these devices. Instead of using the complex
Resettable::get_transitional_function machinery, we register a hold
On 8/29/24 23:16, LIU Zhiwei wrote:
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tcg/riscv/tcg-target-con-set.h | 1 +
tcg/riscv/tcg-target.c.inc | 44 ++
tcg/riscv/tcg-target.h | 4 ++--
3 files changed, 47 ins
On Tue, 3 Sep 2024 15:18:41 +0200
Philippe Mathieu-Daudé wrote:
> On 3/9/24 10:35, Alireza Sanaee wrote:
> > This patch allows for easier manipulation of the cache description
> > register, CCSIDR. Which is helpful for testing as well. Currently,
> > numbers get hard-coded and might be prone to e
"Maciej S. Szmigiero" writes:
> On 30.08.2024 20:13, Fabiano Rosas wrote:
>> "Maciej S. Szmigiero" writes:
>>
>>> From: "Maciej S. Szmigiero"
>>>
>>> This is necessary for multifd_send() to be able to be called
>>> from multiple threads.
>>>
>>> Signed-off-by: Maciej S. Szmigiero
>>> ---
>>>
On 8/29/24 23:16, LIU Zhiwei wrote:
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tcg/riscv/tcg-target.h | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson
r~
On 3/9/24 15:37, Clément Léger wrote:
On 03/09/2024 15:34, Philippe Mathieu-Daudé wrote:
On 3/9/24 09:53, Clément Léger wrote:
On 02/09/2024 21:38, Philippe Mathieu-Daudé wrote:
On 30/8/24 13:57, Clément Léger wrote:
On 30/08/2024 13:31, Michael Tokarev wrote:
30.08.2024 14:14, Clément Léger
"Maciej S. Szmigiero" writes:
> On 30.08.2024 20:55, Fabiano Rosas wrote:
>> "Maciej S. Szmigiero" writes:
>>
>>> From: "Maciej S. Szmigiero"
>>>
>>> Since device state transfer via multifd channels requires multifd
>>> channels with packets and is currently not compatible with multifd
>>> com
On 8/29/24 23:16, LIU Zhiwei wrote:
@@ -2589,6 +2605,69 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,
unsigned vece,
}
}
break;
+case INDEX_op_shli_vec:
+if (a2 > 31) {
+tcg_gen_shls_vec(vece, v0, v1, tcg_constant_i32(a2));
+
On Tue, Sep 03, 2024 at 05:02:44PM +0200, Philippe Mathieu-Daudé wrote:
> On 3/9/24 15:37, Clément Léger wrote:
> > On 03/09/2024 15:34, Philippe Mathieu-Daudé wrote:
> > > On 3/9/24 09:53, Clément Léger wrote:
> > > > On 02/09/2024 21:38, Philippe Mathieu-Daudé wrote:
> > > > > On 30/8/24 13:57, C
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