Re: [RFC PATCH 0/6] Enable shared device assignment

On 7/31/2024 7:18 PM, David Hildenbrand wrote: > Sorry for the late reply! > >>> Current users must skip it, yes. How private memory would have to be >>> handled, and who would handle it, is rather unclear. >>> >>> Again, maybe we'd want separate RamDiscardManager for private and shared >>> mem

Re: [PATCH 2/4] hw/misc/bcm2835_property: Avoid overflow in OTP access properties

23.07.2024 16:10, Peter Maydell wrote: Coverity points out that in our handling of the property RPI_FWREQ_SET_CUSTOMER_OTP we have a potential overflow. This happens because we read start_num and number from the guest as unsigned 32 bit integers, but then the variable 'n' we use as a loop counte

Re: [PATCH 2/4] hw/misc/bcm2835_property: Avoid overflow in OTP access properties

02.08.2024 10:02, Michael Tokarev wrote: 23.07.2024 16:10, Peter Maydell wrote: Coverity points out that in our handling of the property RPI_FWREQ_SET_CUSTOMER_OTP we have a potential overflow.  This happens because we read start_num and number from the guest as unsigned 32 bit integers, but the

[PATCH] hw/audio/virtio-snd: fix invalid param check

Commit 9b6083465f ("virtio-snd: check for invalid param shift operands") tries to prevent invalid parameters specified by the guest. However, the code is not correct. Change the code so that the parameters format and rate, which are a bit numbers, are compared with the bit size of the data type.

[PATCH v3 0/3] target/riscv: Remove redundant insn length check for zama16b

In this patch set, we remove the redundant insn length check for zama16b as the specification clarified that zama16b applies to compressed encodings[1]. Richard points out we should obey the MXLEN requirement for F/D/Q loads or stores, so we add this constraint for trans_fld/fsd. I notice that w

[PATCH v3 1/3] target/riscv: Remove redundant insn length check for zama16b

Compressed encodings also applies to zama16b. https://github.com/riscv/riscv-isa-manual/pull/1557 Suggested-by: Alistair Francis Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvd.c.inc | 4 ++-- target/riscv/insn_trans/trans_rvf.c.inc | 4 ++-- target/riscv/insn_trans/trans_rvi.c.

[PATCH v3 2/3] target/riscv: Add MXLEN check for F/D/Q applies to zama16b

Zama16b loads and stores of no more than MXLEN bits defined in the F, D, and Q extensions. Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvd.c.inc | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/ins

[PATCH v3 3/3] target/riscv: Relax fld alignment requirement

According to the risc-v specification: "FLD and FSD are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN≥64." We currently implement fld as MO_ATOM_IFALIGN when XLEN < 64, which does not violate the rules. But it will hide some problems. So relax it to M

Re: [PATCH v3] util: use RETRY_ON_EINTR() on open() more consistently

Hi Philippe and everyone else on the thread, In the meantime, I learned that we can cause the kernel to restart the open() syscall by returning ERESTARTSYS from the kernel-level block device driver side. It was our mistake from the DRBD side that we returned EINTR instead. The proposed patch to q

[PATCH] i386/cpu: Introduce enable_cpuid_0x1f to force exposing CPUID 0x1f

Currently, QEMU exposes CPUID 0x1f to guest only when necessary, i.e., when topology level that cannot be enumerated by leaf 0xB, e.g., die or module level, are configured for the guest. However, 1) TDX architecture forces to require CPUID 0x1f to configure CPU topology. and 2) There is a bug in W

Re: [PATCH v4 6/6] hvf: arm: Do not advance PC when raising an exception

02.08.2024 09:44, Akihiko Odaki wrote: On 2024/08/02 15:41, Michael Tokarev wrote: 20.07.2024 12:30, Akihiko Odaki wrote: This is identical with commit 30a1690f2402 ("hvf: arm: Do not advance PC when raising an exception") but for writes instead of reads. Fixes: a2260983c655 ("hvf: arm: Add su

Re: [PATCH] vhost: Add VIRTIO_NET_F_RSC_EXT to vhost feature bits

.46b02c50be8c 100644 > --- a/net/vhost-vdpa.c > +++ b/net/vhost-vdpa.c > @@ -88,6 +88,7 @@ const int vdpa_feature_bits[] = { > VIRTIO_NET_F_MQ, > VIRTIO_NET_F_MRG_RXBUF, > VIRTIO_NET_F_MTU, > +VIRTIO_NET_F_RSC_EXT, > VIRTIO_NET_F_RSS, > VIRTIO_NET

Re: [PATCH v1] target/i386: Always set leaf 0x1f

On 8/2/2024 12:46 AM, Manish wrote: On 01/08/24 8:41 pm, Xiaoyao Li wrote: !---|  CAUTION: External Email |---! On 8/1/2024 6:25 PM, Igor Mammedov wrote: On Thu, 1

Re: [PATCH 8/8] qemu-options: Add the description of smp-cache object

On Thu, Aug 01, 2024 at 01:28:27PM +0200, Markus Armbruster wrote: > Date: Thu, 01 Aug 2024 13:28:27 +0200 > From: Markus Armbruster > Subject: Re: [PATCH 8/8] qemu-options: Add the description of smp-cache > object > > Zhao Liu writes: > > > On Thu, Jul 25, 2024 at 11:07:12AM +0200, Markus Ar

Re: [PULL 3/4] target/arm: Handle denormals correctly for FMOPA (widening)

01.08.2024 17:23, Peter Maydell wrote: The FMOPA (widening) SME instruction takes pairs of half-precision floating point values, widens them to single-precision, does a two-way dot product and accumulates the results into a single-precision destination. We don't quite correctly handle the FPCR b

Re: [PATCH v7 4/5] qemu/osdep: Add excluded fd parameter to qemu_close_all_open_fd()

On 31/07/2024 23:56, Richard Henderson wrote: > On 7/31/24 18:48, Clément Léger wrote: >> @@ -823,8 +824,34 @@ static bool qemu_close_all_open_fd_proc(void) >>   dfd = dirfd(dir); >>     for (de = readdir(dir); de; de = readdir(dir)) { >> +    bool close_fd = true; >> + >> +    i

Re: [PULL 05/21] hvf: arm: Raise an exception for sysreg by default

On 7/30/24 19:40, Peter Maydell wrote: From: Akihiko Odaki Any sysreg access results in an exception unless defined otherwise so we should raise an exception by default. Signed-off-by: Akihiko Odaki Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/hvf/hvf.c | 174 +++

Re: [PATCH v3 1/3] target/riscv: Remove redundant insn length check for zama16b

On 8/2/24 17:24, LIU Zhiwei wrote: Compressed encodings also applies to zama16b. https://github.com/riscv/riscv-isa-manual/pull/1557 Suggested-by: Alistair Francis Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvd.c.inc | 4 ++-- target/riscv/insn_trans/trans_rvf.c.inc | 4 ++--

Re: [PATCH v3 2/3] target/riscv: Add MXLEN check for F/D/Q applies to zama16b

On 8/2/24 17:24, LIU Zhiwei wrote: Zama16b loads and stores of no more than MXLEN bits defined in the F, D, and Q extensions. Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvd.c.inc | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_tr

Re: [PATCH v3 3/3] target/riscv: Relax fld alignment requirement

On 8/2/24 17:24, LIU Zhiwei wrote: According to the risc-v specification: "FLD and FSD are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN≥64." We currently implement fld as MO_ATOM_IFALIGN when XLEN < 64, which does not violate the rules. But it will

Re: [PATCH v2 1/2] qdev-monitor: avoid QemuOpts in QMP device_add

Stefan Hajnoczi writes: > The QMP device_add monitor command converts the QDict arguments to > QemuOpts and then back again to QDict. This process only supports scalar > types. Device properties like virtio-blk-pci's iothread-vq-mapping (an > array of objects) are silently dropped by qemu_opts_fr

Re: [PATCH v2 2/2] vl: use qmp_device_add() in qemu_create_cli_devices()

Stefan Hajnoczi writes: > qemu_create_cli_devices() should use qmp_device_add() to match the > behavior of the QMP monitor. A comment explained that libvirt changes > implementing strict CLI syntax were needed. > > Peter Krempa has confirmed that modern libvirt uses > the same JSON for -device (

Re: [PATCH v2 0/2] qdev-monitor: avoid QemuOpts in QMP device_add

Can we additionally cut out the QemuOpts middleman in usbback_portid_add()? qdict = qdict_new(); qdict_put_str(qdict, "driver", "usb-host"); tmp = g_strdup_printf("%s.0", usbif->xendev.qdev.id); qdict_put_str(qdict, "bus", tmp); g_free(tmp); tmp = g_strdup_printf("%s-%u", u

Re: [PATCH v3 08/24] tests/functional: add a module for handling asset download & caching

On Fri, Aug 02, 2024 at 07:51:14AM +1000, Richard Henderson wrote: > On 7/31/24 03:03, Daniel P. Berrangé wrote: > > +def __init__(self, url, hash): > > +self.url = url > > +self.hash = hash > > +self.cache_dir = Path(Path("~").expanduser(), > > +

[PATCH 01/18] bsd-user: Implement RISC-V CPU initialization and main loop

From: Mark Corbin Added the initial implementation for RISC-V CPU initialization and main loop. This includes setting up the general-purpose registers and program counter based on the provided target architecture definitions. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by

[PATCH 05/18] bsd-user: Add prototype for RISC-V TLS register setup

From: Mark Corbin Included the prototype for the 'target_cpu_set_tls' function in the 'target_arch.h' header file. This function is responsible for setting the Thread Local Storage (TLS) register for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh --- bsd-user/riscv

[PATCH 07/18] bsd-user: Define RISC-V register structures and register copying

From: Mark Corbin Added definitions for RISC-V register structures, including general-purpose registers and floating-point registers, in 'target_arch_reg.h'. Implemented the 'target_copy_regs' function to copy register values from the CPU state to the target register structure, ensuring proper en

[PATCH 13/18] bsd-user: Add generic RISC-V64 target definitions

From: Warner Losh Added a generic definition for RISC-V64 target-specific details. Implemented the 'regpairs_aligned' function,which returns 'false' to indicate that register pairs are not aligned in the RISC-V64 ABI. Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh --- bsd-user/riscv/ta

[PATCH 10/18] bsd-user: Add RISC-V thread setup and initialization support

From: Mark Corbin Implemented functions for setting up and initializing threads in the RISC-V architecture. The 'target_thread_set_upcall' function sets up the stack pointer, program counter, and function argument for new threads. The 'target_thread_init' function initializes thread registers bas

[PATCH 12/18] bsd-user: Define RISC-V system call structures and constants

From: Mark Corbin Introduced definitions for the RISC-V system call interface, including the 'target_pt_regs' structure that outlines the register storage layout during a system call. Added constants for hardware machine identifiers. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-aut

[PATCH 02/18] bsd-user: Add RISC-V CPU execution loop and syscall handling

From: Mark Corbin Implemented the RISC-V CPU execution loop, including handling various exceptions and system calls. The loop continuously executes CPU instructions,processes exceptions, and handles system calls by invoking FreeBSD syscall handlers. Signed-off-by: Mark Corbin Signed-off-by: Aje

[PATCH 00/18] bsd-user: Comprehensive RISCV support

This patch series provides support for the RISC-V 64-bit architecture, enabling signal processing, system call handling, threading, and memory management tailored to RISC-V. Mark Corbin (16): bsd-user: Implement RISC-V CPU initialization and main loop bsd-user: Add RISC-V CPU execution loop an

[PATCH 11/18] bsd-user: Define RISC-V VM parameters and helper functions

From: Mark Corbin Added definitions for RISC-V VM parameters, including maximum and default sizes for text, data, and stack, as well as address space limits. Implemented helper functions for retrieving and setting specific values in the CPU state, such as stack pointer and return values. Signed-

[PATCH 06/18] bsd-user: Add RISC-V ELF definitions and hardware capability detection

From: Mark Corbin Introduced RISC-V specific ELF definitions and hardware capability detection. Additionally, a function to retrieve hardware capabilities ('get_elf_hwcap') is implemented, which returns the common bits set in each CPU's ISA strings. Signed-off-by: Mark Corbin Signed-off-by: Aje

[PATCH 09/18] bsd-user: Implement RISC-V sysarch system call emulation

From: Mark Corbin Added the 'do_freebsd_arch_sysarch' function to emulate the 'sysarch' system call for the RISC-V architecture. Currently, this function returns '-TARGET_EOPNOTSUPP' to indicate that the operation is not supported. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh --- bsd

Re: [PATCH] target/i386: SEV: fix mismatch in vcek-disabled property name

On 8/2/2024 1:43 AM, Paolo Bonzini wrote: The vcek-disabled property of the sev-snp-guest object is misspelled vcek-required (which I suppose would use the opposite polarity) in the call to object_class_property_add_bool(). Fix it. Reported-by: Zixi Chen Cc: Pankaj Gupta Signed-off-by: Paolo

[PATCH 18/18] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files

From: Warner Losh Added configuration for RISC-V 64-bit target to the build system. Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh --- configs/targets/riscv64-bsd-user.mak | 4 1 file changed, 4 insertions(+) create mode 100644 configs/targets/riscv64-bsd-user.mak diff --git a/c

[PATCH 03/18] bsd-user: Implement RISC-V CPU register cloning and reset functions

From: Mark Corbin Added functions for cloning CPU registers and resetting the CPU state for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh --- bsd-user/riscv/target_arch_cpu.h | 14 ++ 1 file changed, 14 insertions(+) diff --git a/bsd-user/riscv/target

[PATCH 14/18] bsd-user: Define RISC-V signal handling structures and constants

From: Mark Corbin Added definitions for RISC-V signal handling, including structures and constants for managing signal frames and context Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Warner Losh --- bsd-user/riscv/target_arch_signal.h | 75 +++

[PATCH 17/18] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV

From: Mark Corbin Added implementations for 'set_mcontext' and 'get_ucontext_sigreturn' functions for RISC-V architecture, Both functions ensure that the CPU state and user context are properly managed. Signed-off-by: Mark Corbin Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh Co-author

[PATCH 15/18] bsd-user: Implement RISC-V signal trampoline setup functions

From: Mark Corbin Added functions for setting up the RISC-V signal trampoline and signal frame: 'set_sigtramp_args()': Configures the RISC-V CPU state with arguments for the signal handler. It sets up the registers with the signal number,pointers to the signal info and user context, the signal h

[PATCH 16/18] bsd-user: Implement 'get_mcontext' for RISC-V

From: Mark Corbin Added the 'get_mcontext' function to extract and populate the RISC-V machine context from the CPU state. This function is used to gather the current state of the general-purpose registers and store it in a 'target_mcontext_' structure. Signed-off-by: Mark Corbin Signed-off-by:

[PATCH 08/18] bsd-user: Add RISC-V signal trampoline setup function

From: Mark Corbin Implemented the `setup_sigtramp` function for setting up the signal trampoline code in the RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh --- bsd-user/riscv/target_arch_sigtramp.h | 46 +++ 1 file changed, 46 insertions(+)

[PATCH 04/18] bsd-user: Implement RISC-V TLS register setup

From: Mark Corbin Added the 'target_cpu_set_tls' function to handle setting the Thread Local Storage (TLS) register for the RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh --- bsd-user/riscv/target_arch_cpu.c | 29 + 1 file changed, 29 in

[PATCH] hvf: arm: Fix hvf_sysreg_read_cp() call

(hvf_sysreg_read_cp(cpu, reg, val)) { return 0; } break; --- base-commit: 31669121a01a14732f57c49400bc239cf9fd505f change-id: 20240802-hvf-40971c54eccf Best regards, -- Akihiko Odaki

Re: [PATCH 2/5] docs/interop/nbd.txt: Convert to rST

On Thu, 1 Aug 2024 at 19:39, Eric Blake wrote: > > On Thu, Aug 01, 2024 at 06:01:28PM GMT, Peter Maydell wrote: > > Convert nbd.txt to rST format. > > > > Signed-off-by: Peter Maydell > > --- > > MAINTAINERS| 2 +- > > docs/interop/index.rst | 1 + > > docs/interop/nbd.rst | 89 +

Re: [PULL 05/21] hvf: arm: Raise an exception for sysreg by default

On 2024/08/02 16:51, Richard Henderson wrote: On 7/30/24 19:40, Peter Maydell wrote: From: Akihiko Odaki Any sysreg access results in an exception unless defined otherwise so we should raise an exception by default. Signed-off-by: Akihiko Odaki Reviewed-by: Peter Maydell Signed-off-by: Pete

Re: [PULL 3/4] target/arm: Handle denormals correctly for FMOPA (widening)

On Fri, 2 Aug 2024 at 08:45, Michael Tokarev wrote: > > 01.08.2024 17:23, Peter Maydell wrote: > > The FMOPA (widening) SME instruction takes pairs of half-precision > > floating point values, widens them to single-precision, does a > > two-way dot product and accumulates the results into a > > si

Re: [PATCH] hvf: arm: Fix hvf_sysreg_read_cp() call

On Fri, 2 Aug 2024 at 09:37, Akihiko Odaki wrote: > > Commit 05b8d7249109 ("hvf: arm: Do not advance PC when raising an > exception") changed val from uint64_t to a pointer to uint64_t in > hvf_sysreg_read(), but didn't change its hvf_sysreg_read_cp() call. > > Fixes: 05b8d7249109 ("hvf: arm: Do n

Re: [RFC 0/5] accel/kvm: Support KVM PMU filter

Hi Zhao, On 7/10/24 12:51, Zhao Liu wrote: Hi QEMU maintainers, arm and PMU folks, I picked up Shaoqing's previous work [1] on the KVM PMU filter for arm, and now is trying to support this feature for x86 with a JSON-compatible API. While arm and x86 use different KVM ioctls to configure the P

Re: [RFC 0/5] accel/kvm: Support KVM PMU filter

Hello Shaoqin, On Fri, Aug 02, 2024 at 05:01:47PM +0800, Shaoqin Huang wrote: > Date: Fri, 2 Aug 2024 17:01:47 +0800 > From: Shaoqin Huang > Subject: Re: [RFC 0/5] accel/kvm: Support KVM PMU filter > > Hi Zhao, > > On 7/10/24 12:51, Zhao Liu wrote: > > Hi QEMU maintainers, arm and PMU folks, >

Re: [RFC 0/5] accel/kvm: Support KVM PMU filter

Hi Zhao, On 8/2/24 17:37, Zhao Liu wrote: Hello Shaoqin, On Fri, Aug 02, 2024 at 05:01:47PM +0800, Shaoqin Huang wrote: Date: Fri, 2 Aug 2024 17:01:47 +0800 From: Shaoqin Huang Subject: Re: [RFC 0/5] accel/kvm: Support KVM PMU filter Hi Zhao, On 7/10/24 12:51, Zhao Liu wrote: Hi QEMU maint

Re: [PATCH v4 5/7] qapi/ghes-cper: add an interface to do generic CPER error injection

Mauro Carvalho Chehab writes: > Creates a QAPI to be used for generic ACPI APEI hardware error > injection (HEST) via GHESv2. Creates a QMP command > The actual GHES code will be added at the followup patch. > > Signed-off-by: Mauro Carvalho Chehab > --- > MAINTAINERS| 7 ++ >

Re: [RFC 0/5] accel/kvm: Support KVM PMU filter

On Fri, Aug 02, 2024 at 05:41:57PM +0800, Shaoqin Huang wrote: > Date: Fri, 2 Aug 2024 17:41:57 +0800 > From: Shaoqin Huang > Subject: Re: [RFC 0/5] accel/kvm: Support KVM PMU filter > > Hi Zhao, > > On 8/2/24 17:37, Zhao Liu wrote: > > Hello Shaoqin, > > > > On Fri, Aug 02, 2024 at 05:01:47PM

Re: [PULL 0/8] Net patches

On 8/2/24 13:19, Jason Wang wrote: The following changes since commit 31669121a01a14732f57c49400bc239cf9fd505f: Merge tag 'pull-target-arm-20240801' ofhttps://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-08-02 08:18:37 +1000) are available in the Git repository at: https:

Re: [PATCH] hvf: arm: Fix hvf_sysreg_read_cp() call

On 8/2/24 18:44, Peter Maydell wrote: On Fri, 2 Aug 2024 at 09:37, Akihiko Odaki wrote: Commit 05b8d7249109 ("hvf: arm: Do not advance PC when raising an exception") changed val from uint64_t to a pointer to uint64_t in hvf_sysreg_read(), but didn't change its hvf_sysreg_read_cp() call. Fixes

[PATCH 0/4] linux-user/i386: Emulate orig_ax

Hi, Currently gdbstub is barely usable with i386-linux-user: GDB cannot even parse a shared library list, so no symbols are available. This boils down to unavailability of info proc, which is gated behind org.gnu.gdb.i386.linux. See amd64_linux_init_abi(); info proc is enabled by amd64_linux_init_

[PATCH 1/5] include/exec: Introduce env_cpu_const()

It's the same as env_cpu(), but for const objects. Signed-off-by: Ilya Leoshkevich --- include/exec/cpu-common.h | 13 - linux-user/elfload.c | 2 +- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 2e1b

[PATCH 2/5] linux-user/i386: Emulate orig_ax

The kernel uses orig_rax/orig_eax to store the syscall number before a syscall. One can see this value in core dumps and ptrace. Signed-off-by: Ilya Leoshkevich --- linux-user/elfload.c | 4 ++-- linux-user/i386/cpu_loop.c | 3 +++ linux-user/qemu.h | 5 + 3 files changed, 10

[PATCH 4/5] target/i386/gdbstub: Expose orig_ax

Copy XML files describing orig_ax from GDB and glue them with CPUX86State.orig_ax. Signed-off-by: Ilya Leoshkevich --- configs/targets/i386-linux-user.mak | 2 +- configs/targets/x86_64-linux-user.mak | 2 +- gdb-xml/i386-32bit-linux.xml | 11 ++ gdb-xml/i386-64bit-linux.xml

[PATCH 3/5] target/i386/gdbstub: Factor out gdb_get_reg() and gdb_write_reg()

i386 gdbstub handles both i386 and x86_64. Factor out two functions for reading and writing registers without knowing their bitness. Signed-off-by: Ilya Leoshkevich --- target/i386/gdbstub.c | 52 ++- 1 file changed, 31 insertions(+), 21 deletions(-) diff

[PATCH 5/5] tests/tcg: Run test-proc-mappings.py on i386

Now that orig_ax is exposed and GDB is happy, don't skip test-proc-mappings.py on i386. In fact, it's broken only on m68k now, so skip only this architecture. Signed-off-by: Ilya Leoshkevich --- .../tcg/multiarch/gdbstub/test-proc-mappings.py | 17 ++--- 1 file changed, 6 insertions(

Re: [PATCH v2 1/4] block: get type of block allocation in commit_run

On 14.07.24 00:56, Vincent Vanlaer wrote: bdrv_co_common_block_status_above not only returns whether the block is allocated, but also if it contains zeroes. Signed-off-by: Vincent Vanlaer Reviewed-by: Vladimir Sementsov-Ogievskiy -- Best regards, Vladimir

Re: [PATCH v2 2/4] block: refactor commit_run for multiple write types

On 14.07.24 00:56, Vincent Vanlaer wrote: Signed-off-by: Vincent Vanlaer Reviewed-by: Vladimir Sementsov-Ogievskiy Honestly, I don't like this (mostly preexisting, but your patch make the problem more obvious) code for its "nested success path" if (ret >= 0) { ret = ... if (ret >= 0) {

Re: [PATCH 5/5] tests/tcg: Run test-proc-mappings.py on i386

Ilya Leoshkevich writes: > Now that orig_ax is exposed and GDB is happy, don't skip > test-proc-mappings.py on i386. In fact, it's broken only on > m68k now, so skip only this architecture. > > Signed-off-by: Ilya Leoshkevich Acked-by: Alex Bennée -- Alex Bennée Virtualisation Tech Lead @ Li

Re: [PATCH for-9.2 v11 10/11] hw/pci: Use -1 as the default value for rombar

Akihiko Odaki writes: > vfio_pci_size_rom() distinguishes whether rombar is explicitly set to 1 > by checking dev->opts, bypassing the QOM property infrastructure. > > Use -1 as the default value for rombar to tell if the user explicitly > set it to 1. The property is also converted from unsigned

Re: [PATCH v2 3/4] block: allow commit to unmap zero blocks

On 14.07.24 00:56, Vincent Vanlaer wrote: Non-active block commits do not discard blocks only containing zeros, causing images to lose sparseness after the commit. This commit fixes that by writing zero blocks using blk_co_pwrite_zeroes rather than writing them out as any other arbitrary data. S

Re: [PATCH v2 5/7] qapi: add job-change

On 18.07.24 13:59, Markus Armbruster wrote: Vladimir Sementsov-Ogievskiy writes: Add a new-style command job-change, doing same thing as block-job-change. The aim is finally deprecate block-job-* APIs and move to job-* APIs. We add a new command to qapi/block-core.json, not to qapi/job.json t

Re: [PATCH v2 6/7] qapi/block-core: derpecate block-job-change

On 18.07.24 14:01, Markus Armbruster wrote: Vladimir Sementsov-Ogievskiy writes: That's a first step to move on newer job-* APIs. The difference between block-job-change and job-change is in find_block_job_locked() vs find_job_locked() functions. What's different? 1. find_block_job_locked()

Re: [PATCH v2 1/3] block/commit: implement final flush

On 29.07.24 15:25, Kevin Wolf wrote: Am 19.07.2024 um 12:35 hat Vladimir Sementsov-Ogievskiy geschrieben: On 18.07.24 22:22, Kevin Wolf wrote: Am 26.06.2024 um 16:50 hat Vladimir Sementsov-Ogievskiy geschrieben: Actually block job is not completed without the final flush. It's rather unexpecte

Re: [PATCH] hw/audio/virtio-snd: fix invalid param check

On Fri, 02 Aug 2024 10:18, Volker Rümelin wrote: Commit 9b6083465f ("virtio-snd: check for invalid param shift operands") tries to prevent invalid parameters specified by the guest. However, the code is not correct. Change the code so that the parameters format and rate, which are a bit numbers

Re: [PULL v2 17/61] virtio-snd: check for invalid param shift operands

On Fri, 02 Aug 2024 08:03, Volker Rümelin wrote: Am 01.08.24 um 10:22 schrieb Michael S. Tsirkin: On Sat, Jul 27, 2024 at 08:55:10AM +0200, Volker Rümelin wrote: Hi Manos, this patch doesn't work as intended. I guess you wanted to write     if (params->format >= sizeof(supported_formats

[RFC v3 1/3] vhost: Introduce packed vq and add buffer elements

This is the first patch in a series to add support for packed virtqueues in vhost_shadow_virtqueue. This patch implements the insertion of available buffers in the descriptor area. It takes into account descriptor chains, but does not consider indirect descriptors. Signed-off-by: Sahil Siddiq ---

[RFC v3 0/3] Add packed virtqueue to shadow virtqueue

Hi, Here's a new patch series that incorporates all the suggested changes from v2. I have tried my best to deduplicate the implementation. Please let me know if I have missed something. I'll also test these changes out by following the suggestions given in response to v1. I'll have more confiden

[RFC v3 2/3] vhost: Data structure changes to support packed vqs

Introduce "struct vring_packed". Modify VhostShadowVirtqueue so it can support split and packed virtqueue formats. Signed-off-by: Sahil Siddiq --- No changes from v1/v2 -> v3 hw/virtio/vhost-shadow-virtqueue.h | 66 -- 1 file changed, 44 insertions(+), 22 deletions(

[RFC v3 3/3] vhost: Allocate memory for packed vring

Allocate memory for the packed vq format and support packed vq in the SVQ "start" and "stop" operations. Signed-off-by: Sahil Siddiq --- Changes v2 -> v3: * vhost-shadow-virtqueue.c (vhost_svq_memory_packed): New function (vhost_svq_start): - Remove common variables out of if-else branch.

Re: [RFC v2 1/3] vhost: Introduce packed vq and add buffer elements

Hi, On Monday, July 29, 2024 1:51:27 PM GMT+5:30 Eugenio Perez Martin wrote: > On Sun, Jul 28, 2024 at 7:37 PM Sahil wrote: > > [...] > > > > +static bool vhost_svq_add_packed(VhostShadowVirtqueue *svq, > > > > +const struct iovec *out_sg, size_t > > > > out_num,

Re: [PATCH] qmp: Fix higher half vaddrs for [p]memsave

Josh Junon writes: > Previously, int64_t's were used when parsing virtual / physical > addresses for the [p]memsave commands over QMP (HMP was unaffected). > This caused issues when the virtual addresses were in the higher > half of a 64-bit address space, as various portions of the parsing > cod

Re: [PATCH] qmp: Fix higher half vaddrs for [p]memsave

On Fri, Aug 02, 2024 at 01:39:15PM +0200, Markus Armbruster wrote: > Josh Junon writes: > > > Previously, int64_t's were used when parsing virtual / physical > > addresses for the [p]memsave commands over QMP (HMP was unaffected). > > This caused issues when the virtual addresses were in the high

Re: [PATCH] arm/kvm: add support for MTE

Hi Peter, On 16-07-2024 09:15 pm, Peter Maydell wrote: On Tue, 9 Jul 2024 at 07:05, Ganapatrao Kulkarni wrote: Extend the 'mte' property for the virt machine to cover KVM as well. For KVM, we don't allocate tag memory, but instead enable the capability. If MTE has been enabled, we need to

Re: [PATCH 01/18] bsd-user: Implement RISC-V CPU initialization and main loop

On 8/2/24 18:34, Ajeet Singh wrote: +static inline void target_cpu_init(CPURISCVState *env, +struct target_pt_regs *regs) +{ +int i; + +for (i = 0; i < 32; i++) { i = 1 as r0 is zero. Otherwise, Reviewed-by: Richard Henderson r~

Re: [PATCH 0/2] Multifd fixes

On Thu, 01 Aug 2024 14:40:59 -0300, Fabiano Rosas wrote: > on mapped-ram for libvirt. > > CI run: https://gitlab.com/farosas/qemu/-/pipelines/1397467740 > > Fabiano Rosas (2): > migration: Fix cleanup of iochannel in file migration > migration/multifd: Fix multifd_send_setup cleanup when chan

Re: (subset) [PATCH v2 08/15] migration: Free removed SaveStateEntry

On Thu, 27 Jun 2024 22:37:51 +0900, Akihiko Odaki wrote: > This fixes LeakSanitizer warnings. > > Queued, thanks!

[PATCH v2] qmp: Use unsigned integers for address parameters

Fixes higher-half address parsing for QMP commands `[p]memsave` and `dump-guest-memory`. Signed-off-by: Josh Junon --- dump/dump.c | 4 ++-- qapi/dump.json| 2 +- qapi/machine.json | 11 +-- system/cpus.c | 8 4 files changed, 16 insertions(+), 9 deletions(-) d

Re: [PATCH 02/18] bsd-user: Add RISC-V CPU execution loop and syscall handling

On 8/2/24 18:34, Ajeet Singh wrote: From: Mark Corbin Implemented the RISC-V CPU execution loop, including handling various exceptions and system calls. The loop continuously executes CPU instructions,processes exceptions, and handles system calls by invoking FreeBSD syscall handlers. Signed-of

Re: [PATCH 03/18] bsd-user: Implement RISC-V CPU register cloning and reset functions

On 8/2/24 18:34, Ajeet Singh wrote: From: Mark Corbin Added functions for cloning CPU registers and resetting the CPU state for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh --- bsd-user/riscv/target_arch_cpu.h | 14 ++ 1 file changed, 14 insertion

Re: [PATCH for-9.2 v11 08/11] pcie_sriov: Remove num_vfs from PCIESriovPF

On Fri, Aug 02, 2024 at 02:17:58PM +0900, Akihiko Odaki wrote: > num_vfs is not migrated so use PCI_SRIOV_CTRL_VFE and PCI_SRIOV_NUM_VF > instead. > > Signed-off-by: Akihiko Odaki > --- > include/hw/pci/pcie_sriov.h | 1 - > hw/pci/pcie_sriov.c | 28 > hw/pc

Re: [PATCH 04/18] bsd-user: Implement RISC-V TLS register setup

On 8/2/24 18:34, Ajeet Singh wrote: From: Mark Corbin Added the 'target_cpu_set_tls' function to handle setting the Thread Local Storage (TLS) register for the RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh --- bsd-user/riscv/target_arch_cpu.c | 29

Re: [PATCH 05/18] bsd-user: Add prototype for RISC-V TLS register setup

On 8/2/24 18:34, Ajeet Singh wrote: From: Mark Corbin Included the prototype for the 'target_cpu_set_tls' function in the 'target_arch.h' header file. This function is responsible for setting the Thread Local Storage (TLS) register for RISC-V architecture. Signed-off-by: Mark Corbin Signed-of

Re: [PATCH 06/18] bsd-user: Add RISC-V ELF definitions and hardware capability detection

On 8/2/24 18:34, Ajeet Singh wrote: From: Mark Corbin Introduced RISC-V specific ELF definitions and hardware capability detection. Additionally, a function to retrieve hardware capabilities ('get_elf_hwcap') is implemented, which returns the common bits set in each CPU's ISA strings. Signed-o

Re: [PATCH 06/10] tests/avocado/kvm_xen_guest.py: cope with asset RW requirements

On 1/8/24 17:17, Cleber Rosa wrote: On Thu, Aug 1, 2024 at 8:57 AM Philippe Mathieu-Daudé wrote: I agree those files should not be modified, but I wonder if you thought about any solution to this? Given that the same user writes (downloads) those files, do you think setting file permissions bet

Re: [PATCH] arm/kvm: add support for MTE

On Fri, Aug 02 2024, Ganapatrao Kulkarni wrote: > Hi Peter, > > On 16-07-2024 09:15 pm, Peter Maydell wrote: >> On Tue, 9 Jul 2024 at 07:05, Ganapatrao Kulkarni >> wrote: >>> >>> Extend the 'mte' property for the virt machine to cover KVM as >>> well. For KVM, we don't allocate tag memory, but

Re: [PATCH] vhost: Add VIRTIO_NET_F_RSC_EXT to vhost feature bits

On Fri, Aug 02, 2024 at 10:34:37AM +0300, Yuri Benditovich wrote: > At the moment kernel (vhost) and vhost user backends do not support > this feature (and IMO they do not need to) > In order to support it they need to implement a) coalescing of > segmented TCP packets and b) population of respecti

Re: [PATCH 07/18] bsd-user: Define RISC-V register structures and register copying

On 8/2/24 18:34, Ajeet Singh wrote: From: Mark Corbin Added definitions for RISC-V register structures, including general-purpose registers and floating-point registers, in 'target_arch_reg.h'. Implemented the 'target_copy_regs' function to copy register values from the CPU state to the target r

Re: [PATCH v2 6/7] qapi/block-core: derpecate block-job-change

Vladimir Sementsov-Ogievskiy writes: > On 18.07.24 14:01, Markus Armbruster wrote: >> Vladimir Sementsov-Ogievskiy writes: >> >>> That's a first step to move on newer job-* APIs. >>> >>> The difference between block-job-change and job-change is in >>> find_block_job_locked() vs find_job_locked(

Re: [PATCH] linux-user/elfload: Fix pr_pid values in core files

On 1/8/24 22:23, Ilya Leoshkevich wrote: Analyzing qemu-produced core dumps of multi-threaded apps runs into: (gdb) info threads [...] 21 Thread 0x3ff83cc0740 (LWP 9295) warning: Couldn't find general-purpose registers in core file. in ?? () The reason is that all pr

Re: [PATCH] qmp: Fix higher half vaddrs for [p]memsave

Josh Junon writes: > On Fri, Aug 02, 2024 at 01:39:15PM +0200, Markus Armbruster wrote: [...] >> I'd go for a much smaller solution: change the QMP commands to unsigned, >> keep the HMP commands signed, with a silent conversion just like >> hmp_memory_dump() & friends. >> > > Sounds good to me

Re: [PATCH v2 4/4] virtio-net: Add support for USO features

On Fri, Aug 02, 2024 at 01:30:51PM +0900, Akihiko Odaki wrote: > 4) is the second easiest to implement, but the design of 4) will depend on > whether we will satisfy 2) or 3). In the email I cited earlier, I suggested > an option -use-platform to specify the expectation on the platform. If it is >

Re: [RFC V1 1/6] migration: SCM_RIGHTS for QEMUFile

On 30/06/2024 20:44, Steve Sistare wrote: Define functions to put/get file descriptors to/from a QEMUFile, for qio channels that support SCM_RIGHTS. Maintain ordering such that put(A), put(fd), put(B) followed by get(A), get(fd), get(B) always succeeds. Other get orderings may succeed but

Re: [PATCH v3 08/24] tests/functional: add a module for handling asset download & caching

On 1/8/24 19:02, Daniel P. Berrangé wrote: On Thu, Aug 01, 2024 at 06:20:58PM +0200, Philippe Mathieu-Daudé wrote: On 30/7/24 19:03, Daniel P. Berrangé wrote: The 'Asset' class is a simple module that declares a downloadable asset that can be cached locally. Downloads are stored in the user's h

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