Re: [PULL 00/63] virtio,pci,pc: features,fixes

On 7/22/24 10:16, Michael S. Tsirkin wrote: A couple of fixes are outstanding, will merge later. The following changes since commit a87a7c449e532130d4fa8faa391ff7e1f04ed660: Merge tag 'pull-loongarch-20240719' ofhttps://gitlab.com/gaosong/qemu into staging (2024-07-19 16:28:28 +1000) are

Re: [PATCH v2 6/7] util/fifo8: Expose fifo8_pop_buf()

Hi Mark, On 22/7/24 23:26, Mark Cave-Ayland wrote: On 22/07/2024 17:07, Philippe Mathieu-Daudé wrote: Extract fifo8_pop_buf() from hw/scsi/esp.c and expose it as part of the API. This function takes care of non-contiguous (wrapped) FIFO buffer (which is an implementation detail). I wonder i

Re: [PATCH 2/2] hw/misc/aspeed_hace: Fix SG Accumulative hashing

Hello Alejandro, On 7/22/24 22:15, Alejandro Zeise wrote: Make the Aspeed HACE module use the new qcrypto accumulative hashing functions when in scatter-gather accumulative mode. A hash context will maintain a "running-hash" as each scatter-gather chunk is received. Previously each scatter-gath

[PATCH 01/14] bsd-user:Add CPU initialization and management functions

From: Stacey Son Added function to initialize ARM CPU and check if it supports 64-bit mode. Implemented CPU loop function to handle exceptions and emulate execution of instructions. Added function to clone CPU state to create a new thread. Included AArch64 specific CPU functions for bsd-user to

[PATCH 06/14] bsd-user:Add setup_sigframe_arch function for ARM AArch64

The function utilizes the `get_mcontext` function to retrieve the machine context for the current CPUARMState Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson Message-Id: <20240707191128.10509-7-itac...@freebsd.org> Signed-off-by: Warner Losh --- bsd-user/a

[PATCH 00/14] bsd-user: Misc changes for 9.1 (I hope)

This patch series includes two main sets of patches. To make it simple to review, I've included the changes from my student which the later changes depend on. I've included a change from Jessica and Doug as well. I've reviewed them, but more eyes never hurt. I've also included a number of 'touch u

[PATCH 03/14] bsd-user:Add ARM AArch64 support and capabilities

Added function to access rval2 by accessing the x1 register. Defined ARM AArch64 ELF parameters including mmap and dynamic load addresses. Introduced extensive hardware capability definitions and macros for retrieving hardware capability (hwcap) flags. Implemented function to retrieve ARM AArch64

[PATCH 04/14] bsd-user:Add ARM AArch64 signal handling support

From: Stacey Son Added sigcode setup function for signal trampoline which initializes a sequence of instructions to handle signal returns and exits, copying this code to the target offset. Defined ARM AArch64 specific signal definitions including register indices and sizes, and introduced struc

[PATCH 08/14] bsd-user:Add AArch64 improvements and signal handling functions

From: Stacey Son Added get_ucontext_sigreturn function to check processor state ensuring current execution mode is EL0 and no flags indicating interrupts or exceptions are set. Updated AArch64 code to use CF directly without reading/writing the entire processor state, improving efficiency. Chan

[PATCH 07/14] bsd-user:Add set_mcontext function for ARM AArch64

From: Stacey Son The function copies register values from the provided target_mcontext_t structure to the CPUARMState registers. Note:FP is unfinished upstream but will be a separate commit coming soon. Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson Messag

[PATCH 12/14] bsd-user: Define TARGET_SIGSTACK_ALIGN and use it to round stack

Most (all?) targets require stacks to be properly aligned. Rather than a series of ifdefs in bsd-user/signal.h, instead use a manditory #define for all architectures. Signed-off-by: Warner Losh --- bsd-user/aarch64/target_arch_signal.h | 2 ++ bsd-user/arm/target_arch_signal.h | 2 ++ bsd-us

[PATCH 02/14] bsd-user:Add AArch64 register handling and related functions

From: Stacey Son Added header file for managing CPU register states in FreeBSD user mode. Introduced prototypes for setting and getting thread-local storage (TLS). Implemented AArch64 sysarch() system call emulation and a printing function. Added function for setting up thread upcall to add threa

[PATCH 10/14] bsd-user: Hard wire aarch64 to be 4k pages only

Only support 4k pages for aarch64 binaries. The variable page size stuff isn't working just yet, so put in this lessor-of-evils kludge until that is complete. Signed-off-by: Warner Losh --- target/arm/cpu-param.h | 4 1 file changed, 4 insertions(+) diff --git a/target/arm/cpu-param.h b/ta

[PATCH 14/14] bsd-user: Add aarch64 build to tree

Add the aarch64 bsd-user fragments needed to build the new aarch64 code. Signed-off-by: Warner Losh --- configs/targets/aarch64-bsd-user.mak | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 configs/targets/aarch64-bsd-user.mak diff --git a/configs/targets/aarch64-bsd-user.mak b/con

[PATCH 05/14] bsd-user:Add get_mcontext function for ARM AArch64

From: Stacey Son function to retrieve machine context,it populates the provided target_mcontext_t structure with information from the CPUARMState registers. Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson Message-Id: <20240707191

[PATCH 09/14] bsd-user: Simplify the implementation of execve

From: Doug Rabson This removes the logic which prepends the emulator to each call to execve and fexecve. This is not necessary with the existing imgact_binmisc support and it avoids the need to install the emulator binary into jail environments when using 'binmiscctl --pre-open'. Signed-off-by:

[PATCH 11/14] bsd-user: Sync fork_start/fork_end with linux-user

From: Jessica Clarke This reorders some of the calls, deduplicates code between branches and, most importantly, fixes a double end_exclusive call in the parent that will cause exclusive_context_count to go negative. Signed-off-by: Jessica Clarke Pull-Request: https://github.com/qemu-bsd-user/qe

[PATCH 13/14] bsd-user: Make compile for non-linux user-mode stuff

We include the files that define PR_MTE_TCF_SHIFT only on Linux, but use them unconditionally. Restrict its use to Linux-only. Signed-off-by: Warner Losh --- target/arm/gdbstub64.c | 4 1 file changed, 4 insertions(+) diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 2e2bc

Re: [PATCH v2 7/7] util/fifo8: Introduce fifo8_discard()

On 22/07/2024 17:07, Philippe Mathieu-Daudé wrote: Add the fifo8_discard() helper for clarity. It is a simple wrapper over fifo8_pop_buf(). Signed-off-by: Philippe Mathieu-Daudé --- include/qemu/fifo8.h | 8 hw/scsi/esp.c| 2 +- util/fifo8.c | 6 ++ 3 files ch

Re: [PATCH 14/14] bsd-user: Add aarch64 build to tree

Hi Warner, On 22/7/24 23:43, Warner Losh wrote: Add the aarch64 bsd-user fragments needed to build the new aarch64 code. Signed-off-by: Warner Losh --- configs/targets/aarch64-bsd-user.mak | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 configs/targets/aarch64-bsd-user.mak C

Re: [PATCH 13/14] bsd-user: Make compile for non-linux user-mode stuff

Hi Warner, On 22/7/24 23:43, Warner Losh wrote: We include the files that define PR_MTE_TCF_SHIFT only on Linux, but use them unconditionally. Restrict its use to Linux-only. We should check that in meson, i.e.: config_host_data.set('CONFIG_PRCTL_PR_MTE_TCF_SHIFT', cc.has

Re: [PATCH 14/14] bsd-user: Add aarch64 build to tree

On Mon, Jul 22, 2024 at 3:54 PM Philippe Mathieu-Daudé wrote: > Hi Warner, > > On 22/7/24 23:43, Warner Losh wrote: > > Add the aarch64 bsd-user fragments needed to build the new aarch64 code. > > > > Signed-off-by: Warner Losh > > --- > > configs/targets/aarch64-bsd-user.mak | 3 +++ > > 1 f

Re: [PATCH 14/14] bsd-user: Add aarch64 build to tree

On 23/7/24 00:06, Warner Losh wrote: On Mon, Jul 22, 2024 at 3:54 PM Philippe Mathieu-Daudé mailto:phi...@linaro.org>> wrote: Hi Warner, On 22/7/24 23:43, Warner Losh wrote: > Add the aarch64 bsd-user fragments needed to build the new aarch64 code. > > Signed-off-

Re: [PATCH 0/4] target/arm: Various minor SME bugfixes

On 7/23/24 03:29, Peter Maydell wrote: Peter Maydell (4): target/arm: Don't assert for 128-bit tile accesses when SVL is 128 target/arm: Fix UMOPA/UMOPS of 16-bit values target/arm: Avoid shifts by -1 in tszimm_shr() and tszimm_shl() target/arm: Ignore SMCR_EL2.LEN and SVCR_EL2.LEN i

Re: [PATCH v6 4/4] docs: add test for firmware.json QAPI

Hi Thomas, On 19/7/24 09:37, Thomas Weißschuh wrote: To make sure that the QAPI description stays valid, add a testcase. Suggested-by: Philippe Mathieu-Daudé Link: https://lore.kernel.org/qemu-devel/d9ce0234-4beb-4b90-b14c-76810d3b8...@linaro.org/ Reviewed-by: Daniel P. Berrangé Signed-off-b

Re: [PATCH 0/3] Resolve vt82c686 and piix4 qemu_irq memory leaks

Am 20. Juli 2024 18:38:42 UTC schrieb "Michael S. Tsirkin" : >On Thu, Jul 04, 2024 at 10:58:51PM +0200, Bernhard Beschow wrote: >> This series first turns vt82c686's "INTR" pin into a named GPIO for better >> comprehensibility. It then continues fixing qemu_irq memory leaks in vt82c686 >> and pi

Re: [PATCH v2 6/7] util/fifo8: Expose fifo8_pop_buf()

On 22/07/2024 22:39, Philippe Mathieu-Daudé wrote: Hi Mark, On 22/7/24 23:26, Mark Cave-Ayland wrote: On 22/07/2024 17:07, Philippe Mathieu-Daudé wrote: Extract fifo8_pop_buf() from hw/scsi/esp.c and expose it as part of the API. This function takes care of non-contiguous (wrapped) FIFO buf

Re: [PULL 00/25] Misc QEMU-GA patches 2024-07-22

On 7/22/24 17:00, Konstantin Kostiuk wrote: The following changes since commit 23fa74974d8c96bc95cbecc0d4e2d90f984939f6: Merge tag 'pull-target-arm-20240718' ofhttps://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-07-19 07:02:17 +1000) are available in the Git repository at:

Re: [PULL 00/16] Final bits for 9.1-rc0 (docker, plugins, gdbstub, semihosting)

Philippe Mathieu-Daudé writes: > On 22/7/24 23:07, Philippe Mathieu-Daudé wrote: >> Hi Alex, >> On 22/7/24 13:03, Alex Bennée wrote: >>> warn: No match for commit c135d5eaafe7aa2533da663d8e5a34a424b71eb9 >>> found at https://gitlab.com/stsquad/qemu.git >>> warn: Are you sure you pushed >>> 'pull-

Re: [RFC PATCH v2 0/9] migration/multifd: Remove multifd_send_state->pages

On Mon, Jul 22, 2024 at 06:20:28PM -0300, Fabiano Rosas wrote: > Peter Xu writes: > > > On Mon, Jul 22, 2024 at 05:21:48PM -0300, Fabiano Rosas wrote: > >> Peter Xu writes: > >> > >> > On Mon, Jul 22, 2024 at 02:59:05PM -0300, Fabiano Rosas wrote: > >> >> Hi, > >> >> > >> >> In this v2 I took

[PULL v2 00/16] Final bits for 9.1-rc0 (docker, plugins, gdbstub, semihosting)

The following changes since commit a7ddb48bd1363c8bcdf42776d320289c42191f01: Merge tag 'pull-aspeed-20240721' of https://github.com/legoater/qemu into staging (2024-07-22 07:52:05 +1000) are available in the Git repository at: https://gitlab.com/stsquad/qemu.git tags/pull-maintainer-9.1-rc0

Re: [PATCH 13/14] bsd-user: Make compile for non-linux user-mode stuff

Philippe Mathieu-Daudé writes: > Hi Warner, > > On 22/7/24 23:43, Warner Losh wrote: >> We include the files that define PR_MTE_TCF_SHIFT only on Linux, but use >> them unconditionally. Restrict its use to Linux-only. > > We should check that in meson, i.e.: > > config_host_data.set('CONFIG_PRCTL

[PATCH] plugins: fix race condition with scoreboards

A deadlock can be created if a new vcpu (a) triggers a scoreboard reallocation, and another vcpu (b) wants to create a new scoreboard at the same time. In this case, (a) holds the plugin lock, and starts an exclusive section, waiting for (b). But at the same time, (b) is waiting for plugin lock.

Re: [PATCH 1/2] util/getauxval: Ensure setting errno if not found

On 7/21/24 19:08, Vivian Wang wrote: Sometimes zero is a valid value for getauxval (e.g. AT_EXECFD). Make sure that we can distinguish between a valid zero value and a not found entry by setting errno. Ignore getauxval from sys/auxv.h on glibc < 2.19 because it does not set errno. Signed-off-by

Re: [PATCH 2/2] linux-user/main: Check errno when getting AT_EXECFD

On 7/21/24 19:08, Vivian Wang wrote: It's possible for AT_EXECFD to end up with a valid value of 0. Check errno when using qemu_getauxval instead of return value to handle this case. Not handling this case leads to a confusing condition where the executable ends up as fd 0, i.e. stdin. Signed-o

Re: [PULL 21/30] target/riscv: Implement privilege mode filtering for cycle/instret

On Sat, Jul 20, 2024 at 7:44 AM Peter Maydell wrote: > > On Thu, 18 Jul 2024 at 03:12, Alistair Francis wrote: > > > > From: Atish Patra > > > > Privilege mode filtering can also be emulated for cycle/instret by > > tracking host_ticks/icount during each privilege mode switch. This > > patch imp

Re: [PATCH] plugins: fix race condition with scoreboards

@Alex: If possible, this patch should be included for the release to come. On 7/22/24 16:23, Pierrick Bouvier wrote: A deadlock can be created if a new vcpu (a) triggers a scoreboard reallocation, and another vcpu (b) wants to create a new scoreboard at the same time. In this case, (a) holds th

Re: [PULL 05/30] target/riscv: Support Zama16b extension

On Thu, Jul 18, 2024 at 12:10 PM Alistair Francis wrote: > > From: LIU Zhiwei > > Zama16b is the property that misaligned load/stores/atomics within > a naturally aligned 16-byte region are atomic. > > According to the specification, Zama16b applies only to AMOs, loads > and stores defined in the

Re: [PULL 26/30] target/riscv: Do not setup pmu timer if OF is disabled

On Sat, Jul 20, 2024 at 8:19 AM Peter Maydell wrote: > > On Thu, 18 Jul 2024 at 03:15, Alistair Francis wrote: > > > > From: Atish Patra > > > > The timer is setup function is invoked in both hpmcounter > > write and mcountinhibit write path. If the OF bit set, the > > LCOFI interrupt is disable

Re: [PULL 29/63] hw/pci: Do not add ROM BAR for SR-IOV VF

On Mon, Jul 22, 2024 at 11:21:13PM +0900, Akihiko Odaki wrote: > On 2024/07/22 9:17, Michael S. Tsirkin wrote: > > From: Akihiko Odaki > > > > A SR-IOV VF cannot have a ROM BAR. > > > > Co-developed-by: Yui Washizu > > Signed-off-by: Akihiko Odaki > > Message-Id: <20240715-sriov-v5-1-3f5539093

Re: [PULL 00/63] virtio,pci,pc: features,fixes

On Tue, Jul 23, 2024 at 07:32:56AM +1000, Richard Henderson wrote: > On 7/22/24 10:16, Michael S. Tsirkin wrote: > > A couple of fixes are outstanding, will merge later. > > > > > > The following changes since commit a87a7c449e532130d4fa8faa391ff7e1f04ed660: > > > >Merge tag 'pull-loongarch-

Re: [PATCH 0/3] Resolve vt82c686 and piix4 qemu_irq memory leaks

On Mon, Jul 22, 2024 at 10:21:30PM +, Bernhard Beschow wrote: > > > Am 20. Juli 2024 18:38:42 UTC schrieb "Michael S. Tsirkin" : > >On Thu, Jul 04, 2024 at 10:58:51PM +0200, Bernhard Beschow wrote: > >> This series first turns vt82c686's "INTR" pin into a named GPIO for better > >> comprehens

Re: [PULL 26/30] target/riscv: Do not setup pmu timer if OF is disabled

On Tue, Jul 23, 2024 at 9:33 AM Atish Kumar Patra wrote: > > On Sat, Jul 20, 2024 at 8:19 AM Peter Maydell > wrote: > > > > On Thu, 18 Jul 2024 at 03:15, Alistair Francis wrote: > > > > > > From: Atish Patra > > > > > > The timer is setup function is invoked in both hpmcounter > > > write and

Re: [PULL 00/63] virtio,pci,pc: features,fixes

On 7/23/24 10:20, Michael S. Tsirkin wrote: Fails ubsan testing: https://gitlab.com/qemu-project/qemu/-/jobs/7397450714 ../publish/hw/net/virtio-net.c:3895:18: runtime error: member access within null pointer of type 'struct vhost_net' r~ Thanks! this is just make check under ubsan build, r

Re: [PULL 26/30] target/riscv: Do not setup pmu timer if OF is disabled

On 7/23/24 10:43, Alistair Francis wrote: #define get_field(reg, mask) (((reg) & \ (uint64_t)(mask)) / ((mask) & ~((mask) << 1))) Notice that part of this expression is "(mask) << 1". So Coverity complains that we took a constant value and shifted it right off the top. I think

Re: [PATCH 09/14] bsd-user: Simplify the implementation of execve

On 7/23/24 07:43, Warner Losh wrote: From: Doug Rabson This removes the logic which prepends the emulator to each call to execve and fexecve. This is not necessary with the existing imgact_binmisc support and it avoids the need to install the emulator binary into jail environments when using 'bi

[PATCH v4 0/7] Rework x86 page table walks

This version of the 'info pg' command adopts Peter Maydell's request to write guest-agnostic page table iterator and accessor code, along with architecture-specific hooks. The first patch in this series contributes a generic page table iterator and an x86 instantiation. As a client, we first intro

[PATCH v4 1/7] Code motion: expose some TCG definitions for page table walk consolidation.

Signed-off-by: Don Porter --- include/hw/core/sysemu-cpu-ops.h | 6 + target/i386/cpu.h| 5 ++-- target/i386/helper.c | 36 +++ target/i386/tcg/helper-tcg.h | 32 target/i386/tcg/seg_helper.c

[PATCH v4 7/7] Convert x86_mmu_translate() to use common code.

Signed-off-by: Don Porter --- target/i386/tcg/helper-tcg.h | 2 +- target/i386/tcg/sysemu/excp_helper.c | 417 ++- 2 files changed, 30 insertions(+), 389 deletions(-) diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index 1cbeab9161..8f63

[PATCH v4 3/7] Add an "info pg" command that prints the current page tables

The new "info pg" monitor command prints the current page table, including virtual address ranges, flag bits, and snippets of physical page numbers. Completely filled regions of the page table with compatible flags are "folded", with the result that the complete output for a freshly booted x86-64

[PATCH v4 4/7] Convert 'info tlb' to use generic iterator.

If the the guest is using nested page tables, change the output format slightly, to first show guest virtual to guest physical, then guest physical to host physical, as below: (qemu) info tlb Info guest TLB (guest virtual to guest physical): 00800080: 0076a000 ---U-P 00800

[PATCH v4 2/7] Import vmcs12 definition from Linux/KVM

Signed-off-by: Don Porter --- target/i386/kvm/vmcs12.h | 213 +++ 1 file changed, 213 insertions(+) create mode 100644 target/i386/kvm/vmcs12.h diff --git a/target/i386/kvm/vmcs12.h b/target/i386/kvm/vmcs12.h new file mode 100644 index 00..c7b139f4db

[PATCH v4 6/7] Convert x86_cpu_get_memory_mapping() to use generic iterators

Signed-off-by: Don Porter --- target/i386/arch_memory_mapping.c | 305 ++ 1 file changed, 19 insertions(+), 286 deletions(-) diff --git a/target/i386/arch_memory_mapping.c b/target/i386/arch_memory_mapping.c index ef29e4b42f..bb97443f0f 100644 --- a/target/i386/arch_

[PATCH v4 5/7] Convert 'info mem' to use generic iterator

In the case of nested paging, change the output slightly to show both the guest's and host's view. For example: (qemu) info mem Info guest mem (guest virtual to guest physical mappings): 00800080-00800085c000 0005c000 ur- 008000a0-008000a1 0001 ur-

Re: [PATCH 10/14] bsd-user: Hard wire aarch64 to be 4k pages only

On 7/23/24 07:43, Warner Losh wrote: Only support 4k pages for aarch64 binaries. The variable page size stuff isn't working just yet, so put in this lessor-of-evils kludge until that is complete. Hmm. In what way is it not working? What if we limit this to bsd-user/main.c instead? set_pref

Re: [PATCH 11/14] bsd-user: Sync fork_start/fork_end with linux-user

On 7/23/24 07:43, Warner Losh wrote: -/* - * Child processes created by fork() only have a single thread. Discard - * information about the parent threads. - */ +/* Child processes created by fork() only have a single thread. + Discard informati

Re: [PATCH 12/14] bsd-user: Define TARGET_SIGSTACK_ALIGN and use it to round stack

On 7/23/24 07:43, Warner Losh wrote: Most (all?) targets require stacks to be properly aligned. Rather than a series of ifdefs in bsd-user/signal.h, instead use a manditory #define for all architectures. Signed-off-by: Warner Losh --- bsd-user/aarch64/target_arch_signal.h | 2 ++ bsd-user/arm

Re: [PATCH 13/14] bsd-user: Make compile for non-linux user-mode stuff

On 7/23/24 07:43, Warner Losh wrote: We include the files that define PR_MTE_TCF_SHIFT only on Linux, but use them unconditionally. Restrict its use to Linux-only. Signed-off-by: Warner Losh --- target/arm/gdbstub64.c | 4 1 file changed, 4 insertions(+) Reviewed-by: Richard Henderson

Re: [PULL 05/30] target/riscv: Support Zama16b extension

On 2024/7/23 7:32, Alistair Francis wrote: On Thu, Jul 18, 2024 at 12:10 PM Alistair Francis wrote: From: LIU Zhiwei Zama16b is the property that misaligned load/stores/atomics within a naturally aligned 16-byte region are atomic. According to the specification, Zama16b applies only to AMO

Re: [PATCH 14/14] bsd-user: Add aarch64 build to tree

On 7/23/24 08:11, Philippe Mathieu-Daudé wrote: On 23/7/24 00:06, Warner Losh wrote: On Mon, Jul 22, 2024 at 3:54 PM Philippe Mathieu-Daudé > wrote:     Hi Warner,     On 22/7/24 23:43, Warner Losh wrote: > Add the aarch64 bsd-user fragments needed to build th

[PATCH 1/1] target/riscv: Remove redundant insn length check for zama16b

Both trans_fld/fsd/flw/fsw and gen_load/store will never be a translation function for compressed instructions, thus we can remove instruction length check for them. Suggested-by: Alistair Francis Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvd.c.inc | 4 ++-- target/riscv/insn_

Re: [PATCH 1/1] target/riscv: Remove redundant insn length check for zama16b

On 7/23/24 11:30, LIU Zhiwei wrote: Both trans_fld/fsd/flw/fsw and gen_load/store will never be a translation function for compressed instructions, thus we can remove instruction length check for them. Suggested-by: Alistair Francis Signed-off-by: LIU Zhiwei That is both false (trans_fld is

Re: [PULL 00/12] QTests, Avocado and s390x fixes for 9.1 softfreeze

On 7/22/24 22:00, Thomas Huth wrote: Hi Richard! The following changes since commit a7ddb48bd1363c8bcdf42776d320289c42191f01: Merge tag 'pull-aspeed-20240721' ofhttps://github.com/legoater/qemu into staging (2024-07-22 07:52:05 +1000) are available in the Git repository at: https://g

RE: [PATCH v5 05/13] vfio/iommufd: Introduce auto domain creation

>-Original Message- >From: Cédric Le Goater >Subject: Re: [PATCH v5 05/13] vfio/iommufd: Introduce auto domain >creation > >On 7/22/24 10:50, Joao Martins wrote: >> On 22/07/2024 06:16, Duan, Zhenzhong wrote: -Original Message- From: Joao Martins Subject: [PATCH v

Re: [PATCH] intel-iommu: fix Read DMAR IQA REG DW

> > When dmar_readq or devmem2 read the DW of IQA always 0UL because > > "& VTD_IQA_QS". So, try to fix it. > > > > case: > > after vtd_mem_write > > IQA val: 0x100206801 > > > > after vtd_mem_read > > IQA val: 0x100206001 > > > > Signed-off-by: yeeli > > > how was this tested? If VT-D hardware s

RE: [PATCH 2/2] vfio/ccw: Don't initialize HOST_IOMMU_DEVICE with mdev

>-Original Message- >From: Eric Farman >Subject: Re: [PATCH 2/2] vfio/ccw: Don't initialize HOST_IOMMU_DEVICE >with mdev > >On Mon, 2024-07-22 at 17:36 +0200, Cédric Le Goater wrote: >> On 7/22/24 17:09, Joao Martins wrote: >> > On 22/07/2024 15:57, Eric Farman wrote: >> > > On Mon, 2024

Re: [PATCH] intel-iommu: fix Read DMAR IQA REG DW

> or devmem2 read the reg: > > "devmem2 0xfed90090" > "/dev/mem opened." > "Memory mapped at address 0x7f983014f000." > "Value at address 0xFED90090 (0x7f983014f000): 0x0" Sorry, correct the devmem2 read value. "Value at address 0xFED90090 (0x7f983014f000): 0x1DA801"

RE: [PATCH v5 09/13] vfio/iommufd: Probe and request hwpt dirty tracking capability

>-Original Message- >From: Joao Martins >Subject: Re: [PATCH v5 09/13] vfio/iommufd: Probe and request hwpt dirty >tracking capability > >On 22/07/2024 15:09, Joao Martins wrote: >> On 22/07/2024 09:58, Joao Martins wrote: >>> On 22/07/2024 07:05, Duan, Zhenzhong wrote: > -

[PATCH 07/12] target/ppc: Merge helper_{dcbz,dcbzep}

Merge the two and pass the mmu_idx directly from translation. Swap the argument order in dcbz_common to avoid extra swaps. Reviewed-by: Nicholas Piggin Signed-off-by: Richard Henderson --- target/ppc/helper.h | 3 +-- target/ppc/mem_helper.c | 14 -- target/ppc/translate.c |

[PATCH 09/12] target/s390x: Use user_or_likely in do_access_memset

Eliminate the ifdef by using a predicate that is always true with CONFIG_USER_ONLY. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/s390x/tcg/mem_helper.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x

[PATCH 00/12] tcg patch queue

The following changes since commit a7ddb48bd1363c8bcdf42776d320289c42191f01: Merge tag 'pull-aspeed-20240721' of https://github.com/legoater/qemu into staging (2024-07-22 07:52:05 +1000) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20240723 for

[PATCH 05/12] target/ppc: Hoist dcbz_size out of dcbz_common

The 970 logic does not apply to dcbzep, which is an e500 insn. Reviewed-by: Nicholas Piggin Reviewed-by: BALATON Zoltan Signed-off-by: Richard Henderson --- target/ppc/mem_helper.c | 30 +++--- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/target/ppc/m

[PATCH 01/12] accel/tcg: Move {set, clear}_helper_retaddr to cpu_ldst.h

Use of these in helpers goes hand-in-hand with tlb_vaddr_to_host and other probing functions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- accel/tcg/user-retaddr.h | 28 include/exec/cpu_ldst.h | 34 ++ accel/tcg/c

[PATCH 10/12] target/s390x: Use user_or_likely in access_memmove

Invert the conditional, indent the block, and use the macro that expands to true for user-only. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/s390x/tcg/mem_helper.c | 54 +-- 1 file changed, 26 insertions(+), 28 deletions(-) diff --git a

[PATCH 08/12] target/ppc: Improve helper_dcbz for user-only

Mark the reserve_addr check unlikely. Use tlb_vaddr_to_host instead of probe_write, relying on the memset itself to test for page writability. Use set/clear_helper_retaddr so that we can properly unwind on segfault. With this, a trivial loop around guest memset will no longer spend nearly 25% of

[PATCH 02/12] target/arm: Use set/clear_helper_retaddr in helper-a64.c

Use these in helper_dc_dva and the FEAT_MOPS routines to avoid a race condition with munmap in another thread. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/helper-a64.c | 14 -- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/target/a

[PATCH 06/12] target/ppc: Split out helper_dbczl for 970

We can determine at translation time whether the insn is or is not dbczl. We must retain a runtime check against the HID5 register, but we can move that to a separate function that never affects other ppc models. Reviewed-by: Nicholas Piggin Reviewed-by: BALATON Zoltan Signed-off-by: Richard He

[PATCH 12/12] target/riscv: Simplify probing in vext_ldff

The current pairing of tlb_vaddr_to_host with extra is either inefficient (user-only, with page_check_range) or incorrect (system, with probe_pages). For proper non-fault behaviour, use probe_access_flags with its nonfault parameter set to true. Reviewed-by: Max Chou Acked-by: Alistair Francis

[PATCH 11/12] target/s390x: Use set/clear_helper_retaddr in mem_helper.c

Avoid a race condition with munmap in another thread. For access_memset and access_memmove, manage the value within the helper. For uses of access_{get,set}_byte, manage the value across the for loops. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/s390x/tcg/mem_helper.

[PATCH 04/12] target/ppc/mem_helper.c: Remove a conditional from dcbz_common()

From: BALATON Zoltan Instead of passing a bool and select a value within dcbz_common() let the callers pass in the right value to avoid this conditional statement. On PPC dcbz is often used to zero memory and some code uses it a lot. This change improves the run time of a test case that copies me

[PATCH 03/12] target/arm: Use set/clear_helper_retaddr in SVE and SME helpers

Avoid a race condition with munmap in another thread. Use around blocks that exclusively use "host_fn". Keep the blocks as small as possible, but without setting and clearing for every operation on one page. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/sme_help

Re: [PATCH 1/1] target/riscv: Remove redundant insn length check for zama16b

On Tue, Jul 23, 2024 at 12:13 PM Richard Henderson wrote: > > On 7/23/24 11:30, LIU Zhiwei wrote: > > Both trans_fld/fsd/flw/fsw and gen_load/store will never be a > > translation function for compressed instructions, thus we can > > remove instruction length check for them. > > > > Suggested-by:

Re: [PULL v2 00/16] Final bits for 9.1-rc0 (docker, plugins, gdbstub, semihosting)

On 7/23/24 09:04, Alex Bennée wrote: The following changes since commit a7ddb48bd1363c8bcdf42776d320289c42191f01: Merge tag 'pull-aspeed-20240721' ofhttps://github.com/legoater/qemu into staging (2024-07-22 07:52:05 +1000) are available in the Git repository at: https://gitlab.com/stsqu

Re: [PATCH] ppc/pnv: Update Power10's cfam id to use Power10 DD2

On Mon Jul 22, 2024 at 7:17 PM AEST, Aditya Gupta wrote: > Hello, > > Any comments on this change ? > > Though this isn't urgent and won't change behaviour much, mainly other > than skiboot recognising the chip as P10 DD2. Hey Aditya, Yeah I missed this in my last PR but I have it in my tree. T

Re: [PATCH v5 1/5] target/ppc: reduce code duplication across Power9/10 init code

On Thu Jun 6, 2024 at 10:16 PM AEST, Aditya Gupta wrote: > From: Harsh Prateek Bora > > Power9/10 initialization code consists of a lot of logical OR of > various flag bits as supported by respective Power platform during its > initialization, most of which is duplicated and only selected bits are

Re: [PATCH v5 2/5] target/ppc: Add Power11 DD2.0 processor

On Thu Jun 6, 2024 at 10:16 PM AEST, Aditya Gupta wrote: > Add CPU target code to add support for new Power11 Processor. > > Power11 core is same as Power10, hence reuse functions defined for > Power10. > > Cc: Cédric Le Goater > Cc: Daniel Henrique Barboza > Cc: Frédéric Barrat > Cc: Harsh Prat

Re: [PATCH v5 3/5] ppc/pseries: Add Power11 cpu type

On Thu Jun 6, 2024 at 10:16 PM AEST, Aditya Gupta wrote: > Add sPAPR CPU Core definition for Power11 > > Cc: David Gibson (reviewer:sPAPR (pseries)) > Cc: Harsh Prateek Bora (reviewer:sPAPR (pseries)) > Cc: Cédric Le Goater > Cc: Daniel Henrique Barboza > Cc: Frédéric Barrat > Cc: Harsh Pratee

RE: [PATCH v5 05/13] vfio/iommufd: Introduce auto domain creation

>-Original Message- >From: Joao Martins >Subject: Re: [PATCH v5 05/13] vfio/iommufd: Introduce auto domain >creation > >On 22/07/2024 06:16, Duan, Zhenzhong wrote: >>> -Original Message- >>> From: Joao Martins >>> Subject: [PATCH v5 05/13] vfio/iommufd: Introduce auto domain >cr

Re: [PATCH] ppc/pnv: Update Power10's cfam id to use Power10 DD2

Hi Nick, On 23/07/24 09:48, Nicholas Piggin wrote: On Mon Jul 22, 2024 at 7:17 PM AEST, Aditya Gupta wrote: Hello, Any comments on this change ? Though this isn't urgent and won't change behaviour much, mainly other than skiboot recognising the chip as P10 DD2. Hey Aditya, Yeah I missed th

RE: [PATCH v6 1/9] vfio/iommufd: Introduce auto domain creation

>-Original Message- >From: Joao Martins >Subject: [PATCH v6 1/9] vfio/iommufd: Introduce auto domain creation > >There's generally two modes of operation for IOMMUFD: > >1) The simple user API which intends to perform relatively simple things >with IOMMUs e.g. DPDK. The process generall

RE: [PATCH v6 8/9] vfio/migration: Don't block migration device dirty tracking is unsupported

>-Original Message- >From: Joao Martins >Subject: [PATCH v6 8/9] vfio/migration: Don't block migration device dirty >tracking is unsupported > >By default VFIO migration is set to auto, which will support live >migration if the migration capability is set *and* also dirty page >tracking

Re: [PATCH 1/2] vhost-user: add a write-read lock

On Sun, 21 Jul 2024 at 01:11, Michael S. Tsirkin wrote: > So it's not a rw lock. It's just a mutex. > Lock should be named after what they protect, not > after where they are held. > In this case, this ensures only 1 request is > outstanding at a time. > So vhost_user_request_reply_lock Okay, wil

Re: [PATCH v5 5/5] target/ppc: Fix regression due to Power10 and Power11 having same PCR

On Thu Jun 6, 2024 at 10:16 PM AEST, Aditya Gupta wrote: > Power11 has the same PCR (Processor Compatibility Register) value, as > Power10. > > Due to this, QEMU considers Power11 as a valid compat-mode for Power10, > ie. earlier it was possible to run QEMU with '-M > pseries,max-compat-mode=power

Re: [PATCH 10/14] bsd-user: Hard wire aarch64 to be 4k pages only

On Mon, Jul 22, 2024 at 7:10 PM Richard Henderson < richard.hender...@linaro.org> wrote: > On 7/23/24 07:43, Warner Losh wrote: > > Only support 4k pages for aarch64 binaries. The variable page size stuff > > isn't working just yet, so put in this lessor-of-evils kludge until that > > is complete.

Re: [PATCH v5 2/5] target/ppc: Add Power11 DD2.0 processor

Hi Nick, On 23/07/24 10:00, Nicholas Piggin wrote: <...snip...> +{ /* POWER11, ISA3.10 */ +.name = "power11", +.pvr = CPU_POWERPC_LOGICAL_3_10_PLUS, Might call that _P11 rather than _PLUS, but I can fold that in my tree. Sure, makes sense, I can make these changes, and se

Re: [PATCH v5 1/5] target/ppc: reduce code duplication across Power9/10 init code

On 23/07/24 09:51, Nicholas Piggin wrote: On Thu Jun 6, 2024 at 10:16 PM AEST, Aditya Gupta wrote: From: Harsh Prateek Bora Power9/10 initialization code consists of a lot of logical OR of various flag bits as supported by respective Power platform during its initialization, most of which is

Re: [PATCH 0/2] Postcopy migration and vhost-user errors

On Sun, 21 Jul 2024 at 01:11, Michael S. Tsirkin wrote: > > > > On Wed, Jul 17, 2024 at 04:55:52AM -0400, Michael S. Tsirkin wrote: > > > > > I just want to understand how we managed to have two threads > > > > > talking in parallel. BQL is normally enough, which path > > > > > manages to invoke v

RE: [PATCH v6 9/9] vfio/common: Allow disabling device dirty page tracking

>-Original Message- >From: Joao Martins >Subject: [PATCH v6 9/9] vfio/common: Allow disabling device dirty page >tracking > >The property 'x-pre-copy-dirty-page-tracking' allows disabling the whole >tracking of VF pre-copy phase of dirty page tracking, though it means >that it will only

Re: [PATCH 14/14] bsd-user: Add aarch64 build to tree

On Mon, Jul 22, 2024 at 7:17 PM Richard Henderson < richard.hender...@linaro.org> wrote: > On 7/23/24 08:11, Philippe Mathieu-Daudé wrote: > > On 23/7/24 00:06, Warner Losh wrote: > >> > >> > >> On Mon, Jul 22, 2024 at 3:54 PM Philippe Mathieu-Daudé < > phi...@linaro.org > >>

Re: [PATCH v5 5/5] target/ppc: Fix regression due to Power10 and Power11 having same PCR

On 23/07/24 10:28, Nicholas Piggin wrote: On Thu Jun 6, 2024 at 10:16 PM AEST, Aditya Gupta wrote: Power11 has the same PCR (Processor Compatibility Register) value, as Power10. Due to this, QEMU considers Power11 as a valid compat-mode for Power10, ie. earlier it was possible to run QEMU wit

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