According to RISC-V Debug specification, the optional textra32 and
textra64 trigger CSRs can be used to configure additional matching
conditions for the triggers. For example, if the textra.MHSELECT field
is set to 4 (mcontext), this trigger will only match or fire if the low
bits of mcontext/hcont
According to RISC-V Debug specification, the optional textra32 and textra64
trigger CSRs can be used to configure additional matching conditions for the
triggers.
This series support to write MHVALUE and MHSELECT fields into textra32 and
textra64 trigger CSRs. Besides, the additional matching cond
This commit allows program to write textra trigger CSR for type 2, 3, 6
triggers. In this preliminary patch, the textra.MHVALUE and the
textra.MHSELECT fields are allowed to be configured. Other fields, such
as textra.SBYTEMASK, textra.SVALUE, and textra.SSELECT, are hardwired to
zero for now.
For
From: Jamin Lin
Fix coding style issues from checkpatch.pl
Test command:
./scripts/checkpatch.pl --no-tree -f hw/arm/aspeed.c
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed.c | 21 ++---
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/
Coverity reports a possible integer overflow because routine
aspeeed_smc_hclk_divisor() has a codepath returning 0, which could
lead to an integer overflow when computing variable 'hclk_shift' in
the caller aspeed_smc_dma_calibration().
The value passed to aspeed_smc_hclk_divisor() is always betwe
From: Cédric Le Goater
The QEMU device model representing the eMMC device of the machine is
currently created with type SD_CARD. Change the type to EMMC now that
it is available.
Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
Tested-by: Andrew Jeffery
Reviewed-by: Philippe Mathie
The image was built using the process described in commit c8cb19876d3e
("hw/sd/sdcard: Support boot area in emmc image") with artefacts from
the latest successful build of the IBM P10 BMC platform available on:
https://jenkins.openbmc.org/job/ci-openbmc/distro=ubuntu,label=docker-builder,target
From: Cédric Le Goater
Bit SCU500[2] of the AST2600 controls the boot device of the SoC.
Future changes will configure this bit to boot from eMMC disk images
specially built for this purpose.
Signed-off-by: Joel Stanley
Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
Tested-by: A
From: Cédric Le Goater
The first boot area partition (64K) of the eMMC device should contain
an initial boot loader (u-boot SPL). Load it as a ROM only if an eMMC
device is available to boot from but no flash device is.
Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
Tested-by: And
From: Cédric Le Goater
When the boot-from-eMMC HW strapping bit is set, use the 'boot-config'
property to set the boot config register to boot from the first boot
area partition of the eMMC device. Also set the boot partition size
of the device.
Signed-off-by: Cédric Le Goater
Reviewed-by: Andr
From: Jamin Lin
Add ADC model for AST2700 ADC support.
The ADC controller registers base address is start at
0x14C0_ and its address space is 0x1000.
The ADC controller interrupt is connected to
GICINT130_INTC group at bit 16. The GIC IRQ is 130.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric
From: Cédric Le Goater
To change default behavior of a machine and boot from eMMC, future
changes will add a machine option to let the user configure the
boot-from-eMMC HW strapping bit. Add a new machine attribute first.
Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
Tested-by: A
The following changes since commit a87a7c449e532130d4fa8faa391ff7e1f04ed660:
Merge tag 'pull-loongarch-20240719' of https://gitlab.com/gaosong/qemu into
staging (2024-07-19 16:28:28 +1000)
are available in the Git repository at:
https://github.com/legoater/qemu/ tags/pull-aspee
From: Cédric Le Goater
Report support on the AST2600 SoC if the boot-from-eMMC HW strapping
bit is set at the board level. AST2700 also has support but it is not
yet ready in QEMU and others SoCs do not have support, so return false
always for these.
Signed-off-by: Cédric Le Goater
Reviewed-by:
From: Jamin Lin
According to the datasheet of ASPEED SOCs,
an I2C controller owns 8KB of register space for AST2700,
owns 4KB of register space for AST2600, AST2500 and AST2400,
and owns 64KB of register space for AST1030.
It set the memory region size 4KB by default and it does not compatible
r
From: Cédric Le Goater
This value is taken from a running Rainier machine.
Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
Tested-by: Andrew Jeffery
Tested-by: Philippe Mathieu-Daudé
---
hw/arm/aspeed.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/a
From: Cédric Le Goater
The default behavior of some Aspeed machines is to boot from the eMMC
device, like the rainier-bmc. Others like ast2600-evb could also boot
from eMMC if the HW strapping boot-from-eMMC bit was set. Add a
property to set or unset this bit. This is useful to test boot images.
From: Jamin Lin
According to the datasheet of ASPEED SOCs,
each I2C bus has their own pool buffer since AST2500.
Only AST2400 utilized a pool buffer share to all I2C bus.
And firmware required to set the offset of pool buffer
by writing "Function Control Register(I2CD 00)"
To make this model mo
From: Jamin Lin
AST2700 and AST2600 ADC controllers are identical.
Introduce ast2700 class and set 2 engines.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
include/hw/adc/aspeed_adc.h | 1 +
hw/adc/aspeed_adc.c | 16
2 files changed, 17 insertions(+)
di
Peter Maydell said my second patch is not right. So I modified the patch. I
forked Paolo's hpet branch and added my latest version patches. Please
confirm the following repository.
https://github.com/TaiseiIto/qemu
It passes my HPET test.
Taisei
差出人: 伊藤 太清
送信日時
On Sat, 20 Jul 2024, Michael S. Tsirkin wrote:
On Thu, Jul 04, 2024 at 10:58:51PM +0200, Bernhard Beschow wrote:
This series first turns vt82c686's "INTR" pin into a named GPIO for better
comprehensibility. It then continues fixing qemu_irq memory leaks in vt82c686
and piix4 by connecting out IR
Found when trying to build coreutils under linux-user as binfmt_misc
interpreter with "open-binary" flag.
I'm unsure whether the version detection in patch 1 makes sense. Please
advise on how to handle situations like this.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2448
Vivian Wang
Sometimes zero is a valid value for getauxval (e.g. AT_EXECFD). Make
sure that we can distinguish between a valid zero value and a not found
entry by setting errno.
Ignore getauxval from sys/auxv.h on glibc < 2.19 because it does not set
errno.
Signed-off-by: Vivian Wang
---
util/getauxval.c |
It's possible for AT_EXECFD to end up with a valid value of 0. Check
errno when using qemu_getauxval instead of return value to handle this
case.
Not handling this case leads to a confusing condition where the
executable ends up as fd 0, i.e. stdin.
Signed-off-by: Vivian Wang
Fixes: 0b959cf5e4cc
On Fri, Jul 19, 2024 at 07:19:37PM +0530, Ani Sinha wrote:
> Date: Fri, 19 Jul 2024 19:19:37 +0530
> From: Ani Sinha
> Subject: [PATCH] hw/x86: add a couple of comments explaining how the kernel
> image is parsed
> X-Mailer: git-send-email 2.42.0
>
> Cosmetic: add comments in x86_load_linux() po
If I use `-serial stdio` on Windows, after QEMU exits, the terminal
could not handle arrow keys and tab any more. Because stdio backend
on Windows sets console mode to virtual terminal input when starts,
but does not restore the old mode when finalize.
This small patch saves the old console mode a
Queued for my 9.1 pull request...
Thanks! Sorry for the delay...
Warner
On Sun, Jul 7, 2024 at 1:11 PM Ajeet Singh wrote:
> Patch 1: Previous patches 1 to 5, which were reviewed and acked, have been
> folded into this patch.Some changes that were suggested,
> such as replacing "psta
The last register of this device is at offset 0x14 occupying 8 bits so
to cover it the mmio region needs to be 0x15 bytes long. Also correct
the name of the field storing this register value to match the
register name.
Signed-off-by: BALATON Zoltan
---
hw/i2c/mpc_i2c.c | 8
1 file chang
From: Davidlohr Bueso
Iterate over the list keeping the output payload size into account,
returning the results from a previous scan media operation. The
scan media operation does not fail prematurely due to device being
out of storage, so this implementation does not deal with the
retry/restart
From: Yi Liu
Signed-off-by: Yi Liu
Message-Id: <20240708032112.796339-1-yi.l@intel.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b7e9ced3e8..8ad64ff76b 100644
--- a
From: Zheyu Ma
Currently, if the function fails during the key_len check, the op_code
does not have a proper value, causing virtio_crypto_free_create_session_req
not to free the memory correctly, leading to a memory leak.
By setting the op_code before performing any checks, we ensure that
virtio
From: Stefano Garzarella
I have recently been working on supporting vhost-user on any POSIX,
so I want to help maintain it.
Cc: Michael S. Tsirkin
Signed-off-by: Stefano Garzarella
Message-Id: <20240704081336.21208-1-sgarz...@redhat.com>
Reviewed-by: Alex Bennée
Reviewed-by: Michael S. Tsirki
From: Davidlohr Bueso
Implement transfer and activate functionality per 3.1 spec for
supporting update metadata (no actual buffers). Transfer times
are arbitrarily set to ten and two seconds for full and part
transfers, respectively.
cxl update-firmware mem0 -F fw.img
cxl update-firmware mem0
A couple of fixes are outstanding, will merge later.
The following changes since commit a87a7c449e532130d4fa8faa391ff7e1f04ed660:
Merge tag 'pull-loongarch-20240719' of https://gitlab.com/gaosong/qemu into
staging (2024-07-19 16:28:28 +1000)
are available in the Git repository at:
https:/
From: Manos Pitsidianakis
When setting the parameters of a PCM stream, we compute the bit flag
with the format and rate values as shift operand to check if they are
set in supported_formats and supported_rates.
If the guest provides a format/rate value which when shifting 1 results
in a value bi
From: Clément Mathieu--Drif
The constant must be unsigned, otherwise the two's complement
overrides the other fields when a PASID is present.
Fixes: 1b2b12376c8a ("intel-iommu: PASID support")
Signed-off-by: Clément Mathieu--Drif
Reviewed-by: Yi Liu
Reviewed-by: Zhenzhong Duan
Reviewed-by: Mi
From: Manos Pitsidianakis
When reading input audio in the virtio-snd input callback,
virtio_snd_pcm_in_cb(), we do not check whether the iov can actually fit
the data buffer. This is because we use the buffer->size field as a
total-so-far accumulator instead of byte-size-left like in TX buffers.
From: Clément Mathieu--Drif
The 'level' field in vtd_iotlb_key is an unsigned integer.
We don't need to store level as an int in vtd_lookup_iotlb.
This is not an issue by itself, but using unsigned here seems cleaner.
Signed-off-by: Clément Mathieu--Drif
Reviewed-by: Yi Liu
Message-Id: <20240
From: Clément Mathieu--Drif
Per the below code, it can overflow as am can be larger than 8 according
to the CH 6.5.2.3 IOTLB Invalidate. Use uint64_t to avoid overflows.
Fixes: b5a280c00840 ("intel-iommu: add IOTLB using hash table")
Signed-off-by: Clément Mathieu--Drif
Reviewed-by: Minwoo Im
From: Akihiko Odaki
Signed-off-by: Akihiko Odaki
Message-Id: <20240715-sriov-v5-8-3f5539093...@daynix.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
MAINTAINERS | 1 +
docs/system/index.rst | 1 +
docs/system/sriov.rst | 36 +
From: Shiju Jose
CXL spec 3.1 section 8.2.9.6 describes optional device specific features.
CXL devices supports features with changeable attributes.
Get Supported Features retrieves the list of supported device specific
features. The settings of a feature can be retrieved using Get Feature and
op
From: Hanna Czenczek
Requiring `vhost_started` to be true for resetting vhost devices in
`virtio_reset()` seems like the wrong condition: Most importantly, the
preceding `virtio_set_status(vdev, 0)` call will (for vhost devices) end
up in `vhost_dev_stop()` (through vhost devices' `.set_status`
i
From: Sunil V L
Currently, PCI link devices (PNP0C0F) are always created within the
scope of the PCI root bridge. However, RISC-V needs these link devices
to be created outside to ensure the probing order in the OS. This
matches the example given in the ACPI specification [1] as well. Hence,
crea
From: Igor Mammedov
Currently QEMU describes initial[1] RAM* in SMBIOS as a series of
virtual DIMMs (capped at 16Gb max) using type 17 structure entries.
Which is fine for the most cases. However when starting guest
with terabytes of RAM this leads to too many memory device
structures, which ev
From: Clément Mathieu--Drif
These 2 macros are for high 64-bit of the FRCD registers.
Declarations have to be moved accordingly.
Signed-off-by: Clément Mathieu--Drif
Reviewed-by: Minwoo Im
Reviewed-by: Yi Liu
Message-Id: <20240709142557.317271-3-clement.mathieu--d...@eviden.com>
Reviewed-by:
From: Jonathan Cameron
Similar protection to that provided for -numa memdev=x
to make sure that memory used to back a type3 device is not also mapped
as normal RAM, or for multiple type3 devices.
This is an easy footgun to remove and seems multiple people have
run into it.
Signed-off-by: Jonath
From: Eric Auger
We currently miss the removal of the endpoint in case of detach.
Signed-off-by: Eric Auger
Message-Id: <20240716094619.1713905-5-eric.au...@redhat.com>
Tested-by: Cédric Le Goater
Reviewed-by: Cédric Le Goater
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
From: Sunil V L
As per the step 5 in the process documented in bios-tables-test.c,
generate the expected ACPI AML data files for RISC-V using the
rebuild-expected-aml.sh script and update the
bios-tables-test-allowed-diff.h.
These are all new files being added for the first time. Hence, iASL dif
From: Zhao Liu
QEMU crashes (Segmentation fault) when getting cxl-fmw property via
qmp:
(QEMU) qom-get path=machine property=cxl-fmw
This issue is caused by accessing wrong callback (opaque) type in
machine_get_cfmw().
cxl_machine_init() sets the callback as `CXLState *` type but
machine_get_c
From: Akihiko Odaki
SR-IOV requires PCI Express.
Signed-off-by: Akihiko Odaki
Message-Id: <20240715-sriov-v5-4-3f5539093...@daynix.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/pci/pcie_sriov.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/pci/pc
From: Sunil V L
Add basic ACPI table test case for RISC-V.
Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
Reviewed-by: Igor Mammedov
Message-Id: <20240716144306.2432257-9-suni...@ventanamicro.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
tests/qtest/bio
From: Huai-Cheng Kuo
SPDM enables authentication, attestation and key exchange to assist in
providing infrastructure security enablement. It's a standard published
by the DMTF [1].
SPDM supports multiple transports, including PCIe DOE and MCTP.
This patch adds support to QEMU to connect to an ex
From: Eric Auger
We are currently missing the deallocation of the [host_]resv_regions
in case of hot unplug. Also to make things more simple let's rule
out the case where multiple HostIOMMUDevices would be aliased and
attached to the same IOMMUDevice. This allows to remove the handling
of conflic
From: Sunil V L
After PCI link devices are moved out of the scope of PCI root complex,
the DSDT files of machines which use GPEX, will change. So, update the
expected AML files with these changes for these machines.
Mainly, there are 2 changes.
1) Since the link devices are created now directly
From: Eric Auger
Trace when VFIO gets notified about the deletion of an IOMMU MR.
Also trace the name of the region in the add_iommu trace message.
Signed-off-by: Eric Auger
Message-Id: <20240716094619.1713905-6-eric.au...@redhat.com>
Tested-by: Cédric Le Goater
Reviewed-by: Cédric Le Goater
From: Jonah Palmer
Add VIRTIO_F_IN_ORDER feature support in virtqueue_split_pop and
virtqueue_packed_pop.
VirtQueueElements popped from the available/descritpor ring are added to
the VirtQueue's used_elems array in-order and in the same fashion as
they would be added the used and descriptor ring
From: Jonah Palmer
Add VIRTIO_F_IN_ORDER feature support for the virtqueue_fill operation.
The goal of the virtqueue_ordered_fill operation when the
VIRTIO_F_IN_ORDER feature has been negotiated is to search for this
now-used element, set its length, and mark the element as filled in
the VirtQue
From: Eric Auger
This reverts commit 1b889d6e39c32d709f1114699a014b381bcf1cb1.
There are different problems with that tentative fix:
- Some resources are left dangling (resv_regions,
host_resv_ranges) and memory subregions are left attached to
the root MR although freed as embedded in the sde
From: Salil Mehta
CPUs Control device(\\_SB.PCI0) register interface for the x86 arch is IO port
based and existing CPUs AML code assumes _CRS objects would evaluate to a system
resource which describes IO Port address. But on ARM arch CPUs control
device(\\_SB.PRES) register interface is memory-
From: Salil Mehta
CPU ctrl-dev MMIO region length could be used in ACPI GED and various other
architecture specific places. Move ACPI_CPU_HOTPLUG_REG_LEN macro to more
appropriate common header file.
Signed-off-by: Salil Mehta
Reviewed-by: Alex Bennée
Reviewed-by: Jonathan Cameron
Reviewed-by
From: Akihiko Odaki
Allow user to attach SR-IOV VF to a virtio-pci PF.
Signed-off-by: Akihiko Odaki
Message-Id: <20240715-sriov-v5-6-3f5539093...@daynix.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
include/hw/virtio/virtio-pci.h | 1 +
hw/virtio/virtio-pci.c
From: Jonah Palmer
Extend the virtio device property definitions to include the
VIRTIO_F_IN_ORDER feature.
The default state of this feature is disabled, allowing it to be
explicitly enabled where it's supported.
Acked-by: Eugenio Pérez
Signed-off-by: Jonah Palmer
Message-Id: <20240710125522.
From: Alistair Francis
Add all of the defined protocols/features from the PCIe-SIG r6.0
"Table 6-32 PCI-SIG defined Data Object Types (Vendor ID = 0001h)"
table.
Signed-off-by: Alistair Francis
Reviewed-by: Jonathan Cameron
Reviewed-by: Wilfred Mallawa
Message-Id: <20240703092027.644758-2-ali
From: Jonah Palmer
Add VIRTIO_F_IN_ORDER feature support for the virtqueue_flush operation.
The goal of the virtqueue_ordered_flush operation when the
VIRTIO_F_IN_ORDER feature has been negotiated is to write elements to
the used/descriptor ring in-order and then update used_idx.
The function i
From: Stefano Garzarella
Coverity reported:
>>> CID 1549454: Integer handling issues (OVERFLOW_BEFORE_WIDEN)
>>> Potentially overflowing expression
"le32_to_cpu(desc->num_sectors) << 9" with type "uint32_t"
(32 bits, unsigned) is evaluated using 32-bit arithmeti
From: Fan Ni
The whole mailbox output payload space is already zeroed after copying
out the input payload, which happens before processing the specific mailbox
command:
https://elixir.bootlin.com/qemu/v8.2.1/source/hw/cxl/cxl-device-utils.c#L204
Signed-off-by: Fan Ni
Link: https://lore.kernel.o
From: Eric Auger
Now we have switched to PCIIOMMUOps to convey host IOMMU information,
the host reserved regions are transmitted when the PCIe topology is
built. This happens way before the virtio-iommu driver calls the probe
request. So let's remove the probe_done flag that allowed to check
the
From: Hyeonggon Yoo <42.hye...@gmail.com>
The spec states that reads/writes should have no effect and a part of
commands should be ignored when the media is disabled, not when the
sanitize command is running.
Introduce cxl_dev_media_disabled() to check if the media is disabled and
replace sanitiz
From: Sunil V L
As per the requirement ACPI_080 in the RISC-V Boot and Runtime Services
(BRS) specification [1], PLIC and APLIC should be in namespace as well.
So, add them using the defined HID.
[1] -
https://github.com/riscv-non-isa/riscv-brs/releases/download/v0.0.2/riscv-brs-spec.pdf
From: Sunil V L
The expected ACPI AML files are moved now under ${arch}/{machine} path.
Hence, there is no need to search in old path which didn't have ${arch}.
Remove the code which searches for the expected AML files under old path
as well.
Suggested-by: Igor Mammedov
Signed-off-by: Sunil V L
> -Original Message-
> From: qemu-devel-bounces+yaoxt.fnst=fujitsu@nongnu.org
> On Behalf Of Vivian
> Wang
> Sent: Sunday, July 21, 2024 5:08 PM
> To: qemu-devel@nongnu.org
> Cc: Vivian Wang ; Richard Henderson ;
> Laurent Vivier
> Subject: [PATCH 1/2] util/getauxval: Ensure settin
From: Akihiko Odaki
A SR-IOV VF cannot have a ROM BAR.
Co-developed-by: Yui Washizu
Signed-off-by: Akihiko Odaki
Message-Id: <20240715-sriov-v5-1-3f5539093...@daynix.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/pci/pci.c | 8
1 file changed, 8 inser
From: Akihiko Odaki
pci_config_get_bar_addr() had a division by vf_stride. vf_stride needs
to be non-zero when there are multiple VFs, but the specification does
not prohibit to make it zero when there is only one VF.
Do not perform the division for the first VF to avoid division by zero.
Signe
From: Akihiko Odaki
A user can create a SR-IOV device by specifying the PF with the
sriov-pf property of the VFs. The VFs must be added before the PF.
A user-creatable VF must have PCIDeviceClass::sriov_vf_user_creatable
set. Such a VF cannot refer to the PF because it is created before the
PF.
From: Davidlohr Bueso
Use simple heuristics to determine the cost of scanning any given
chunk, assuming cost is equal across the whole device, without
differentiating between volatile or persistent partitions. This
is aligned to the fact that these constraints are not enforced
in respective poiso
From: Jonah Palmer
Add support for the VIRTIO_F_IN_ORDER feature across a variety of vhost
devices.
The inclusion of VIRTIO_F_IN_ORDER in the feature bits arrays for these
devices ensures that the backend is capable of offering and providing
support for this feature, and that it can be disabled
From: Akihiko Odaki
A device cannot be a SR-IOV PF and a VF at the same time.
Signed-off-by: Akihiko Odaki
Message-Id: <20240715-sriov-v5-3-3f5539093...@daynix.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/pci/pcie_sriov.c | 5 +
1 file changed, 5 insertio
From: Shiju Jose
CXL spec 3.1 section 8.2.9.9.11.1 describes the device patrol scrub control
feature. The device patrol scrub proactively locates and makes corrections
to errors in regular cycle. The patrol scrub control allows the request to
configure patrol scrub input configurations.
The patr
From: Salil Mehta
ACPI GED (as described in the ACPI 6.4 spec) uses an interrupt listed in the
_CRS object of GED to intimate OSPM about an event. Later then demultiplexes the
notified event by evaluating ACPI _EVT method to know the type of event. Use
ACPI GED to also notify the guest kernel abo
From: Salil Mehta
Add common function to help unregister the GDB register space. This shall be
done in context to the CPU unrealization.
Note: These are common functions exported to arch specific code. For example,
for ARM this code is being referred in associated arch specific patch-set:
Link:
From: Salil Mehta
Virtual CPU Hot-unplug leads to unrealization of a CPU object. This also
involves destruction of the CPU AddressSpace. Add common function to help
destroy the CPU AddressSpace.
Signed-off-by: Salil Mehta
Tested-by: Vishnu Pajjuri
Reviewed-by: Gavin Shan
Tested-by: Xianglai L
From: Shiju Jose
CXL spec 3.1 section 8.2.9.9.11.2 describes the DDR5 Error Check Scrub (ECS)
control feature.
The Error Check Scrub (ECS) is a feature defined in JEDEC DDR5 SDRAM
Specification (JESD79-5) and allows the DRAM to internally read, correct
single-bit errors, and write back corrected
From: Sunil V L
The requirement ACPI_060 in the RISC-V BRS specification [1], requires
NS16550 compatible UART to have the HID RSCV0003. So, update the HID for
the UART.
[1] -
https://github.com/riscv-non-isa/riscv-brs/releases/download/v0.0.2/riscv-brs-spec.pdf
(Chapter 6)
Signed-off-
From: Akihiko Odaki
A virtio-net device can be added as a SR-IOV VF to another virtio-pci
device that will be the PF.
Signed-off-by: Akihiko Odaki
Message-Id: <20240715-sriov-v5-7-3f5539093...@daynix.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/virtio/virtio-
From: Salil Mehta
OSPM evaluates _EVT method to map the event. The CPU hotplug event eventually
results in start of the CPU scan. Scan figures out the CPU and the kind of
event(plug/unplug) and notifies it back to the guest. Update the GED AML _EVT
method with the call to method \\_SB.CPUS.CSCN (
From: Eric Auger
Add a trace point on virtio_iommu_detach_endpoint_from_domain().
Signed-off-by: Eric Auger
Message-Id: <20240716094619.1713905-7-eric.au...@redhat.com>
Tested-by: Cédric Le Goater
Reviewed-by: Cédric Le Goater
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
From: Sunil V L
so that CI tests don't fail when those ACPI tables are updated in the
next patch. This is as per the documentation in bios-tables-tests.c.
Signed-off-by: Sunil V L
Reviewed-by: Igor Mammedov
Message-Id: <20240716144306.2432257-4-suni...@ventanamicro.com>
Reviewed-by: Michael S.
From: Wilfred Mallawa
Setup Data Object Exchange (DOE) as an extended capability for the NVME
controller and connect SPDM to it (CMA) to it.
Signed-off-by: Wilfred Mallawa
Signed-off-by: Alistair Francis
Reviewed-by: Jonathan Cameron
Acked-by: Klaus Jensen
Message-Id: <20240703092027.644758-
From: Sunil V L
As per process documented (steps 1-3) in bios-tables-test.c, add empty
AML data files for RISC-V ACPI tables and add the entries in
bios-tables-test-allowed-diff.h.
Signed-off-by: Sunil V L
Acked-by: Alistair Francis
Reviewed-by: Igor Mammedov
Message-Id: <20240716144306.24322
From: Hyeonggon Yoo <42.hye...@gmail.com>
Per CXL r3.1 Section 8.2.9.9.5.1: Sanitize (Opcode 4400h), the
sanitize command should delete all event logs. Introduce
cxl_discard_all_event_logs() and call
this in __do_sanitization().
Signed-off-by: Hyeonggon Yoo <42.hye...@gmail.com>
Reviewed-by: Davi
From: Jonah Palmer
Add the boolean 'in_order_filled' member to the VirtQueueElement structure.
The use of this boolean will signify whether the element has been processed
and is ready to be flushed (so long as the element is in-order). This
boolean is used to support the VIRTIO_F_IN_ORDER feature
From: Gregory Price
Preparation for allowing devices to define their own CCI commands
Signed-off-by: Gregory Price
Link:
https://lore.kernel.org/r/20230906001517.324380-2-gregory.pr...@memverge.com
Signed-off-by: Jonathan Cameron
Message-Id: <20240705123039.963781-2-jonathan.came...@huawei.co
From: Salil Mehta
KVM vCPU creation is done once during the vCPU realization when Qemu vCPU thread
is spawned. This is common to all the architectures as of now.
Hot-unplug of vCPU results in destruction of the vCPU object in QOM but the
corresponding KVM vCPU object in the Host KVM is not destr
Currently, some components still open-coding the range overlap check.
Sometimes this check may be fail because some patterns are missed.
To avoid the above problems and improve the readability of the code,
it is better to use the ranges_overlap() to do this check.
Yao Xingtao (13):
range: Make
Just like range_overlaps_range(), use the returned bool value
to check whether 2 given ranges overlap.
Signed-off-by: Yao Xingtao
---
include/qemu/range.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/qemu/range.h b/include/qemu/range.h
index 4ce694a39831..d446a
use ranges_overlap() instead of open-coding the overlap check to improve
the readability of the code.
Signed-off-by: Yao Xingtao
---
hw/core/loader.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/core/loader.c b/hw/core/loader.c
index 31593a117171..dac0df561b16 100644
use ranges_overlap() instead of open-coding the overlap check to improve
the readability of the code.
Signed-off-by: Yao Xingtao
---
hw/arm/boot.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index d480a7da02cf..a004a90e87be 100644
--- a/
use ranges_overlap() instead of open-coding the overlap check to improve
the readability of the code.
Signed-off-by: Yao Xingtao
---
hw/cxl/cxl-mailbox-utils.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
inde
use ranges_overlap() instead of open-coding the overlap check to improve
the readability of the code.
Signed-off-by: Yao Xingtao
---
tests/qtest/fuzz/generic_fuzz.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tests/qtest/fuzz/generic_fuzz.c b/tests/qtest/fuzz/generic_fu
use ranges_overlap() instead of open-coding the overlap check to improve
the readability of the code.
Signed-off-by: Yao Xingtao
---
target/sparc/ldst_helper.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index 2
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