According to RISC-V Debug specification, the optional textra32 and textra64 trigger CSRs can be used to configure additional matching conditions for the triggers.
This series support to write MHVALUE and MHSELECT fields into textra32 and textra64 trigger CSRs. Besides, the additional matching condition between textra.MHVALUE and mcontext CSR is also implemented. Changes from v2: - Remove redundant log Changes from v1: - Log that mhselect only supports 0 or 4 for now - Simplify writing of tdata3 Alvin Chang (2): target/riscv: Preliminary textra trigger CSR writting support target/riscv: Add textra matching condition for the triggers target/riscv/cpu_bits.h | 10 +++ target/riscv/debug.c | 132 +++++++++++++++++++++++++++++++++++++--- target/riscv/debug.h | 3 + 3 files changed, 138 insertions(+), 7 deletions(-) -- 2.34.1
