On 2024/7/10 11:28 AM, Richard Henderson wrote:
The current pairing of tlb_vaddr_to_host with extra is either
inefficient (user-only, with page_check_range) or incorrect
(system, with probe_pages).
For proper non-fault behaviour, use probe_access_flags with
its nonfault parameter set to true.
S
Akihiko Odaki writes:
> Commit 23ef50ae2d0c (".gitlab-ci.d/buildtest.yml: Use
> -fno-sanitize=function in the clang-system job") adds
> -fno-sanitize=function for the CI but doesn't add the flag in the
> other context. Move it to meson.build.
>
> Signed-off-by: Akihiko Odaki
> ---
> meson.build
On 2024/07/15 16:10, Alex Bennée wrote:
Akihiko Odaki writes:
Commit 23ef50ae2d0c (".gitlab-ci.d/buildtest.yml: Use
-fno-sanitize=function in the clang-system job") adds
-fno-sanitize=function for the CI but doesn't add the flag in the
other context. Move it to meson.build.
Signed-off-by: Aki
On 7/8/24 10:06 AM, Andrey Drobyshev wrote:
> On 6/24/24 10:43 AM, Andrey Drobyshev wrote:
>> On 6/17/24 9:39 AM, Andrey Drobyshev wrote:
>>> On 6/10/24 11:53 AM, Andrey Drobyshev wrote:
On 6/3/24 12:19 PM, Andrey Drobyshev wrote:
> On 5/13/24 9:31 AM, Andrey Drobyshev wrote:
>> v1:
>
From: Vincent Fu
The number of PIDs is in the upper 16 bits of cdw10. So we need to
right-shift by 16 bits instead of only a single bit.
Fixes: 73064edfb864 ("hw/nvme: flexible data placement emulation")
Cc: qemu-sta...@nongnu.org
Signed-off-by: Vincent Fu
Reviewed-by: Klaus Jensen
Signed-off-
The following patches are queued for QEMU stable v8.2.6:
https://gitlab.com/qemu-project/qemu/-/commits/staging-8.2
Patch freeze is 2024-07-14 (frozen), and the release is planned for 2024-07-16:
https://wiki.qemu.org/Planning/8.2
I expect this to be the last release in stable-8.2.x series.
From: Maxim Mikityanskiy
qemu_chr_open_fd() sets stdout into non-blocking mode. Restore the old
fd flags on exit to avoid breaking unsuspecting applications that run on
the same terminal after qemu and don't expect to get EAGAIN.
While at at, also ensure term_exit is called once (at the moment i
From: Stefano Garzarella
Commit d152cdd6f6 ("virtio: use virtio accessor to access packed event")
switched using of address_space_read_cached() to virito_lduw_phys_cached()
to access packed descriptor event.
When we used address_space_read_cached(), we needed to call
virtio_tswap16s() to handle
From: Cindy Lu
In function kvm_virtio_pci_vector_use_one(), the function will only use
the irqfd/vector for itself. Therefore, in the undo label, the failing
process is incorrect.
To fix this, we can just remove this label.
Fixes: f9a09ca3ea ("vhost: add support for configure interrupt")
Cc: qem
From: Markus Armbruster
When a command's arguments are specified as an explicit type T,
generated documentation points to the members of T.
Example:
##
# @announce-self:
#
# Trigger generation of broadcast RARP frames to update network
[...]
##
{ 'command': 'announce
For qemu_open_old(), osdep.h said:
> Don't introduce new usage of this function, prefer the following
> qemu_open/qemu_create that take an "Error **errp".
So replace qemu_open_old() with qemu_open().
Cc: Yi Liu
Cc: Eric Auger
Cc: Zhenzhong Duan
Signed-off-by: Zhao Liu
---
backends/iommufd.c
For qemu_open_old(), osdep.h said:
> Don't introduce new usage of this function, prefer the following
> qemu_open/qemu_create that take an "Error **errp".
So replace qemu_open_old() with qemu_open().
Signed-off-by: Zhao Liu
---
hw/usb/host-libusb.c | 3 +--
1 file changed, 1 insertion(+), 2 de
Hi list,
After Daniel's renaming (448058aa99aa "util: rename qemu_open() to
qemu_open_old()"), I find some qemu_open_old() can be directly replaced
by the new qemu_open().
This series considers the case where @errp exists, for which @errp can
be passed directly to qemu_open().
There would be mor
For qemu_open_old(), osdep.h said:
> Don't introduce new usage of this function, prefer the following
> qemu_open/qemu_create that take an "Error **errp".
So replace qemu_open_old() with qemu_open().
Signed-off-by: Zhao Liu
---
hw/usb/u2f-passthru.c | 4 +---
1 file changed, 1 insertion(+), 3
For qemu_open_old(), osdep.h said:
> Don't introduce new usage of this function, prefer the following
> qemu_open/qemu_create that take an "Error **errp".
So replace qemu_open_old() with qemu_open(). And considering the SGX
enablement description is useful, convert it into a error message hint.
For qemu_open_old(), osdep.h said:
> Don't introduce new usage of this function, prefer the following
> qemu_open/qemu_create that take an "Error **errp".
So replace qemu_open_old() with qemu_open().
Cc: David Hildenbrand
Cc: Igor Mammedov
Signed-off-by: Zhao Liu
---
backends/hostmem-epc.c |
For qemu_open_old(), osdep.h said:
> Don't introduce new usage of this function, prefer the following
> qemu_open/qemu_create that take an "Error **errp".
So replace qemu_open_old() with qemu_open(). And considering
rng_random_opened() will lose its obvious error handling case after
removing erro
For qemu_open_old(), osdep.h said:
> Don't introduce new usage of this function, prefer the following
> qemu_open/qemu_create that take an "Error **errp".
So replace qemu_open_old() with qemu_open().
Cc: Alex Williamson
Cc: "Cédric Le Goater"
Signed-off-by: Zhao Liu
---
hw/vfio/container.c |
Hello Pierrick,
On 7/12/24 19:23, Pierrick Bouvier wrote:
Hello Simon,
On 7/12/24 00:53, Simon Hamelin wrote:
On 7/11/24 12:03, Alex Bennée wrote:
+static void exit_emulation(int return_code)
+{
+ exit(return_code);
+}
+
+static void exit_icount_reached(unsigned int cpu_index, void *udat
On Thu, 11 Jul 2024 at 21:12, Peter Xu wrote:
> I apologize if I suggested WITH_QEMU_LOCK_GUARD when we talked.. I don't
> remember which one I suggested, but in this case IIUC it'll be much easier
> to review if you use the other sister function QEMU_LOCK_GUARD()
> instead.. That should make the
This new plugin allows to stop emulation using conditions on the
emulation state. By setting this plugin arguments, it is possible
to set an instruction count limit and/or trigger address(es) to stop at.
The code returned at emulation exit can be customized.
This plugin demonstrates how someone co
On 7/15/24 10:09, Simon Hamelin wrote:
Hello Pierrick,
On 7/12/24 19:23, Pierrick Bouvier wrote:
Hello Simon,
On 7/12/24 00:53, Simon Hamelin wrote:
On 7/11/24 12:03, Alex Bennée wrote:
+static void exit_emulation(int return_code)
+{
+ exit(return_code);
+}
+
+static void exit_icount
> -Original Message-
> From: Michael S. Tsirkin
> Sent: Friday, July 12, 2024 6:49 AM
> To: Wang, Yichen
> Cc: Paolo Bonzini ; Marc-André Lureau
> ; Daniel P. Berrangé ;
> Thomas Huth ; Philippe Mathieu-Daudé
> ; Peter Xu ; Fabiano Rosas
> ; Eric Blake ; Markus Armbruster
> ; Cornelia Huc
On Thu, Jul 4, 2024 at 4:48 PM Laurent Vivier wrote:
> Add the description of "-netdev stream" and "-netdev dgram" in the QEMU
> manpage.
>
> Add some examples on how to use them, including a way to use
> "-netdev stream" and "passt" in place of "-netdev user".
> ("passt" is a non privileged tran
On 7/14/24 10:29 PM, LIU Zhiwei wrote:
On 2024/7/12 17:52, Daniel Henrique Barboza wrote:
On 7/9/24 11:24 PM, LIU Zhiwei wrote:
From: TANG Tiancheng
To regularly test booting Linux with rv32 on QEMU RV64,
we have added a test to boot_linux_console.py to retrieve
cpuinfo and verify if it
In the next patch, combine_tlb() will be added which combines 2 TLB
entries into one for nested translations, which chooses the granule
and level from the smallest entry.
This means that with nested translation, an entry can be cached with
the granule of stage-2 and not stage-1.
However, currentl
Soon, smmuv3_do_translate() will be used to translate the CD and the
TTBx, instead of re-writting the same logic to convert the returned
cached entry to an address, add a new macro CACHED_ENTRY_TO_ADDR.
Reviewed-by: Eric Auger
Signed-off-by: Mostafa Saleh
---
hw/arm/smmuv3.c | 3 +-
ASID and VMID used to be uint16_t in the translation config, however,
in other contexts they can be int as -1 in case of TLB invalidation,
to represent all (don’t care).
When stage-2 was added asid was set to -1 in stage-2 and vmid to -1
in stage-1 configs. However, that meant they were set as (655
smmuv3_translate() does everything from STE/CD parsing to TLB lookup
and PTW.
Soon, when nesting is supported, stage-1 data (tt, CD) needs to be
translated using stage-2.
Split smmuv3_translate() to 3 functions:
- smmu_translate(): in smmu-common.c, which does the TLB lookup, PTW,
TLB insertio
Previously, to check if faults are enabled, it was sufficient to check
the current stage of translation and check the corresponding
record_faults flag.
However, with nesting, it is possible for stage-1 (nested) translation
to trigger a stage-2 fault, so we check SMMUPTWEventInfo as it would
have t
The BookE decrementer stops at 0, meaning that it won't decremented
towards "negative" values.
However, the current logic is inverted: decr is updated solely when
the resulting value would be negative.
Signed-off-by: Clément Chigot
Fixed: 8e0a5ac87800 ("hw/ppc: Avoid decrementer rounding errors")
According to the SMMU architecture specification (ARM IHI 0070 F.b),
in “3.4 Address sizes”
The address output from the translation causes a stage 1 Address Size
fault if it exceeds the range of the effective IPA size for the given CD.
However, this check was missing.
There is already a s
This patch adds support for nested (combined) TLB entries.
The main function combine_tlb() is not used here but in the next
patches, but to simplify the patches it is introduced first.
Main changes:
1) New field added in the SMMUTLBEntry struct: parent_perm, for
nested TLB, holds the stage-2 pe
For the following events (ARM IHI 0070 F.b - 7.3 Event records):
- F_TRANSLATION
- F_ACCESS
- F_PERMISSION
- F_ADDR_SIZE
If fault occurs at stage 2, S2 == 1 and:
- If translating an IPA for a transaction (whether by input to
stage 2-only configuration, or after successful stage 1 translation
Currently, translation stage is represented as an int, where 1 is stage-1 and
2 is stage-2, when nested is added, 3 would be confusing to represent nesting,
so we use an enum instead.
While keeping the same values, this is useful for:
- Doing tricks with bit masks, where BIT(0) is stage-1 and BIT
Currently, QEMU supports emulating either stage-1 or stage-2 SMMUs
but not nested instances.
This patch series adds support for nested translation in SMMUv3,
this is controlled by property “arm-smmuv3.stage=nested”, and
advertised to guests as (IDR0.S1P == 1 && IDR0.S2P == 2)
Main changes(architec
When nested translation is requested, do the following:
- Translate stage-1 table address IPA into PA through stage-2.
- Translate stage-1 table walk output (IPA) through stage-2.
- Create a single TLB entry from stage-1 and stage-2 translations
using logic introduced before.
smmu_ptw() has a ne
According to ARM SMMU architecture specification (ARM IHI 0070 F.b),
In "5.2 Stream Table Entry":
[51:6] S1ContextPtr
If Config[1] == 1 (stage 2 enabled), this pointer is an IPA translated by
stage 2 and the programmed value must be within the range of the IAS.
In "5.4.1 CD notes":
The transla
Some commands need rework for nesting, as they used to assume S1
and S2 are mutually exclusive:
- CMD_TLBI_NH_ASID: Consider VMID if stage-2 is supported
- CMD_TLBI_NH_ALL: Consider VMID if stage-2 is supported, otherwise
invalidate everything, this required a new vmid invalidation
function fo
With nesting, we would need to invalidate IPAs without
over-invalidating stage-1 IOVAs. This can be done by
distinguishing IPAs in the TLBs by having ASID=-1.
To achieve that, rework the invalidation for IPAs to have a
separate function, while for IOVA invalidation ASID=-1 means
invalidate for all
SMMUv3 OAS is currently hardcoded in the code to 44 bits, for nested
configurations that can be a problem, as stage-2 might be shared with
the CPU which might have different PARANGE, and according to SMMU manual
ARM IHI 0070F.b:
6.3.6 SMMU_IDR5, OAS must match the system physical address size.
Everything is in place, consolidate parsing of STE cfg and setting
translation stage.
Advertise nesting if stage requested is "nested".
Reviewed-by: Jean-Philippe Brucker
Reviewed-by: Eric Auger
Signed-off-by: Mostafa Saleh
---
hw/arm/smmuv3.c | 35 ++-
1 file
Soon, Instead of doing TLB invalidation by ASID only, VMID will be
also required.
Add smmu_iotlb_inv_asid_vmid() which invalidates by both ASID and VMID.
However, at the moment this function is only used in SMMU_CMD_TLBI_NH_ASID
which is a stage-1 command, so passing VMID = -1 keeps the original
b
IOMMUTLBEvent only understands IOVA, for stage-1 or stage-2
SMMU instances we consider the input address as the IOVA, but when
nesting is used, we can't mix stage-1 and stage-2 addresses, so for
nesting only stage-1 is considered the IOVA and would be notified.
Signed-off-by: Mostafa Saleh
---
h
The SMMUv3 spec (ARM IHI 0070 F.b - 7.3 Event records) defines the
class of events faults as:
CLASS: The class of the operation that caused the fault:
- 0b00: CD, CD fetch.
- 0b01: TTD, Stage 1 translation table fetch.
- 0b10: IN, Input address
However, this value was not set and left as 0 which
Hi Zhao,
> From: Zhao Liu
> Sent: Monday, July 15, 2024 7:11 AM
> To: Salil Mehta
>
> Hi Salil,
>
> I ran the unit tests again on x86 platform, and everything looks good.
>
> Please feel free to keep my tested-by tag.
Many thanks for confirming this. Appreciate this.
Best Wishes
S
Hi Michael, Yi and Jason
Thanks for your feedback on the previous versions.
If you agree with the series, do you think we can move forward?
Thanks!
>cmd
On 09/07/2024 16:26, CLEMENT MATHIEU--DRIF wrote:
> From: Clément Mathieu--Drif
>
> Various fixes for VT-d
>
> This series contains fixes tha
On Mon, Jul 15, 2024 at 08:48:52AM +, CLEMENT MATHIEU--DRIF wrote:
> Hi Michael, Yi and Jason
>
> Thanks for your feedback on the previous versions.
> If you agree with the series, do you think we can move forward?
Yes, tagged, thanks!
> Thanks!
> >cmd
>
> On 09/07/2024 16:26, CLEMENT MAT
On 7/13/24 3:57 PM, Conor Dooley wrote:
On Sat, Jul 13, 2024 at 02:43:25PM -0300, Daniel Henrique Barboza wrote:
Commit b1f1e9dcfa renamed 'riscv,delegate' to 'riscv,delegation' since
it is the correct name as per dt-bindings, and the absence of the
correct name will result in validation fail
Commit b1f1e9dcfa renamed 'riscv,delegate' to 'riscv,delegation' since
it is the correct name as per dt-bindings, and the absence of the
correct name will result in validation fails when dumping the dtb and
using dt-validate.
But this change has a side-effect: every other firmware available that
i
The following patches are queued for QEMU stable v9.0.2:
https://gitlab.com/qemu-project/qemu/-/commits/staging-9.0
Patch freeze is 2024-07-14 (frozen), and the release is planned for 2024-07-16:
https://wiki.qemu.org/Planning/9.0
Please respond here or CC qemu-sta...@nongnu.org on any addi
From: Maxim Mikityanskiy
qemu_chr_open_fd() sets stdout into non-blocking mode. Restore the old
fd flags on exit to avoid breaking unsuspecting applications that run on
the same terminal after qemu and don't expect to get EAGAIN.
While at at, also ensure term_exit is called once (at the moment i
From: Cindy Lu
In function kvm_virtio_pci_vector_use_one(), the function will only use
the irqfd/vector for itself. Therefore, in the undo label, the failing
process is incorrect.
To fix this, we can just remove this label.
Fixes: f9a09ca3ea ("vhost: add support for configure interrupt")
Cc: qem
From: Markus Armbruster
When a command's arguments are specified as an explicit type T,
generated documentation points to the members of T.
Example:
##
# @announce-self:
#
# Trigger generation of broadcast RARP frames to update network
[...]
##
{ 'command': 'announce
From: Vincent Fu
The number of PIDs is in the upper 16 bits of cdw10. So we need to
right-shift by 16 bits instead of only a single bit.
Fixes: 73064edfb864 ("hw/nvme: flexible data placement emulation")
Cc: qemu-sta...@nongnu.org
Signed-off-by: Vincent Fu
Reviewed-by: Klaus Jensen
Signed-off-
From: Stefano Garzarella
Commit d152cdd6f6 ("virtio: use virtio accessor to access packed event")
switched using of address_space_read_cached() to virito_lduw_phys_cached()
to access packed descriptor event.
When we used address_space_read_cached(), we needed to call
virtio_tswap16s() to handle
Richard Henderson writes:
> From: Daniyal Khan
>
> We made a copy above because the fp exception flags
> are not propagated back to the FPST register, but
> then failed to use the copy.
>
> Cc: qemu-sta...@nongnu.org
> Fixes: 558e956c719 ("target/arm: Implement FMOPA, FMOPS (non-widening)")
> Si
As the comment in qapi/error, dereferencing @errp requires
ERRP_GUARD():
* = Why, when and how to use ERRP_GUARD() =
*
* Without ERRP_GUARD(), use of the @errp parameter is restricted:
* - It must not be dereferenced, because it may be null.
...
* ERRP_GUARD() lifts these restrictions.
*
* To use
As the comment in qapi/error, dereferencing @errp requires
ERRP_GUARD():
* = Why, when and how to use ERRP_GUARD() =
*
* Without ERRP_GUARD(), use of the @errp parameter is restricted:
* - It must not be dereferenced, because it may be null.
...
* ERRP_GUARD() lifts these restrictions.
*
* To use
As the comment in qapi/error, dereferencing @errp requires
ERRP_GUARD():
* = Why, when and how to use ERRP_GUARD() =
*
* Without ERRP_GUARD(), use of the @errp parameter is restricted:
* - It must not be dereferenced, because it may be null.
...
* ERRP_GUARD() lifts these restrictions.
*
* To use
On 15/7/24 10:21, Zhao Liu wrote:
For qemu_open_old(), osdep.h said:
Don't introduce new usage of this function, prefer the following
qemu_open/qemu_create that take an "Error **errp".
So replace qemu_open_old() with qemu_open().
Signed-off-by: Zhao Liu
---
hw/usb/host-libusb.c | 3 +--
On 15/7/24 10:21, Zhao Liu wrote:
For qemu_open_old(), osdep.h said:
Don't introduce new usage of this function, prefer the following
qemu_open/qemu_create that take an "Error **errp".
So replace qemu_open_old() with qemu_open().
Cc: Yi Liu
Cc: Eric Auger
Cc: Zhenzhong Duan
Signed-off-by:
On 15/7/24 10:21, Zhao Liu wrote:
For qemu_open_old(), osdep.h said:
Don't introduce new usage of this function, prefer the following
qemu_open/qemu_create that take an "Error **errp".
So replace qemu_open_old() with qemu_open().
Signed-off-by: Zhao Liu
---
hw/usb/u2f-passthru.c | 4 +---
On 15/7/24 10:21, Zhao Liu wrote:
For qemu_open_old(), osdep.h said:
Don't introduce new usage of this function, prefer the following
qemu_open/qemu_create that take an "Error **errp".
So replace qemu_open_old() with qemu_open().
Cc: David Hildenbrand
Cc: Igor Mammedov
Signed-off-by: Zhao
On 15/7/24 10:21, Zhao Liu wrote:
For qemu_open_old(), osdep.h said:
Don't introduce new usage of this function, prefer the following
qemu_open/qemu_create that take an "Error **errp".
So replace qemu_open_old() with qemu_open().
Cc: Alex Williamson
Cc: "Cédric Le Goater"
Signed-off-by: Zh
On 15/7/24 10:21, Zhao Liu wrote:
For qemu_open_old(), osdep.h said:
Don't introduce new usage of this function, prefer the following
qemu_open/qemu_create that take an "Error **errp".
So replace qemu_open_old() with qemu_open(). And considering
rng_random_opened() will lose its obvious error
On 11/7/24 09:24, Ani Sinha wrote:
load_image_gzipped() does not seem to be used anywhere. Remove it.
Signed-off-by: Ani Sinha
---
hw/core/loader.c| 13 -
include/hw/loader.h | 4 +---
2 files changed, 1 insertion(+), 16 deletions(-)
Patch queued, thanks.
Hi Daniel, got a public branch I could pull?
On Mon, Jul 15, 2024 at 11:46:54AM +0200, Philippe Mathieu-Daudé wrote:
> Date: Mon, 15 Jul 2024 11:46:54 +0200
> From: Philippe Mathieu-Daudé
> Subject: Re: [PATCH 7/7] backends/rng-random: Get rid of qemu_open_old()
>
> On 15/7/24 10:21, Zhao Liu wrote:
> > For qemu_open_old(), osdep.h said:
>
On 27/6/24 14:58, Philippe Mathieu-Daudé wrote:
v2:
- Only skip mmio-related code in loongson_ipi_realize()
Jiaxun Yang (1):
hw/intc/loongson_ipi: Gate MMIO regions creation with property
include/hw/intc/loongson_ipi.h | 1 +
hw/intc/loongson_ipi.c | 16 ++--
hw/mips
This series implements basic functions of IOPMP specification v0.9.1 rapid-k
model.
The specification url:
https://github.com/riscv-non-isa/iopmp-spec/releases/tag/v0.9.1
When IOPMP is enabled, memory access to system memory from devices and
the CPU will be checked by the IOPMP.
The issue of CPU
Signed-off-by: Ethan Chen
---
target/riscv/cpu_cfg.h| 2 ++
target/riscv/cpu_helper.c | 18 +++---
2 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index fb7eebde52..2946fec20c 100644
--- a/target/riscv/cpu_cfg.h
+++
Support basic functions of IOPMP specification v0.9.1 rapid-k model.
The specification url:
https://github.com/riscv-non-isa/iopmp-spec/releases/tag/v0.9.1
The IOPMP checks whether memory access from a device or CPU is valid.
This implementation uses an IOMMU to modify the address space accessed
b
If the IOMMU granularity is smaller than the TARGET_PAGE size, there may be
multiple entries within the same page. To obtain the correct result, pass
the original address to the IOMMU.
Similar to the RISC-V PMP solution, the TLB_INVALID_MASK will be set when
there are multiple entries in the same
Allow memory regions to have different behaviors for read and fetch
operations.
For example, the RISC-V IOPMP could raise an interrupt when the CPU
tries to fetch from a non-executable region.
If the fetch operation for a memory region is not implemented, the read
operation will still be used for
On 15/7/24 11:59, Zhao Liu wrote:
As the comment in qapi/error, dereferencing @errp requires
ERRP_GUARD():
* = Why, when and how to use ERRP_GUARD() =
*
* Without ERRP_GUARD(), use of the @errp parameter is restricted:
* - It must not be dereferenced, because it may be null.
...
* ERRP_GUARD() l
06.07.2024 00:50, Brian Cain wrote:
On 7/4/2024 3:47 AM, Zhao Liu wrote:
Fix the superfluous trailing semicolon in target/hexagon/imported/mmvec/
ext.idef.
Cc: Brian Cain
Signed-off-by: Zhao Liu
Reviewed-by: Brian Cain
Brian, is it okay to fix this in something "imported" ?
I realize yo
04.07.2024 11:47, Zhao Liu wrote:
Hi,
I checked the files in QEMU to fix these few errors about "superfluous
trailing semicolon" to honor the requirement in checkpatch.pl.
Applied to the trivial-patches queue (pending confirmation from Brian
for the 4th patch).
Thanks,
/mjt
--
GPG Key trans
Richard Henderson writes:
> This operation has float16 inputs and thus must use
> the FZ16 control not the FZ control.
>
> Cc: qemu-sta...@nongnu.org
> Reported-by: Daniyal Khan
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2374
> Signed-off-by: Richard Henderson
Reviewed-by: Alex
Richard Henderson writes:
> From: Daniyal Khan
>
> Signed-off-by: Daniyal Khan
> Message-Id: 172090222034.13953.1688870870882292209...@git.sr.ht
> [rth: Split test cases to separate patch, tidy assembly.]
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisa
On 2024/7/15 下午5:57, Philippe Mathieu-Daudé wrote:
On 27/6/24 14:58, Philippe Mathieu-Daudé wrote:
v2:
- Only skip mmio-related code in loongson_ipi_realize()
Jiaxun Yang (1):
hw/intc/loongson_ipi: Gate MMIO regions creation with property
include/hw/intc/loongson_ipi.h | 1 +
hw/intc
On Jul 12 10:36, Changqi Lu wrote:
> Add reservation acquire, reservation register,
> reservation release and reservation report commands
> in the nvme device layer.
>
> By introducing these commands, this enables the nvme
> device to perform reservation-related tasks, including
> querying keys, q
On 4/7/24 22:58, Bernhard Beschow wrote:
Makes the code more comprehensible, matches the datasheet and the piix4 device
model.
Signed-off-by: Bernhard Beschow
---
hw/isa/vt82c686.c | 2 +-
hw/mips/fuloong2e.c | 2 +-
hw/ppc/amigaone.c | 4 ++--
hw/ppc/pegasos2.c | 4 ++--
4 files ch
To enable system memory transactions through the IOPMP, memory regions must
be moved to the IOPMP downstream and then replaced with IOMMUs for IOPMP
translation.
The iopmp_setup_system_memory() function copies subregions of system memory
to create the IOPMP downstream and then replaces the specifi
On Thu, 11 Jul 2024 at 21:08, Peter Xu wrote:
> Hmm, I thought it was one of the vcpu threads that invoked
> vhost_dev_start(), rather than any migration thread?
[QEMU=vhost-user-front-end] <===> [QEMU=vhost-user-front-end]
^
The iopmp_setup_cpu() function configures the RISCV CPU to support IOPMP and
specifies the CPU's RRID.
Signed-off-by: Ethan Chen
---
hw/misc/riscv_iopmp.c | 6 ++
include/hw/misc/riscv_iopmp.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/hw/misc/riscv_iopmp.c b/hw/misc/riscv
The iopmp_dma_rw() function performs memory read/write operations to system
memory with support for IOPMP. It sends transaction information to the IOPMP
for partial hit detection.
Signed-off-by: Ethan Chen
---
hw/misc/riscv_iopmp.c | 68 +++
include/hw/mis
- Add 'iopmp=on' option to enable IOPMP. It adds an iopmp device virt machine
to protect all regions of system memory, and configures RRID of CPU.
Signed-off-by: Ethan Chen
---
docs/system/riscv/virt.rst | 5 +++
hw/riscv/Kconfig | 1 +
hw/riscv/virt.c| 63 +
On 15/7/24 12:08, maobibo wrote:
On 2024/7/15 下午5:57, Philippe Mathieu-Daudé wrote:
On 27/6/24 14:58, Philippe Mathieu-Daudé wrote:
v2:
- Only skip mmio-related code in loongson_ipi_realize()
Jiaxun Yang (1):
hw/intc/loongson_ipi: Gate MMIO regions creation with property
include/hw/int
On Thu, 11 Jul 2024 at 20:11, Michael S. Tsirkin wrote:
> Could you supply a Fixes tag here? What commit introduced the race?
'postcopy_end' message was added by:
->
https://github.com/qemu/qemu/commit/46343570c06e63b4499f619011df80f91349cd49
Not sure if its race condition also began with it.
On Mon, Jul 15, 2024 at 11:52:10AM +0200, Markus Armbruster wrote:
> Hi Daniel, got a public branch I could pull?
This particular v1 posting:
https://gitlab.com/berrange/qemu/-/tags/qga-features-v1
Or latest git master rebase
https://gitlab.com/berrange/qemu/-/tree/qga-features
NB, this
Hi Salil,
On 13-07-2024 23:55, Salil Mehta wrote:
[Note: References are present at the last after the revision history]
Virtual CPU hotplug support is being added across various architectures [1][3].
This series adds various code bits common across all architectures:
1. vCPU creation and Parki
15.07.2024 13:10, Zhao Liu wrote:
...
Thanks Philippe! I'll wait patch 1's comment, after that I can post a
new version with the change you mentioned.
I don't think either of this is necessary. Patch 1 LGTM, and I'll
drop the comment while applying.
/mjt
--
GPG Key transition (from rsa2048 t
Hi Vishnu,
On Mon, 15 Jul 2024 at 12:04, Vishnu Pajjuri <
vis...@amperemail.onmicrosoft.com> wrote:
> Hi Salil,
> On 13-07-2024 23:55, Salil Mehta wrote:
>
> [Note: References are present at the last after the revision history]
>
> Virtual CPU hotplug support is being added across various archite
On Sat, Jul 13, 2024 at 07:25:09PM +0100, Salil Mehta wrote:
> [Note: References are present at the last after the revision history]
Igor any comments before I merge this?
--
MST
Hi Igor,
We are approaching end of this Qemu cycle, I believe that’s on 17th July. If
you are
satisfied with the changes. May I request your Reviewed/Acked-Bys for this
series?
This series is vouched by many companies. It will be good it to merge it in
this cycle.
Best regards
Salil.
> Fr
Hi Michael,
> From: Michael S. Tsirkin
> Sent: Monday, July 15, 2024 12:13 PM
> To: Salil Mehta
>
> On Sat, Jul 13, 2024 at 07:25:09PM +0100, Salil Mehta wrote:
> > [Note: References are present at the last after the revision history]
>
> Igor any comments before I merge this?
Hi Mich
Hi Peter/Richard,
On 09-07-2024 11:34 am, Ganapatrao Kulkarni wrote:
Extend the 'mte' property for the virt machine to cover KVM as
well. For KVM, we don't allocate tag memory, but instead enable
the capability.
If MTE has been enabled, we need to disable migration, as we do not
yet have a wa
On Mon, Jul 15, 2024 at 11:27:57AM +, Salil Mehta wrote:
> Hi Michael,
>
> > From: Michael S. Tsirkin
> > Sent: Monday, July 15, 2024 12:13 PM
> > To: Salil Mehta
> >
> > On Sat, Jul 13, 2024 at 07:25:09PM +0100, Salil Mehta wrote:
> > > [Note: References are present at the last after
> From: Michael S. Tsirkin
> Sent: Monday, July 15, 2024 12:33 PM
> To: Salil Mehta
>
> On Mon, Jul 15, 2024 at 11:27:57AM +, Salil Mehta wrote:
> > Hi Michael,
> >
> > > From: Michael S. Tsirkin
> > > Sent: Monday, July 15, 2024 12:13 PM
> > > To: Salil Mehta
> > >
> > > O
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