The function sev_encrypt_flash() checks to see if the return value of
launch_update_data() < 0, but the function returns a non-zero (and not
necessarily negative) result on error. This means that some errors in
updating launch data will result in the function returning success.
In addition, the fu
When using an IGVM file the configuration of the system firmware is
defined by IGVM directives contained in the file. In this case the user
should not configure any pflash devices.
This commit skips initialization of the ROM mode when pflash0 is not set
then checks to ensure no pflash devices have
An IGVM file contains configuration of guest state that should be
applied during configuration of the guest, before the guest is started.
This patch allows the user to add an igvm-cfg object to an X86 machine
configuration that allows an IGVM file to be configured that will be
applied to the guest
Adds an IGVM loader to QEMU which processes a given IGVM file and
applies the directives within the file to the current guest
configuration.
The IGVM loader can be used to configure both confidential and
non-confidential guests. For confidential guests, the
ConfidentialGuestSupport object for the
The IGVM library allows Independent Guest Virtual Machine files to be
parsed and processed. IGVM files are used to configure guest memory
layout, initial processor state and other configuration pertaining to
secure virtual machines.
This adds the --enable-igvm configure option, enabled by default,
Queued, thanks.
Paolo
On Wed, 3 Jul 2024, Bernhard Beschow wrote:
Am 3. Juli 2024 00:09:45 UTC schrieb BALATON Zoltan :
On Tue, 2 Jul 2024, Bernhard Beschow wrote:
Am 2. Juli 2024 18:42:23 UTC schrieb Bernhard Beschow :
Am 1. Juli 2024 12:58:15 UTC schrieb Peter Maydell :
On Sat, 29 Jun 2024 at 21:01, BALATON Zolt
Hi
On Wed, Jul 3, 2024 at 12:57 AM wrote:
> From: Dongwon Kim
>
> There is no reason to split those two operations so combining
> two functions - egl_dmabuf_create_sync and egl_dmabuf_create_fence.
>
> v2: egl_dmabuf_create_fence -> egl_dmabuf_create_fence_fd
> (Marc-André Lureau )
>
> Cc:
AVX-VNNI-INT16 (CPUID[EAX=7,ECX=1).EDX[10]) is supported by Clearwater
Forest processor, add it to QEMU as it does not need any specific
enablement.
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i
On 2024/7/2 13:52, CLEMENT MATHIEU--DRIF wrote:
From: Clément Mathieu--Drif
We use this information in vtd_do_iommu_translate to populate the
IOMMUTLBEntry and indicate the correct page mask. This prevents ATS
devices from sending many useless translation requests when a megapage
or gigapage io
On 2024/7/2 13:52, CLEMENT MATHIEU--DRIF wrote:
From: Clément Mathieu--Drif
Signed-off-by: Clément Mathieu--Drif
---
hw/pci/pcie.c | 24 +++
include/hw/pci/pcie.h | 6 +-
include/hw/pci/pcie_regs.h| 3
On Wed, 03 Jul 2024 11:59, Philippe Mathieu-Daudé wrote:
Commit c3287c0f70 ("hw/sd: Introduce a "sd-card" SPI variant
model") removed the 'spi' property. Remove the comment left
over.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sd.c | 4
1 file changed, 4 deletions(-)
diff --git a/hw/
On Wed, Jul 3, 2024, 4:00 AM Paolo Bonzini wrote:
> On 7/2/24 21:59, John Snow wrote:
> > With RHEL 8 support retired (It's been two years today since RHEL 9
> > came out), our very oldest build platform version of Sphinx is now
> > 3.4.3; and keeping backwards compatibility for versions as old a
On 3/7/24 12:01, Manos Pitsidianakis wrote:
Hello Daniel,
This cleanup seems like a good idea,
On Thu, 13 Jun 2024 18:44, "Daniel P. Berrangé"
wrote:
It is confusing having many different pieces of code enabling and
disabling commands, and it is not clear that they all have the same
semantic
On 2024/7/2 13:52, CLEMENT MATHIEU--DRIF wrote:
From: Clément Mathieu--Drif
IOMMU have to implement iommu_ats_request_translation to support ATS.
Devices can use IOMMU_TLB_ENTRY_TRANSLATION_ERROR to check the tlb
entries returned by a translation request.
Signed-off-by: Clément Mathieu--Drif
On Wed, Jul 3, 2024 at 2:06 PM John Snow wrote:
> On Wed, Jul 3, 2024, 4:00 AM Paolo Bonzini wrote:
>> On 7/2/24 21:59, John Snow wrote:
>> > With RHEL 8 support retired (It's been two years today since RHEL 9
>> > came out), our very oldest build platform version of Sphinx is now
>> > 3.4.3; and
On Wed, 03 Jul 2024 11:59, Philippe Mathieu-Daudé wrote:
"General command" (GEN_CMD, CMD56) is described as:
GEN_CMD is the same as the single block read or write
commands (CMD24 or CMD17). The difference is that [...]
the data block is not a memory payload data but has a
vendor specific fo
Hi CMD,
I've went through the series. Some general suggestions on the series.
1) Patch 01, 02, 04 can be sent separately as they are fixes.
2) This series mixed the ATS and PASID capability a bit. Actually,
they don't have dependency. I'd suggest you split the series into
- support ATS
From: TANG Tiancheng
This patch set aims to expose 32-bit RISC-V cpu to RV64 QEMU. Thus
qemu-system-riscv64 can directly boot a RV32 Linux.
This patch set has been tested with 6.9.0 Linux Image.
And add an avocado test in tests/avocado.
v2:
Remove the line that was inadvertently left in PATCH
From: TANG Tiancheng
RV32 OpenSBI need a fw_dynamic_info parameter with 32-bit fields instead
of target_ulong.
In RV64 QEMU, target_ulong is 64. So it is not right for booting RV32 OpenSBI.
We create a fw_dynmaic_info32 struct for this purpose.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zh
From: TANG Tiancheng
Ensure pmp_size is correctly determined using mxl for RV32
in RV64 QEMU.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/pmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/pmp.c b/ta
From: TANG Tiancheng
Ensure that riscv_cpu_sxl returns MXL_RV32 when runningRV32 in an
RV64 QEMU.
Signed-off-by: TANG Tiancheng
Fixes: 05e6ca5e156 ("target/riscv: Ignore reserved bits in PTE for RV64")
Reviewed-by: Liu Zhiwei
---
target/riscv/cpu.h | 5 -
1 file changed, 4 insertions(+),
From: TANG Tiancheng
Ensure correct bit width based on sxl when running RV32 on RV64 QEMU.
This is required as MMU address translations run in S-mode.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
target/riscv/cpu_helper.c | 17 -
1 file changed, 12 insertions(+),
From: TANG Tiancheng
Ensure mcause high bit is correctly set by using 32-bit width for RV32
mode and 64-bit width for RV64 mode.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
target/riscv/cpu_helper.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/targ
From: TANG Tiancheng
Add gdb XML files and adjust CPU initialization to allow running RV32 CPUs
in RV64 QEMU.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
configs/targets/riscv64-softmmu.mak | 2 +-
target/riscv/cpu.c | 17 +
2 files changed, 14
From: TANG Tiancheng
To regularly test booting Linux with rv32 on QEMU RV64,
we have added a test to boot_linux_console.py to retrieve
cpuinfo and verify if it shows 'rv32' when using RV64 to
boot rv32 CPUs.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tests/avocado/boot_linux_co
On 7/3/24 10:16 AM, Jamin Lin wrote:
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35)
And the base address of dram is "0x4 " which
is 64bits address.
It have "Normal Priority Transmit Ring Base Address Register High(0x17C)",
"High Priority Transmit Ring Base Address Register H
Hi
(adding Sebastian, one of the glib-rs developers in CC)
On Mon, Jul 1, 2024 at 7:02 PM Paolo Bonzini wrote:
> The qemu::util::foreign module provides:
>
> - A trait for structs that can be converted to a C ("foreign")
> representation
> (CloneToForeign)
>
> - A trait for structs that can b
Hi
On Wed, Jul 3, 2024 at 4:48 PM Marc-André Lureau
wrote:
> Hi
>
> (adding Sebastian, one of the glib-rs developers in CC)
>
> On Mon, Jul 1, 2024 at 7:02 PM Paolo Bonzini wrote:
>
>> The qemu::util::foreign module provides:
>>
>> - A trait for structs that can be converted to a C ("foreign")
Hi,
On 3/7/24 14:34, LIU Zhiwei wrote:
From: TANG Tiancheng
This patch set aims to expose 32-bit RISC-V cpu to RV64 QEMU. Thus
qemu-system-riscv64 can directly boot a RV32 Linux.
This patch set has been tested with 6.9.0 Linux Image.
And add an avocado test in tests/avocado.
v2:
Remove th
On 3/7/24 14:24, Manos Pitsidianakis wrote:
On Wed, 03 Jul 2024 11:59, Philippe Mathieu-Daudé
wrote:
"General command" (GEN_CMD, CMD56) is described as:
GEN_CMD is the same as the single block read or write
commands (CMD24 or CMD17). The difference is that [...]
the data block is not a memo
On Wed, Jul 03, 2024 at 01:00:21PM +0200, BALATON Zoltan wrote:
> On Wed, 3 Jul 2024, Michael S. Tsirkin wrote:
> > On Wed, Jul 03, 2024 at 04:15:23AM +0200, BALATON Zoltan wrote:
> > > On Tue, 2 Jul 2024, Michael S. Tsirkin wrote:
> > > > On Thu, Jun 27, 2024 at 03:08:00PM +0900, Akihiko Odaki wro
In preparation of introducing eMMC support which have
different CSD/CID structures, introduce a pair of handlers
in SDCardClass.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/sd/sd.h | 2 ++
hw/sd/sd.c | 7 +--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/inc
"General command" (GEN_CMD, CMD56) is described as:
GEN_CMD is the same as the single block read or write
commands (CMD24 or CMD17). The difference is that [...]
the data block is not a memory payload data but has a
vendor specific format and meaning.
Thus this block must not be stored ov
Recent SDHCI expect cards to support the v3.01 spec
to negociate lower I/O voltage. Select it by default.
Versioned machine types with a version of 9.0 or
earlier retain the old default (spec v2.00).
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Cédric Le Goater
---
v43: update versioned m
In order to keep eMMC model simpler to maintain,
extract common properties and the common code from
class_init to the (internal) TYPE_SDMMC_COMMON.
Update the corresponding QOM cast macros.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sdmmc-internal.h | 3 +++
hw/sd/core.c | 29 ++
The correct command name is 'SD SEND_OP_COND',
rename accordingly.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sd.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index 04e8fdb262..10f2764a53 100644
--- a/hw/sd/sd.c
+++ b/hw/sd/sd.c
@@ -1701,7
(patches from v42 already reviewed not reposted)
Since v45:
- RAZ/WI on GEN_CMD (Luc & Manos)
- Rename sd_cmd_SEND_OP_COND
- Introduce TYPE_SDMMC_COMMON
Philippe Mathieu-Daudé (5):
hw/sd/sdcard: Use spec v3.01 by default
hw/sd/sdcard: Add sd_cmd_GEN_CMD handler (CMD56)
hw/sd/sdcard: Rename
On 7/3/24 3:43 PM, Philippe Mathieu-Daudé wrote:
The correct command name is 'SD SEND_OP_COND',
rename accordingly.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/sd/sd.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw
On 7/3/24 3:43 PM, Philippe Mathieu-Daudé wrote:
In preparation of introducing eMMC support which have
different CSD/CID structures, introduce a pair of handlers
in SDCardClass.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
include/hw/sd/sd.h | 2
On 7/3/24 3:43 PM, Philippe Mathieu-Daudé wrote:
In order to keep eMMC model simpler to maintain,
extract common properties and the common code from
class_init to the (internal) TYPE_SDMMC_COMMON.
Update the corresponding QOM cast macros.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sdmmc
We want to have some non-Linux OS in testing in case one of changes keep
Linux booting but crash elsewhere. So far OpenBSD was used for it but we
move to FreeBSD 14.x due to longer support cycles.
One OpenBSD stays - will be run on Cortex-A57 only. And only on local
runs hidden behind AVOCADO_TEST
We changed sbsa-ref cpu several times already and may do it again in a
future. To newer core or to enable/disable some properties.
This change switches Neoverse-N2 tests to 'let test default cpu' ones.
Signed-off-by: Marcin Juszkiewicz
---
tests/avocado/machine_aarch64_sbsaref.py | 29 +
On 3/7/24 16:02, Cédric Le Goater wrote:
On 7/3/24 3:43 PM, Philippe Mathieu-Daudé wrote:
In order to keep eMMC model simpler to maintain,
extract common properties and the common code from
class_init to the (internal) TYPE_SDMMC_COMMON.
Update the corresponding QOM cast macros.
Signed-off-by:
FreeBSD has longer support cycle for stable release (14.x EoL in 2028)
than OpenBSD (7.3 we used is already EoL). Also bugfixes are backported
so we can stay on 14.x for longer. Tests done on OpenBSD will now be
done using FreeBSD.
OpenBSD 7.3 stays with Cortex-A57 test for local runs only.
Moved
On 7/3/24 4:07 PM, Philippe Mathieu-Daudé wrote:
On 3/7/24 16:02, Cédric Le Goater wrote:
On 7/3/24 3:43 PM, Philippe Mathieu-Daudé wrote:
In order to keep eMMC model simpler to maintain,
extract common properties and the common code from
class_init to the (internal) TYPE_SDMMC_COMMON.
Update
On 3/7/24 16:06, Marcin Juszkiewicz wrote:
FreeBSD has longer support cycle for stable release (14.x EoL in 2028)
than OpenBSD (7.3 we used is already EoL). Also bugfixes are backported
so we can stay on 14.x for longer. Tests done on OpenBSD will now be
done using FreeBSD.
OpenBSD 7.3 stays wit
On 3/7/24 16:06, Marcin Juszkiewicz wrote:
We changed sbsa-ref cpu several times already and may do it again in a
future. To newer core or to enable/disable some properties.
This change switches Neoverse-N2 tests to 'let test default cpu' ones.
Signed-off-by: Marcin Juszkiewicz
---
tests/avo
When enforce_cpuid is set to false, the guest is launched with a filtered
set of features, meaning that unsupported features by the host are removed
from the guest's vCPU model. This could cause issues for live migration.
For example, a guest on the source is running with features A and B. If
the d
On 6/25/2024 5:19 PM, EwanHai wrote:
Zhaoxin and VIA CPUs handle the CMPLegacy bit in the same way
as Intel CPUs. This patch simplifies the existing logic by
using the IS_XXX_CPU macro and includes checks for Zhaoxin
and VIA vendors to align their behavior with Intel.
Signed-off-by: EwanHai
---
This patch set aims to expose 32-bit RISC-V cpu to RV64 QEMU. Thus
qemu-system-riscv64 can directly boot a RV32 Linux.
This patch set has been tested with 6.9.0 Linux Image.
And add an avocado test in tests/avocado.
v3:
Rebase to the master branch
v2:
Remove the line that was inadvertently l
From: TANG Tiancheng
RV32 OpenSBI need a fw_dynamic_info parameter with 32-bit fields instead
of target_ulong.
In RV64 QEMU, target_ulong is 64. So it is not right for booting RV32 OpenSBI.
We create a fw_dynmaic_info32 struct for this purpose.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zh
From: TANG Tiancheng
Ensure pmp_size is correctly determined using mxl for RV32
in RV64 QEMU.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/pmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/pmp.c b/ta
From: TANG Tiancheng
Ensure that riscv_cpu_sxl returns MXL_RV32 when runningRV32 in an
RV64 QEMU.
Signed-off-by: TANG Tiancheng
Fixes: 05e6ca5e156 ("target/riscv: Ignore reserved bits in PTE for RV64")
Reviewed-by: Liu Zhiwei
---
target/riscv/cpu.h | 5 -
1 file changed, 4 insertions(+),
From: TANG Tiancheng
Ensure correct bit width based on sxl when running RV32 on RV64 QEMU.
This is required as MMU address translations run in S-mode.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
target/riscv/cpu_helper.c | 17 -
1 file changed, 12 insertions(+),
From: TANG Tiancheng
Ensure mcause high bit is correctly set by using 32-bit width for RV32
mode and 64-bit width for RV64 mode.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
target/riscv/cpu_helper.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/targ
From: TANG Tiancheng
Add gdb XML files and adjust CPU initialization to allow running RV32 CPUs
in RV64 QEMU.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
configs/targets/riscv64-softmmu.mak | 2 +-
target/riscv/cpu.c | 17 +
2 files changed, 14
From: TANG Tiancheng
To regularly test booting Linux with rv32 on QEMU RV64,
we have added a test to boot_linux_console.py to retrieve
cpuinfo and verify if it shows 'rv32' when using RV64 to
boot rv32 CPUs.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tests/avocado/boot_linux_co
On Wed, Jul 03, 2024 at 03:53:08PM +0530, Sunil V L wrote:
> On Tue, Jul 02, 2024 at 03:02:36PM +0100, Jonathan Cameron wrote:
> > On Mon, 1 Jul 2024 17:03:43 -0400
> > "Michael S. Tsirkin" wrote:
> >
> > > On Thu, Jun 27, 2024 at 02:18:03PM +0200, Igor Mammedov wrote:
> > > > On Tue, 25 Jun 2024
On Wed, 3 Jul 2024 13:00:21 +0200 (CEST)
BALATON Zoltan wrote:
> On Wed, 3 Jul 2024, Michael S. Tsirkin wrote:
> > On Wed, Jul 03, 2024 at 04:15:23AM +0200, BALATON Zoltan wrote:
> >> On Tue, 2 Jul 2024, Michael S. Tsirkin wrote:
> >>> On Thu, Jun 27, 2024 at 03:08:00PM +0900, Akihiko Odaki w
From: Mi
Add a Virtio backend for SD/MMC devices. Confirmed interoperability with
Linux.
Linux patch link:
https://lore.kernel.org/linux-mmc/20240701120642.30001-1-krashmi...@gmail.com/
Signed-off-by: Mikhail Krasheninnikov
CC: Matwey Kornilov
CC: qemu-bl...@nongnu.org
CC: Michael S. Tsirkin
On 2024/7/3 21:08, Philippe Mathieu-Daudé wrote:
Hi,
On 3/7/24 14:34, LIU Zhiwei wrote:
From: TANG Tiancheng
This patch set aims to expose 32-bit RISC-V cpu to RV64 QEMU. Thus
qemu-system-riscv64 can directly boot a RV32 Linux.
This patch set has been tested with 6.9.0 Linux Image.
And add
On Wed, Jul 3, 2024 at 8:12 AM Paolo Bonzini wrote:
> On Wed, Jul 3, 2024 at 2:06 PM John Snow wrote:
> > On Wed, Jul 3, 2024, 4:00 AM Paolo Bonzini wrote:
> >> On 7/2/24 21:59, John Snow wrote:
> >> > With RHEL 8 support retired (It's been two years today since RHEL 9
> >> > came out), our ver
On Wed, Jul 3, 2024 at 5:53 AM Markus Armbruster wrote:
> Commit 8f9a9259d32c added ObjectType member @x-vfio-user-server with
> feature unstable, but neglected to explain why it is unstable. Do
> that now.
>
> Fixes: 8f9a9259d32c (vfio-user: define vfio-user-server object)
> Cc: Elena Ufimtseva
[warning: long email]
On Wed, Jul 3, 2024 at 2:48 PM Marc-André Lureau
wrote:
>
> Hi
>
> (adding Sebastian, one of the glib-rs developers in CC)
>
> On Mon, Jul 1, 2024 at 7:02 PM Paolo Bonzini wrote:
>>
>> The qemu::util::foreign module provides:
>>
>> - A trait for structs that can be converte
Ensure that the local_mem_size_index is within valid bounds and does not
exceed the allocated memory size before updating it in sm501_system_config_write
to prevent out-of-bounds read.
ASAN log:
==3067247==ERROR: AddressSanitizer: global-buffer-overflow on address
0x55c6586e4d3c at pc 0x55c655d4e
Thanks David for the response.
On 2 Jul 2024, at 2:34 PM, David Woodhouse wrote:
On Tue, 2024-07-02 at 05:17 +, Sandesh Patel wrote:
Hi All,
Is it possible to setup a large Windows VM (say 512 vcpus) without
adding viommu (EIM=on, IR=on)?
When I try to power such VM, the qemu process crashes
Mikhail Krasheninnikov writes:
> From: Mi
>
> Add a Virtio backend for SD/MMC devices. Confirmed interoperability with
> Linux.
>
> Linux patch link:
> https://lore.kernel.org/linux-mmc/20240701120642.30001-1-krashmi...@gmail.com/
Is there a corresponding patch to the VirtIO specification?
--
On Wed, Jul 3, 2024 at 5:25 PM John Snow wrote:
> To be clear I mean offline, isolated RPM builds under RHEL9 where I don't
> think we can utilize PyPI at all; and vendoring Sphinx is I think not a
> practical option due to the number of dependencies and non-pure Python deps.
>
> It's not a prob
On 7/2/24 13:15, Michael S. Tsirkin wrote:
The following changes since commit 1152a0414944f03231f3177207d379d58125890e:
Merge tag 'pull-xen-20240701'
ofhttps://xenbits.xen.org/git-http/people/aperard/qemu-dm into staging
(2024-07-01 09:06:25 -0700)
are available in the Git repository at:
On 7/3/24 03:43, Paolo Bonzini wrote:
Fixes: 70943ad8e4d ("i386/sev: Add support for SNP CPUID validation",
2024-06-05)
Signed-off-by: Paolo Bonzini
---
target/i386/sev.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson
r~
On 7/3/24 07:49, LIU Zhiwei wrote:
-pmp_size = sizeof(target_ulong);
+pmp_size = 2UL << riscv_cpu_mxl(env);
UL is almost always incorrect in qemu, as 'long' has no specifically useful
meaning.
In this case you can drop it completely.
r~
On 7/3/24 07:49, LIU Zhiwei wrote:
+sxlen = 16UL << riscv_cpu_sxl(env);
As before, drop UL.
r~
On Wed, Jul 03, 2024 at 09:31:45AM -0700, Richard Henderson wrote:
> On 7/2/24 13:15, Michael S. Tsirkin wrote:
> > The following changes since commit 1152a0414944f03231f3177207d379d58125890e:
> >
> >Merge tag 'pull-xen-20240701'
> > ofhttps://xenbits.xen.org/git-http/people/aperard/qemu-dm
On 7/3/24 09:51, Michael S. Tsirkin wrote:
On Wed, Jul 03, 2024 at 09:31:45AM -0700, Richard Henderson wrote:
On 7/2/24 13:15, Michael S. Tsirkin wrote:
The following changes since commit 1152a0414944f03231f3177207d379d58125890e:
Merge tag 'pull-xen-20240701'
ofhttps://xenbits.xen.org/git
From: Brad Smith
Signed-off-by: Brad Smith
Message-Id:
Signed-off-by: Richard Henderson
---
util/cpuinfo-ppc.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/util/cpuinfo-ppc.c b/util/cpuinfo-ppc.c
index 47af55aa0c..1304f9aa80 100644
--- a/util/cpuinfo-ppc.c
+++ b
From: Brad Smith
OpenBSD does not support AT_HWCAP.
Signed-off-by: Brad Smith
Message-Id:
Signed-off-by: Richard Henderson
---
util/cpuinfo-ppc.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/util/cpuinfo-ppc.c b/util/cpuinfo-ppc.c
index b2d8893a06
From: Brad Smith
Signed-off-by: Brad Smith
Reviewed-by: Richard Henderson
Message-Id:
Signed-off-by: Richard Henderson
---
util/cpuinfo-aarch64.c | 36
1 file changed, 36 insertions(+)
diff --git a/util/cpuinfo-aarch64.c b/util/cpuinfo-aarch64.c
index 4c
Move detection code out of tcg, similar to other hosts.
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Richard Henderson
---
host/include/riscv/host/cpuinfo.h | 23 +
tcg/riscv/tcg-target.h
With recent linux kernels, there is a syscall to probe for various
ISA extensions. These bits were phased in over several kernel
releases, so we still require checks for symbol availability.
Acked-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Richard Henderson
---
m
The following changes since commit 6746482d12da3b6e4d3cdf06481a0027a797f719:
Merge tag 'sdmmc-20240702' of https://github.com/philmd/qemu into staging
(2024-07-02 09:52:10 -0700)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu tags/pull-tcg-20240703
Reported-by: Brad Smith
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Signed-off-by: Richard Henderson
---
util/cpuinfo-riscv.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c
index 1236e
Argument ordering for setcond2 is:
output, a_low, a_high, b_low, b_high, cond
The test is supposed to be against b_low, not a_high.
Cc: qemu-sta...@nongnu.org
Fixes: ceb9ee06b71 ("tcg/optimize: Handle TCG_COND_TST{EQ,NE}")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2413
Signed-off
With RHEL 8 support retired (It's been two years since RHEL9 released),
our very oldest build platform version of Sphinx is now 3.4.3; and
keeping backwards compatibility for versions as old as v1.6 when using
domain extensions is a lot of work we don't need to do.
This patch is motivated by my wo
In general, the Use_SSI workaround is no longer needed, and neither is
the pre-1.6 logging shim for kerneldoc.
Signed-off-by: John Snow
Acked-by: Markus Armbruster
---
docs/sphinx/hxtool.py| 21 -
docs/sphinx/kerneldoc.py | 38 --
docs
With recent deprecations, we can advance our minimum sphinx version
safely. This is heavily motivated by new qapidoc work which is much
easier to maintain cross-version compatibility for - see difficulties in
our dbus documentation which only works on sphinx >= 4.
We can only guarantee >= 3.4.3 no
On Wed, Jul 03, 2024 at 10:49:12PM +0800, Wei Wang wrote:
> When enforce_cpuid is set to false, the guest is launched with a filtered
> set of features, meaning that unsupported features by the host are removed
> from the guest's vCPU model. This could cause issues for live migration.
> For example
On 7/2/24 09:39, Kevin Wolf wrote:
The following changes since commit c80a339587fe4148292c260716482dd2f86d4476:
Merge tag 'pull-target-arm-20240701'
ofhttps://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-07-01
10:41:45 -0700)
are available in the Git repository at:
https
On 03/07/2024 19.52, John Snow wrote:
With RHEL 8 support retired (It's been two years since RHEL9 released),
our very oldest build platform version of Sphinx is now 3.4.3; and
keeping backwards compatibility for versions as old as v1.6 when using
domain extensions is a lot of work we don't need
On 03/07/2024 19.52, John Snow wrote:
In general, the Use_SSI workaround is no longer needed, and neither is
the pre-1.6 logging shim for kerneldoc.
Signed-off-by: John Snow
Acked-by: Markus Armbruster
---
docs/sphinx/hxtool.py| 21 -
docs/sphinx/kerneldoc.py | 38 ++
On 7/2/24 11:44, Pierrick Bouvier wrote:
data was correctly copied, but size of array was not set
(g_array_sized_new only reserves memory, but does not set size).
As a result, callbacks were not called for code path relying on
plugin_register_vcpu_mem_cb().
Found when trying to trigger mem acce
On Wed, 3 Jul 2024, Zheyu Ma wrote:
Ensure that the local_mem_size_index is within valid bounds and does not
exceed the allocated memory size before updating it in sm501_system_config_write
to prevent out-of-bounds read.
ASAN log:
==3067247==ERROR: AddressSanitizer: global-buffer-overflow on add
On 03/07/2024 19.01, Richard Henderson wrote:
On 7/3/24 09:51, Michael S. Tsirkin wrote:
On Wed, Jul 03, 2024 at 09:31:45AM -0700, Richard Henderson wrote:
On 7/2/24 13:15, Michael S. Tsirkin wrote:
The following changes since commit
1152a0414944f03231f3177207d379d58125890e:
Merge tag 'p
On 7/2/24 11:44, Pierrick Bouvier wrote:
Different code paths handle memory accesses:
- tcg generated code
- load/store helpers
- atomic helpers
This value is saved in cpu->plugin_state.
Atomic operations are doing read/write at the same time, so we generate
two memory callbacks instead of one,
qemu_chr_open_fd() sets stdout into non-blocking mode. Restore the old
fd flags on exit to avoid breaking unsuspecting applications that run on
the same terminal after qemu and don't expect to get EAGAIN.
While at at, also ensure term_exit is called once (at the moment it's
called both from char_s
On Wed, 3 Jul 2024 at 04:40, Zhihai Dong wrote:
>
> Make the README more clearly.
>
> Signed-off-by: Zhihai Dong
> ---
> README.rst | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/README.rst b/README.rst
> index 21df79ef43..b120a1f69e 100644
> --- a/README.rst
> ++
On Wed, Jul 03, 2024 at 08:46:38PM +0200, Thomas Huth wrote:
> On 03/07/2024 19.01, Richard Henderson wrote:
> > On 7/3/24 09:51, Michael S. Tsirkin wrote:
> > > On Wed, Jul 03, 2024 at 09:31:45AM -0700, Richard Henderson wrote:
> > > > On 7/2/24 13:15, Michael S. Tsirkin wrote:
> > > > > The follo
On Wed, Jul 03, 2024 at 03:45:53PM -0400, Michael S. Tsirkin wrote:
> On Wed, Jul 03, 2024 at 08:46:38PM +0200, Thomas Huth wrote:
> > On 03/07/2024 19.01, Richard Henderson wrote:
> > > On 7/3/24 09:51, Michael S. Tsirkin wrote:
> > > > On Wed, Jul 03, 2024 at 09:31:45AM -0700, Richard Henderson w
Queued, thanks.
Paolo
Hello, Alex!
No, there's no patch to the VirtIO specification yet. This is
proof-of-concept solution since I'm not sure that I did everything
correct with the design (and as folks' reviews show, for a good reason).
As soon as most obvious issues would be out of the way, I think I'll
submit a
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