On 7/3/24 07:49, LIU Zhiwei wrote:
+ sxlen = 16UL << riscv_cpu_sxl(env);
As before, drop UL. r~
- [PATCH v3 0/7] target/riscv: Expose RV32 cpu to RV64 QEM... LIU Zhiwei
- [PATCH v3 1/7] target/riscv: Add fw_dynamic_info32 ... LIU Zhiwei
- [PATCH v3 2/7] target/riscv: Adjust PMP size for no... LIU Zhiwei
- Re: [PATCH v3 2/7] target/riscv: Adjust PMP siz... Richard Henderson
- [PATCH v3 3/7] target/riscv: Correct SXL return val... LIU Zhiwei
- Re: [PATCH v3 3/7] target/riscv: Correct SXL re... Alistair Francis
- [PATCH v3 4/7] target/riscv: Detect sxl to set bit ... LIU Zhiwei
- Re: [PATCH v3 4/7] target/riscv: Detect sxl to ... Alistair Francis
- [PATCH v3 5/7] target/riscv: Correct mcause/scause ... LIU Zhiwei
- Re: [PATCH v3 5/7] target/riscv: Correct mcause... Richard Henderson
- [PATCH v3 6/7] target/riscv: Enable RV32 CPU suppor... LIU Zhiwei
- Re: [PATCH v3 6/7] target/riscv: Enable RV32 CP... Alistair Francis
- [PATCH v3 7/7] tests/avocado: Add an avocado test f... LIU Zhiwei
- Re: [PATCH v3 7/7] tests/avocado: Add an avocad... Alistair Francis
