Am 3. Juli 2024 00:09:45 UTC schrieb BALATON Zoltan :
>On Tue, 2 Jul 2024, Bernhard Beschow wrote:
>> Am 2. Juli 2024 18:42:23 UTC schrieb Bernhard Beschow :
>>> Am 1. Juli 2024 12:58:15 UTC schrieb Peter Maydell
>>> :
On Sat, 29 Jun 2024 at 21:01, BALATON Zoltan wrote:
>
> To av
On 2024/7/2 23:29, CLEMENT MATHIEU--DRIF wrote:
On 02/07/2024 15:33, Yi Liu wrote:
Caution: External email. Do not open attachments or click links,
unless this email comes from a known sender and you know the content
is safe.
On 2024/7/2 13:52, CLEMENT MATHIEU--DRIF wrote:
From: Clément Math
On 3/7/24 01:04, Richard Henderson wrote:
On 7/2/24 12:55, Philippe Mathieu-Daudé wrote:
On 27/6/24 20:03, Richard Henderson wrote:
...
+ info |= !got_sigill * CPUINFO_ZBA;
A bit too optimized to my taste, 'if (sigill) info|=ZBA' would be
simpler to follow.
I switched to "info
在2024年7月3日七月 下午2:40，maobibo写道：
[...]
Hi Bobo,
>
> MMIO is loongson ipi specific, it is not necessary to put into common
> function. Functions loongson_ipi_core_readl/loongson_ipi_core_writel can
> be exported in header file include/hw/intc/loongson_ipi_common.h, or get
> MemoryRegionOps of fi
On 18:10 Tue 02 Jul , Philippe Mathieu-Daudé wrote:
> "General command" (GEN_CMD, CMD56) is described as:
>
> GEN_CMD is the same as the single block read or write
> commands (CMD24 or CMD17). The difference is that [...]
> the data block is not a memory payload data but has a
> vendor
On 2024/7/3 下午3:33, Jiaxun Yang wrote:
在2024年7月3日七月 下午2:40，maobibo写道：
[...]
Hi Bobo,
MMIO is loongson ipi specific, it is not necessary to put into common
function. Functions loongson_ipi_core_readl/loongson_ipi_core_writel can
be exported in header file include/hw/intc/loongson_ipi_common
在2024年7月1日七月 下午2:57，Jiaxun Yang写道：
> 在2024年5月30日五月 上午7:49，Bibo Mao写道：
>> Loongson Binary Translation (LBT) is used to accelerate binary
>> translation, which contains 4 scratch registers (scr0 to scr3), x86/ARM
>> eflags (eflags) and x87 fpu stack pointer (ftop).
>>
>> Now LBT feature is added i
On 7/2/24 21:59, John Snow wrote:
With RHEL 8 support retired (It's been two years today since RHEL 9
came out), our very oldest build platform version of Sphinx is now
3.4.3; and keeping backwards compatibility for versions as old as v1.6
when using domain extensions is a lot of work we don't ne
On Wed, Jul 03, 2024 at 10:15:44AM +0400, Marc-André Lureau wrote:
> Hi Daniel
>
> On Tue, Jul 2, 2024 at 10:00 PM Daniel P. Berrangé
> wrote:
> >
> > Ping: for any review comments from QGA maintainers ?
>
> Maybe you could resend for patchew to correctly handle the series.
I don't want to spa
On 3/7/24 09:39, Luc Michel wrote:
On 18:10 Tue 02 Jul , Philippe Mathieu-Daudé wrote:
"General command" (GEN_CMD, CMD56) is described as:
GEN_CMD is the same as the single block read or write
commands (CMD24 or CMD17). The difference is that [...]
the data block is not a memory pa
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35)
And the base address of dram is "0x4 " which
is 64bits address.
It have "Normal Priority Transmit Ring Base Address Register High(0x17C)",
"High Priority Transmit Ring Base Address Register High(0x184)" and
"Receive Ring Base Addr
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35)
And the base address of dram is "0x4 " which
is 64bits address.
Update its network model to ftgmac100_high to support
64bits dram address DMA.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 3 ++-
1 file changed, 2 inse
change from v1:
- ftgmac100
- fix coding style
- support 64 bits dma dram address for AST2700
change from v2:
- ftgmac100: update memory region size to 0x200.
- ftgmac100: introduce a new class(ftgmac100_high),
class attribute and memop handlers, for FTGMAC100_*_HIGH regs read/write.
- aspee
Update a test case to test network connection via ssh and
changes to test Aspeed OpenBMC SDK v09.02 for AST2700.
ASPEED fixed TX mask issue from linux/drivers/ftgmac100.c.
It is required to use ASPEED SDK image since v09.02
for AST2700 QEMU network testing.
A test image is downloaded from the ASP
Hi
On Wed, Jul 3, 2024 at 12:06 PM Daniel P. Berrangé wrote:
>
> On Wed, Jul 03, 2024 at 10:15:44AM +0400, Marc-André Lureau wrote:
> > Hi Daniel
> >
> > On Tue, Jul 2, 2024 at 10:00 PM Daniel P. Berrangé
> > wrote:
> > >
> > > Ping: for any review comments from QGA maintainers ?
> >
> > Maybe
According to the datasheet of ASPEED SOCs,
one MAC controller owns 128KB of register space for AST2500.
However, one MAC controller only owns 64KB of register space for AST2600
and AST2700.
It set the memory region size 128KB and it occupied another
controllers Address Spaces.
Currently, the ftg
According to the w25q01jv datasheet at page 16,
it is required to set QE bit in "Status Register 2".
Besides, users are able to utilize "Write Status Register 1(0x01)"
command to set QE bit in "Status Register 2" and
utilize "Read Status Register 2(0x35)" command to get the QE bit status.
To suppo
These patches add functionality for unit testing RISC-V-specific registers.
The first patch adds a Qtest backend, and the second implements a simple test.
---
v4:
- Change wrapper to direct call
---
Ivan Klokov (2):
target/riscv: Add RISC-V CSR qtest support
tests/qtest: QTest example for
The RISC-V architecture supports the creation of custom
CSR-mapped devices. It would be convenient to test them in the same way
as MMIO-mapped devices. To do this, a new call has been added
to read/write CSR registers.
Signed-off-by: Ivan Klokov
---
target/riscv/cpu.c | 17 ++
ta
Added demo for reading CSR register from qtest environment.
Signed-off-by: Ivan Klokov
---
tests/qtest/meson.build | 2 +
tests/qtest/riscv-csr-test.c | 86
2 files changed, 88 insertions(+)
create mode 100644 tests/qtest/riscv-csr-test.c
diff --git a
Hi Michael,
This patch fixes a regression that was introduced in QEMU 9.0,
reported by yet another user at:
https://gitlab.com/qemu-project/qemu/-/issues/2420
Could you pull this patch into stable-9.0. If you think testing
is important for stable, the following patch adds further unit
testing
On 13/6/24 17:01, Daniel P. Berrangé wrote:
The qmp_guest_{diskstats,cpustats} command impls in
commands-posix.c are surrounded by '#ifdef __linux__' so should
instead live in commands-linux.c
This also removes a "#ifdef CONFIG_LINUX" that was nested inside
a "#ifdef __linux__".
Signed-off-by:
On 13/6/24 17:43, Daniel P. Berrangé wrote:
The qmp_guest_{set,get}_{memory_blocks,block_info} command impls in
commands-posix.c are surrounded by '#ifdef __linux__' so should
instead live in commands-linux.c
This also removes a "#ifdef CONFIG_LINUX" that was nested inside
a "#ifdef __linux__".
On 03/07/2024 09:29, Yi Liu wrote:
On 2024/7/2 23:29, CLEMENT MATHIEU--DRIF wrote:
On 02/07/2024 15:33, Yi Liu wrote:
Caution: External email. Do not open attachments or click links,
unless this email comes from a known sender and you know the content
is safe.
On 2024/7/2 13:52, CLEMENT MA
On 13/6/24 17:43, Daniel P. Berrangé wrote:
Rather than creating stubs for every command that just return
QERR_UNSUPPORTED, use 'if' conditions in the QAPI schema to
fully exclude generation of the commands on Windows.
The command will be rejected at QMP dispatch time instead,
avoiding reimpleme
On 13/6/24 17:43, Daniel P. Berrangé wrote:
Rather than creating stubs for every command that just return
QERR_UNSUPPORTED, use 'if' conditions in the QAPI schema to
fully exclude generation of the commands on non-Linux POSIX
platforms
The command will be rejected at QMP dispatch time instead,
a
On 13/6/24 17:43, Daniel P. Berrangé wrote:
Rather than creating stubs for every comamnd that just return
QERR_UNSUPPORTED, use 'if' conditions in the QAPI schema to
fully exclude generation of the network interface command on
POSIX platforms lacking getifaddrs().
The command will be rejected at
Hi Jonathan,
I appreciate your feedback and valuable suggestions. Replies inlined.
July 2, 2024 at 6:25 AM, "Jonathan Cameron" wrote:
>
> On Fri, 28 Jun 2024 06:09:23 +
>
> "Ho-Ren (Jack) Chuang" wrote:
>
> >
> > If we simply move the set_node_memory_tier() from memory_tier_init()
> >
On 13/6/24 17:43, Daniel P. Berrangé wrote:
Rather than creating stubs for every command that just return
QERR_UNSUPPORTED, use 'if' conditions in the QAPI schema to
fully exclude generation of the commands on non-Windows.
The command will be rejected at QMP dispatch time instead,
avoiding reimp
On 13/6/24 17:43, Daniel P. Berrangé wrote:
Rather than creating stubs for every command that just return
QERR_UNSUPPORTED, use 'if' conditions in the QAPI schema to
fully exclude generation of the filesystem trimming commands
on POSIX platforms lacking required APIs.
The command will be rejecte
On 13/6/24 17:43, Daniel P. Berrangé wrote:
Rather than creating stubs for every command that just return
QERR_UNSUPPORTED, use 'if' conditions in the schema to fully
exclude generation of the filesystem freezing commands on POSIX
platforms lacking the required APIs.
The command will be rejected
On 13/6/24 17:43, Daniel P. Berrangé wrote:
Rather than creating stubs for every command that just return
QERR_UNSUPPORTED, use 'if' conditions in the schema to fully
exclude generation of the filesystem trimming commands on POSIX
platforms lacking required APIs.
The command will be rejected at
On 13/6/24 17:44, Daniel P. Berrangé wrote:
Rather than creating stubs for every command that just return
QERR_UNSUPPORTED, use 'if' conditions in the QAPI schema to
fully exclude generation of the get-users command on POSIX
platforms lacking required APIs.
The command will be rejected at QMP di
03.07.2024 11:21, Daniel P. Berrangé wrote:
Hi Michael,
This patch fixes a regression that was introduced in QEMU 9.0,
reported by yet another user at:
https://gitlab.com/qemu-project/qemu/-/issues/2420
Aha.
Could you pull this patch into stable-9.0. If you think testing
is important fo
On 13/6/24 17:44, Daniel P. Berrangé wrote:
Rather than creating stubs for every command that just return
QERR_UNSUPPORTED, use 'if' conditions in the QAPI schema to
fully exclude generation of the commands on other UNIX.
The command will be rejected at QMP dispatch time instead,
avoiding reimp
On 13/6/24 17:44, Daniel P. Berrangé wrote:
It is referenced by QGAState already, and it is clearer to declare all
data types at the top of the file, rather than have them mixed with
code later.
Signed-off-by: Daniel P. Berrangé
---
qga/main.c | 44 ++--
On 13/6/24 17:44, Daniel P. Berrangé wrote:
This variable was used to support back compat for the old config
file key name, and became redundant after the following change:
commit a7a2d636ae4549ef0551134d4bf8e084a14431c4
Author: Philippe Mathieu-Daudé
Date: Thu May 30 08:36:43 2024 +
On 13/6/24 17:44, Daniel P. Berrangé wrote:
Allowing the user to set the QGA_CONF environment variable to change
the default configuration file path is very unusual practice, made
more obscure since this ability is not documented.
This introduces the more normal '-c PATH' / '--config=PATH' comm
On 13/6/24 17:01, Daniel P. Berrangé wrote:
The qmp_guest_set_vcpus and qmp_guest_get_vcpus command impls in
commands-posix.c are surrounded by '#ifdef __linux__' so should
instead live in commands-linux.c
Reviewed-by: Manos Pitsidianakis
Signed-off-by: Daniel P. Berrangé
---
qga/commands-li
On 13/6/24 17:01, Daniel P. Berrangé wrote:
The qmp_guest_suspend_{disk,ram,hybrid} command impls in
commands-posix.c are surrounded by '#ifdef __linux__' so should
instead live in commands-linux.c
Reviewed-by: Manos Pitsidianakis
Signed-off-by: Daniel P. Berrangé
---
qga/commands-linux.c |
On 13/6/24 17:01, Daniel P. Berrangé wrote:
The qmp_guest_{fstrim, get_fsinfo, get_disks} command impls in
commands-posix.c are surrounded by '#ifdef __linux__' so should
instead live in commands-linux.c
Reviewed-by: Manos Pitsidianakis
Signed-off-by: Daniel P. Berrangé
---
qga/commands-linu
On 2024/6/28 2:03, Richard Henderson wrote:
Move detection code out of tcg, similar to other hosts.
Signed-off-by: Richard Henderson
Reviewed-by: LIU Zhiwei
Zhiwei
---
host/include/riscv/host/cpuinfo.h | 23 +
tcg/riscv/tcg-target.h| 46 -
util/cpu
Recent SDHCI expect cards to support the v3.01 spec
to negociate lower I/O voltage. Select it by default.
Versioned machine types with a version of 9.0 or
earlier retain the old default (spec v2.00).
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Cédric Le Goater
---
v43: update versioned m
(patches from v42 already reviewed not reposted)
- Addressed review comments from Daniel & Luc wrt migration
- Remove old comment
Philippe Mathieu-Daudé (3):
hw/sd/sdcard: Use spec v3.01 by default
hw/sd/sdcard: Do not store vendor data on block drive (CMD56)
hw/sd/sdcard: Remove leftover c
Commit c3287c0f70 ("hw/sd: Introduce a "sd-card" SPI variant
model") removed the 'spi' property. Remove the comment left
over.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sd.c | 4
1 file changed, 4 deletions(-)
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index 000b923c73..904da440ba 100644
-
"General command" (GEN_CMD, CMD56) is described as:
GEN_CMD is the same as the single block read or write
commands (CMD24 or CMD17). The difference is that [...]
the data block is not a memory payload data but has a
vendor specific format and meaning.
Thus this block must not be stored ov
Jonathan Cameron writes:
> On Fri, 28 Jun 2024 06:09:23 +
> "Ho-Ren (Jack) Chuang" wrote:
[snip]
>> @@ -875,8 +886,7 @@ static int __meminit memtier_hotplug_callback(struct
>> notifier_block *self,
>>
>> static int __init memory_tier_init(void)
>> {
>> -int ret, node;
>> -stru
The function ufs_is_mcq_reg() only evaluated the range of the
mcq_op_reg offset, which is defined as a constant.
Therefore, it was possible for ufs_is_mcq_reg() to return true
despite ufs device is configured to not support the mcq.
This could cause ufs_mmio_read()/ufs_mmio_write() to overflow the
On 3/7/24 10:51, Philippe Mathieu-Daudé wrote:
"General command" (GEN_CMD, CMD56) is described as:
GEN_CMD is the same as the single block read or write
commands (CMD24 or CMD17). The difference is that [...]
the data block is not a memory payload data but has a
vendor specific forma
Commit c3287c0f70 ("hw/sd: Introduce a "sd-card" SPI variant
model") removed the 'spi' property. Remove the comment left
over.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sd.c | 4
1 file changed, 4 deletions(-)
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index b158402704..53767beaf8 100644
-
Recent SDHCI expect cards to support the v3.01 spec
to negociate lower I/O voltage. Select it by default.
Versioned machine types with a version of 9.0 or
earlier retain the old default (spec v2.00).
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Cédric Le Goater
---
v43: update versioned m
"General command" (GEN_CMD, CMD56) is described as:
GEN_CMD is the same as the single block read or write
commands (CMD24 or CMD17). The difference is that [...]
the data block is not a memory payload data but has a
vendor specific format and meaning.
Thus this block must not be stored ov
(patches from v42 already reviewed not reposted)
- Addressed review comments from Daniel & Luc wrt migration
- Remove old comment
Philippe Mathieu-Daudé (3):
hw/sd/sdcard: Remove leftover comment about removed 'spi' Property
hw/sd/sdcard: Use spec v3.01 by default
hw/sd/sdcard: Do not store
On 6/24/24 10:52, Michal Privoznik wrote:
> I've noticed that recent QEMU + libvirt (current HEADs, roughly) behave
> a bit different than expected. The problem is in recent change to
> 'query-sev-capabilities' command (well, sev_get_capabilities() in fact)
> which libvirt uses (see patch 2/2). The
"make check SPEED=slow" is currently failing the device-introspect-test on
older machine types since introspecting "scsi-block" is causing an abort:
$ ./qemu-system-x86_64 -M pc-q35-8.0 -monitor stdio
QEMU 9.0.50 monitor - type 'help' for more information
(qemu) device_add scsi-block,help
Unex
On 7/3/24 10:16 AM, Jamin Lin wrote:
According to the datasheet of ASPEED SOCs,
one MAC controller owns 128KB of register space for AST2500.
However, one MAC controller only owns 64KB of register space for AST2600
and AST2700.
It set the memory region size 128KB and it occupied another
controll
On 7/3/24 10:16 AM, Jamin Lin wrote:
According to the w25q01jv datasheet at page 16,
it is required to set QE bit in "Status Register 2".
Besides, users are able to utilize "Write Status Register 1(0x01)"
command to set QE bit in "Status Register 2" and
utilize "Read Status Register 2(0x35)" comm
On 7/3/24 10:16 AM, Jamin Lin wrote:
Update a test case to test network connection via ssh and
changes to test Aspeed OpenBMC SDK v09.02 for AST2700.
ASPEED fixed TX mask issue from linux/drivers/ftgmac100.c.
It is required to use ASPEED SDK image since v09.02
for AST2700 QEMU network testing.
Add all of the defined protocols/features from the PCIe-SIG r6.0
"Table 6-32 PCI-SIG defined Data Object Types (Vendor ID = 0001h)"
table.
Signed-off-by: Alistair Francis
Reviewed-by: Jonathan Cameron
Reviewed-by: Wilfred Mallawa
---
include/hw/pci/pcie_doe.h | 2 ++
1 file changed, 2 insertio
From: Huai-Cheng Kuo
SPDM enables authentication, attestation and key exchange to assist in
providing infrastructure security enablement. It's a standard published
by the DMTF [1].
SPDM supports multiple transports, including PCIe DOE and MCTP.
This patch adds support to QEMU to connect to an ex
From: Wilfred Mallawa
Setup Data Object Exchange (DOE) as an extended capability for the NVME
controller and connect SPDM to it (CMA) to it.
Signed-off-by: Wilfred Mallawa
Signed-off-by: Alistair Francis
Reviewed-by: Jonathan Cameron
Acked-by: Klaus Jensen
---
docs/specs/index.rst|
The Security Protocol and Data Model (SPDM) Specification defines
messages, data objects, and sequences for performing message exchanges
over a variety of transport and physical media.
-
https://www.dmtf.org/sites/default/files/standards/documents/DSP0274_1.3.0.pdf
SPDM currently supports PCIe D
> -Original Message-
> From: Cédric Le Goater
> Sent: Wednesday, July 3, 2024 5:18 PM
> To: Jamin Lin ; Peter Maydell
> ; Steven Lee ; Troy
> Lee ; Andrew Jeffery ;
> Joel Stanley ; Alistair Francis ;
> Kevin
> Wolf ; Hanna Reitz ; Jason Wang
> ; Cleber Rosa ; Philippe
> Mathieu-Daudé ; W
Hi Cedric,
> Subject: Re: [PATCH v2 1/5] hw/net:ftgmac100: update memory region size to
> 0x200
>
> On 7/3/24 10:16 AM, Jamin Lin wrote:
> > According to the datasheet of ASPEED SOCs, one MAC controller owns
> > 128KB of register space for AST2500.
> >
> > However, one MAC controller only owns 64
On 3/7/24 11:09, Thomas Huth wrote:
"make check SPEED=slow" is currently failing the device-introspect-test on
older machine types since introspecting "scsi-block" is causing an abort:
$ ./qemu-system-x86_64 -M pc-q35-8.0 -monitor stdio
QEMU 9.0.50 monitor - type 'help' for more information
On Wed, Jul 3, 2024 at 5:09 PM Thomas Huth wrote:
> "make check SPEED=slow" is currently failing the device-introspect-test on
> older machine types since introspecting "scsi-block" is causing an abort:
>
> $ ./qemu-system-x86_64 -M pc-q35-8.0 -monitor stdio
> QEMU 9.0.50 monitor - type 'help'
On Wed, Jul 3, 2024 at 3:51 PM Jiaxun Yang wrote:
>
>
>
> 在2024年7月1日七月 下午2:57，Jiaxun Yang写道：
> > 在2024年5月30日五月 上午7:49，Bibo Mao写道：
> >> Loongson Binary Translation (LBT) is used to accelerate binary
> >> translation, which contains 4 scratch registers (scr0 to scr3), x86/ARM
> >> eflags (eflags) an
Next patch will add Accel globals support and will use
qdev_prop_set_globals().
At this moment this function is hardwired to be used with DeviceState.
dev->hotplugged is checked to determine if object_apply_global_props()
will receive a NULL or an &error_fatal errp.
Change qdev_prop_set_globals()
Hi,
This is another approach of the problem we tried to fix with [1]. It was
suggested by Paolo during the review.
In the current handling of '-accel' only the first instance is parsed.
All other instances (aside from a 'helper' command that triggers the
help text and exits) is ignored. So this c
We're not honouring KVM options that are provided by any -accel option
aside from the first. In this example:
qemu-system-riscv64 -accel kvm,riscv-aia=emul (...) \
-accel kvm,riscv-aia=hwaccel
'riscv-aia' will be set to 'emul', ignoring the last occurrence of the
option that set 'riscv-aia' t
John Snow writes:
> New bleeding edge versions, new nits to iron out. This addresses the
> 'check-python-tox' optional GitLab test, while 'check-python-minreqs'
> saw no regressions, since it's frozen on an older version of pylint.
>
> Fixes:
> qemu/machine/machine.py:345:52: E0606: Possibly usin
John Snow writes:
> There is a bug in this version,
> see: https://github.com/pylint-dev/pylint/issues/9751
>
> Signed-off-by: John Snow
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
Commit 8f9a9259d32c added ObjectType member @x-vfio-user-server with
feature unstable, but neglected to explain why it is unstable. Do
that now.
Fixes: 8f9a9259d32c (vfio-user: define vfio-user-server object)
Cc: Elena Ufimtseva
Cc: John G Johnson
Cc: Jagannathan Raman
Cc: qemu-sta...@nongnu.o
On 2024/7/3 下午5:43, Huacai Chen wrote:
On Wed, Jul 3, 2024 at 3:51 PM Jiaxun Yang wrote:
在2024年7月1日七月 下午2:57，Jiaxun Yang写道：
在2024年5月30日五月 上午7:49，Bibo Mao写道：
Loongson Binary Translation (LBT) is used to accelerate binary
translation, which contains 4 scratch registers (scr0 to scr3), x86
On 2/7/24 22:05, Philippe Mathieu-Daudé wrote:
On 2/7/24 18:21, Cédric Le Goater wrote:
On 7/2/24 6:15 PM, Philippe Mathieu-Daudé wrote:
On 2/7/24 07:06, Andrew Jeffery wrote:
On Fri, 2024-06-28 at 11:16 +0200, Cédric Le Goater wrote:
On 6/28/24 9:02 AM, Philippe Mathieu-Daudé wrote:
When bo
在2024年7月3日七月 下午6:10，maobibo写道：
[...]
>>>
>>> Huacai, would you agree with me?
>> For me the important thing is consistency, all vm-features or all
>> vcpu-features are both accepted.
> To understand features immediately is difficult job for me. There is
> supported features/used features usages
Hello Daniel,
This cleanup seems like a good idea,
On Thu, 13 Jun 2024 18:44, "Daniel P. Berrangé" wrote:
It is confusing having many different pieces of code enabling and
disabling commands, and it is not clear that they all have the same
semantics, especially wrt prioritization of the block/
On Tue, Jul 02, 2024 at 03:02:36PM +0100, Jonathan Cameron wrote:
> On Mon, 1 Jul 2024 17:03:43 -0400
> "Michael S. Tsirkin" wrote:
>
> > On Thu, Jun 27, 2024 at 02:18:03PM +0200, Igor Mammedov wrote:
> > > On Tue, 25 Jun 2024 20:38:39 +0530
> > > Sunil V L wrote:
> > >
> > > > As per the ste
On Thu, 13 Jun 2024 18:44, "Daniel P. Berrangé" wrote:
The fsfreeze commands are already written to report an error if
vss_init() fails. Reporting a more specific error message is more
helpful than a generic "command is disabled" message, which cannot
beteween an admin config decision and lack o
John Snow writes:
> Python 3.13 is in beta and Fedora 41 is preparing to make it the default
> system interpreter; enable testing for it.
>
> (In the event problems develop prior to release, it should only impact
> the check-python-tox job, which is not run by default and is allowed to
> fail.)
>
Fixes: 70943ad8e4d ("i386/sev: Add support for SNP CPUID validation",
2024-06-05)
Signed-off-by: Paolo Bonzini
---
target/i386/sev.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/i386/sev.c b/target/i386/sev.c
index 3ab8b3c28b7..2a0f94d390d 100644
--- a/target/
Commit d7c72735f61 ("target/i386: Add new EPYC CPU versions with updated
cache_info", 2023-05-08) ensured that AMD-defined CPU models did not
have the 'complex_indexing' bit set, but left it set in "-cpu host"
which uses the default ("legacy") cache information.
Reimplement that commit using a CPU
On Wed, 3 Jul 2024, Michael S. Tsirkin wrote:
On Wed, Jul 03, 2024 at 04:15:23AM +0200, BALATON Zoltan wrote:
On Tue, 2 Jul 2024, Michael S. Tsirkin wrote:
On Thu, Jun 27, 2024 at 03:08:00PM +0900, Akihiko Odaki wrote:
rom_bar is tristate but was defined as uint32_t so convert it into
OnOffAut
Some CPUID features may be provided by KVM for some guests, independent of
processor support, for example TSC deadline or TSC adjust. If these are
not supported by the confidential computing firmware, however, the guest
will fail to start. Add support for removing unsupported features from
"-cpu
Some CPUID features may be provided by KVM for some guests, independent of
processor support, for example TSC deadline or TSC adjust. They are not going
to be present in named models unless the vendor implements them in hardware,
but they will be present in "-cpu host".
If these bits are not supp
SNP firmware rejects several features that KVM implements without needing
hardware support. If these are specified, for example with "-cpu host",
the guest will fail to start.
I am marking this as RFC because it's not future proof. If in the future
AMD processors do provide any of these bits, th
On Wed, Jul 03, 2024 at 06:46:25AM -0300, Daniel Henrique Barboza wrote:
> Next patch will add Accel globals support and will use
> qdev_prop_set_globals().
>
> At this moment this function is hardwired to be used with DeviceState.
> dev->hotplugged is checked to determine if object_apply_global_p
The class function and implementations for updating launch data return
a code in case of error. In some cases an error message is generated and
in other cases, just the error return value is used.
This small refactor adds an 'Error **errp' parameter to all functions
which consistently set an error
Here is v4 of the set of patches to add support for IGVM files to QEMU. This is
based on commit 1a2d52c7fc of qemu.
This version addresses all of the review comments from v3 along with a couple of
small bug fixes. This is a much smaller increment than in the previous version
of the series [1]. Tha
When an SEV guest is started, the reset vector and state are
extracted from metadata that is contained in the firmware volume.
In preparation for using IGVM to setup the initial CPU state,
the code has been refactored to populate vmcb_save_area for each
CPU which is then applied during guest start
IGVM files can contain an initial VMSA that should be applied to each
vcpu as part of the initial guest state. The sev_features flags are
provided as part of the VMSA structure. However, KVM only allows
sev_features to be set during initialization and not as the guest is
being prepared for launch.
Adds a handler for the guest policy initialization IGVM section and
builds an SEV policy based on this information and the ID block
directive if present. The policy is applied using by calling
'set_guest_policy()' on the ConfidentialGuestSupport object.
Signed-off-by: Roy Hopkins
---
backends/ig
IGVM support has been implemented for Confidential Guests that support
AMD SEV and AMD SEV-ES. Add some documentation that gives some
background on the IGVM format and how to use it to configure a
confidential guest.
Signed-off-by: Roy Hopkins
---
docs/system/i386/amd-memory-encryption.rst | 2
Create an enum entry within FirmwareDevice for 'igvm' to describe that
an IGVM file can be used to map firmware into memory as an alternative
to pre-existing firmware devices.
Signed-off-by: Roy Hopkins
---
docs/interop/firmware.json | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
In preparation for supporting the processing of IGVM files to configure
guests, this adds a set of functions to ConfidentialGuestSupport
allowing configuration of secure virtual machines that can be
implemented for each supported isolation platform type such as Intel TDX
or AMD SEV-SNP. These funct
For confidential guests a policy can be provided that defines the
security level, debug status, expected launch measurement and other
parameters that define the configuration of the confidential platform.
This commit adds a new function named set_guest_policy() that can be
implemented by each conf
The new cgs_set_guest_policy() function is provided to receive the guest
policy flags, SNP ID block and SNP ID authentication from guest
configuration such as an IGVM file and apply it to the platform prior to
launching the guest.
The policy is used to populate values for the existing 'policy',
'i
The initialization sections in IGVM files contain configuration that
should be applied to the guest platform before it is started. This
includes guest policy and other information that can affect the security
level and the startup measurement of a guest.
This commit introduces handling of the init
The x86 segment registers are identified by the X86Seg enumeration which
includes LDTR and TR as well as the normal segment registers. The
function 'cpu_x86_load_seg_cache()' uses the enum to determine which
segment to set. However, specifying R_LDTR or R_TR results in an
out-of-bounds access of th
The ConfidentialGuestSupport object defines a number of virtual
functions that are called during processing of IGVM directives to query
or configure initial guest state. In order to support processing of IGVM
files, these functions need to be implemented by relevant isolation
hardware support code
1 - 100 of 392 matches
Mail list logo
