Re: [PATCH v2 00/12] hw/sd/sdcard: Accumulation of cleanups and fixes

On 6/25/24 7:53 AM, Philippe Mathieu-Daudé wrote: Since v1: - various patches merged, few more added Various SD card cleanups and fixes accumulated over the years. Various have been useful to help integrating eMMC support (which will come later). Philippe Mathieu-Daudé (12): tests/qtest: Dis

[PATCH v3 0/2] Fix coverity issues for AST2700

change from v1: aspeed/soc: coverity defect: DIVIDE_BY_ZERO aspeed/sdmc: coverity defect: Control flow issues (DEADCODE) change from v2: add more commit log from reviewer suggestion, Cédric. change from v3: replace qemu_log_mask with assert dram size 0. Jamin Lin (2): aspeed/soc: Fix possible

[PATCH v3 1/2] aspeed/soc: Fix possible divide by zero

Coverity reports a possible DIVIDE_BY_ZERO issue regarding the "ram_size" object property. This can not happen because RAM has predefined valid sizes per SoC. Nevertheless, add a test to close the issue. Fixes: Coverity CID 1547113 Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater [ clg: Re

[PATCH v3 2/2] aspeed/sdmc: Remove extra R_MAIN_STATUS case

Coverity reports that the newly added 'case R_MAIN_STATUS' is DEADCODE because it can not be reached. This is because R_MAIN_STATUS is handled before in the "Unprotected registers" switch statement. Remove it. Fixes: Coverity CID 1547112 Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater [ c

[PATCH v2] aspeed: Deprecate the tacoma-bmc machine

The tacoma-bmc machine was a board including an AST2600 SoC based BMC and a witherspoon like OpenPOWER system. It was used for bring up of the AST2600 SoC in labs. It can be easily replaced by the rainier-bmc machine which is part of a real product offering. Signed-off-by: Cédric Le Goater ---

Re: Help improve 32-bit testing

On 25/06/2024 01.33, Richard Henderson wrote: Hiya, I've just discovered a 32-bit build issue that is probably 3 weeks old. While we still support 32-bit builds at all, I would request that we improve our cross-i686 testing.  For instance: we have cross-i686-user and cross-i686-tci.  There is

Re: [PATCH v2] aspeed: Deprecate the tacoma-bmc machine

On 25/6/24 09:08, Cédric Le Goater wrote: The tacoma-bmc machine was a board including an AST2600 SoC based BMC and a witherspoon like OpenPOWER system. It was used for bring up of the AST2600 SoC in labs. It can be easily replaced by the rainier-bmc machine which is part of a real product offeri

Re: [PATCH 1/2] qom: Rename Object::class into Object::klass

On Mon, Jun 24, 2024 at 08:43:59PM +, Felix Wu wrote: > From: Roman Kiryanov > > 'class' is a C++ keyword and it prevents from > using the QEMU headers with a C++ compiler. > > Google-Bug-Id: 331190993 > Change-Id: I9ab7d2d77edef654a9c7b7cb9cd01795a6ed65a2 Please remove both of these lines

Re: [Bug Report] Possible Missing Endianness Conversion

On Mon, Jun 24, 2024 at 04:19:52PM GMT, Peter Maydell wrote: On Mon, 24 Jun 2024 at 16:11, Stefano Garzarella wrote: CCing Jason. On Mon, Jun 24, 2024 at 4:30 PM Xoykie wrote: > > The virtio packed virtqueue support patch[1] suggests converting > endianness by lines: > > virtio_tswap16s(vdev

Re: [PATCH v1] memory tier: consolidate the initialization of memory tiers

June 24, 2024 at 1:27 AM, "Huang, Ying" wrote: Hi Huang, Ying, Thanks for your feedback. Replies inlined. > > Hi, Jack, > > Thanks for patch! > > "Ho-Ren (Jack) Chuang" writes: > > > > > If we simply move the set_node_memory_tier() from memory_tier_init() to > > > > late_initcall(), it

Re: [PATCH v3 0/2] Fix coverity issues for AST2700

Hello Jamin On 6/25/24 9:07 AM, Jamin Lin wrote: change from v1: aspeed/soc: coverity defect: DIVIDE_BY_ZERO aspeed/sdmc: coverity defect: Control flow issues (DEADCODE) change from v2: add more commit log from reviewer suggestion, Cédric. change from v3: replace qemu_log_mask with assert dram

RE: [PATCH] aspeed/sdmc: Check RAM size value at realize time

> -Original Message- > From: Cédric Le Goater > Sent: Tuesday, June 25, 2024 2:59 PM > To: qemu-...@nongnu.org; qemu-devel@nongnu.org > Cc: Peter Maydell ; Joel Stanley ; > Andrew Jeffery ; Jamin Lin > ; Cédric Le Goater > Subject: [PATCH] aspeed/sdmc: Check RAM size value at realize time

RE: [PATCH v3 0/2] Fix coverity issues for AST2700

Hi Cedric, > -Original Message- > From: Cédric Le Goater > Sent: Tuesday, June 25, 2024 3:22 PM > To: Jamin Lin ; Peter Maydell > ; Steven Lee ; Troy > Lee ; Andrew Jeffery ; > Joel Stanley ; open list:ASPEED BMCs > ; open list:All patches CC here > > Subject: Re: [PATCH v3 0/2] Fix cov

[PATCH 0/7] hw/sd/sd: Introduce sd_cmd_to_receivingdata() / sd_generic_write_byte()

Consolitate writing bytes on the DAT lines by introducing a pair of helpers to reuse in all commands receiving data. Based-on: <20240625061015.24095-1-phi...@linaro.org> Philippe Mathieu-Daudé (7): hw/sd/sdcard: Introduce sd_cmd_to_receivingdata / sd_generic_write_byte hw/sd/sdcard: Dupli

[PATCH 6/7] hw/sd/sdcard: Convert LOCK_UNLOCK to generic_write_byte (CMD42)

Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sd.c | 15 ++- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index b0f29034c0..82b44b65e0 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -1604,17 +1604,7 @@ static sd_rsp_type_t sd_normal_command(SDS

[PATCH 2/7] hw/sd/sdcard: Duplicate WRITE_SINGLE_BLOCK / WRITE_MULTIPLE_BLOCK cases

In order to modify the WRITE_SINGLE_BLOCK case in the next commit, duplicate it first. Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sd.c | 29 + 1 file changed, 29 insertions(+) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 7fea0afb62..8c30826754 100644 --- a/hw/sd/s

[PATCH 7/7] hw/sd/sdcard: Convert GEN_CMD to generic_write_byte (CMD56)

Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sd.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 82b44b65e0..fe2210d65a 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -1633,14 +1633,12 @@ static sd_rsp_type_t sd_normal_command(SDState *s

[PATCH 4/7] hw/sd/sdcard: Convert PROGRAM_CID to generic_write_byte (CMD26)

Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sd.c | 15 ++- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index fff4be3ae2..9db3b32b0b 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -1491,17 +1491,7 @@ static sd_rsp_type_t sd_normal_command(SDS

[PATCH 1/7] hw/sd/sdcard: Introduce sd_cmd_to_receivingdata / sd_generic_write_byte

All commands switching from TRANSFER state to (receiving)DATA do the same: receive stream of data from the DAT lines. Instead of duplicating the same code many times, introduce 2 helpers: - sd_cmd_to_receivingdata() on the I/O line setup the data to be received on the data[] buffer, - sd_generic_

[PATCH 5/7] hw/sd/sdcard: Convert PROGRAM_CSD to generic_write_byte (CMD27)

Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sd.c | 15 ++- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 9db3b32b0b..b0f29034c0 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -1494,17 +1494,7 @@ static sd_rsp_type_t sd_normal_command(SDS

[PATCH 3/7] hw/sd/sdcard: Convert WRITE_SINGLE_BLOCK to generic_write_byte (CMD24)

Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sd.c | 11 ++- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 8c30826754..fff4be3ae2 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -1081,7 +1081,6 @@ static sd_rsp_type_t sd_cmd_unimplemented(SDStat

Re: Help improve 32-bit testing

On Mon, Jun 24, 2024 at 04:33:08PM -0700, Richard Henderson wrote: > Hiya, > > I've just discovered a 32-bit build issue that is probably 3 weeks old. > > While we still support 32-bit builds at all, I would request that we improve > our cross-i686 testing. For instance: we have cross-i686-user

Re: How to use designware-root-port and designware-root-host devices ?

Hi, I ported DWC PCIE part from fsl-imx7.c to my new cusotm virt machine based on RISC-V "virt". It looks ok so far. Now i'm wondering whether there is a "standard/ready to use for most of cases" device tree description for the synopsis pcie host device ? Looking this way: https://mjmwired.net/k

Re: [PATCH 1/1] include/qemu: Provide a C++ compatible version of typeof_strip_qual

On Mon, Jun 24, 2024 at 08:56:47PM +, Felix Wu wrote: > From: Roman Kiryanov > > to use the QEMU headers with a C++ compiler. > > Signed-off-by: Felix Wu > Signed-off-by: Roman Kiryanov > --- > include/qemu/atomic.h | 8 > include/qemu/atomic.hpp | 38 +

Re: Help improve 32-bit testing

Hi Richard, On 25/6/24 01:33, Richard Henderson wrote: Hiya, I've just discovered a 32-bit build issue that is probably 3 weeks old. How and what did you notice? While we still support 32-bit builds at all, I would request that we improve our cross-i686 testing.  For instance: we have cross

Re: [PATCH v2 1/6] target/riscv: Remove obsolete sfence.vm instruction

Reviewed-by: Jason Chien On 2024/6/19 下午 11:27, Rajnesh Kanwal wrote: Signed-off-by: Rajnesh Kanwal Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 1 - target/riscv/insn_trans/trans_privileged.c.inc | 5 - 2 files changed, 6 deletions(-) diff --git

Re: [PATCH] qapi/qom: make some QOM properties depend on the build settings

Gentle ping :-) On Tue, Jun 04, 2024 at 03:59:31PM GMT, Stefano Garzarella wrote: Some QOM properties are associated with ObjectTypes that already depend on CONFIG_* switches. So to avoid generating dead code, let's also make the definition of those properties dependent on the corresponding CONF

Re: [PATCH v2 3/6] target/riscv: Add support for Control Transfer Records extension CSRs.

Hi Rajnesh, On 2024/6/19 下午 11:27, Rajnesh Kanwal wrote: This commit adds support for [m|s|vs]ctrcontrol, sctrstatus and sctrdepth CSRs handling. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.h | 5 ++ target/riscv/cpu_cfg.h | 2 + target/riscv/csr.c | 128

Re: [PATCH v3 02/15] uefi-test-tools: Add support for python based build script

On Fri, 21 Jun 2024 17:28:53 +0530 Sunil V L wrote: > edk2-funcs.sh which is used in this Makefile, was removed in the commit > c28a2891f3 ("edk2: update build script"). It is replaced with a python > based script. So, update the Makefile and add the configuration file as > required to support th

Re: [PATCH v3 01/15] uefi-test-tools/UefiTestToolsPkg: Add RISC-V support

On Fri, 21 Jun 2024 17:28:52 +0530 Sunil V L wrote: > Enable building the test application for RISC-V with appropriate > dependencies updated. > > Signed-off-by: Sunil V L > Acked-by: Gerd Hoffmann > Acked-by: Alistair Francis Acked-by: Igor Mammedov > --- > tests/uefi-test-tools/UefiTest

Re: [PATCH v1] memory tier: consolidate the initialization of memory tiers

"Ho-Ren Chuang" writes: > June 24, 2024 at 1:27 AM, "Huang, Ying" wrote: > > Hi Huang, Ying, > > Thanks for your feedback. Replies inlined. > >> >> Hi, Jack, >> >> Thanks for patch! >> >> "Ho-Ren (Jack) Chuang" writes: >> >> > >> > If we simply move the set_node_memory_tier() from memory_

Re: [PATCH v2 5/6] target/riscv: Add CTR sctrclr instruction.

Hi Rajnesh, On 2024/6/19 下午 11:27, Rajnesh Kanwal wrote: CTR extension adds a new instruction sctrclr to quickly clear the recorded entries buffer. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.h| 1 + target/riscv/cpu_helper.c | 7

[PATCH 0/4] Add support for Zhaoxin Yongfeng CPU model and other improvements

This patch series introduces support for the Zhaoxin Yongfeng CPU model and includes some improvements and updates related to Zhaoxin and VIA CPUs. The changes ensure that QEMU can correctly identify and emulate Zhaoxin CPUs, providing accurate functionality and performance characteristics. ###

[PATCH 3/4] target/i386: Introduce Zhaoxin Yongfeng CPU model

Introduce support for the Zhaoxin Yongfeng CPU model. The Zhaoxin Yongfeng CPU is Zhaoxin's latest server CPU. This new cpu model ensure that QEMU can correctly emulate the Zhaoxin Yongfeng CPU, providing accurate functionality and performance characteristics. Signed-off-by: EwanHai --- target/

[PATCH 2/4] target/i386: Add CPUID leaf 0xC000_0001 EDX definitions

Add new CPUID feature flags for various VIA PadLock extensions. These definitions will be used for ZHAOXIN/VIA CPU models. Signed-off-by: EwanHai --- target/i386/cpu.h | 21 + 1 file changed, 21 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 365373652

[PATCH 1/4] target/i386: Add support for Zhaoxin/VIA CPU vendor identification

This patch adds CPUID vendor strings and macros to identify Zhaoxin/VIA CPUs. Changes: - Added Zhaoxin/VIA CPUID vendor strings. - Defined CPUID_VENDOR_ZHAOXIN. - Added IS_ZHAOXIN_CPU/IS_VIA_CPU macro. Signed-off-by: EwanHai --- target/i386/cpu.h | 17 + 1 file changed, 17 inser

[PATCH 4/4] target/i386: Update CMPLegacy handling for Zhaoxin and VIA CPUs

Zhaoxin and VIA CPUs handle the CMPLegacy bit in the same way as Intel CPUs. This patch simplifies the existing logic by using the IS_XXX_CPU macro and includes checks for Zhaoxin and VIA vendors to align their behavior with Intel. Signed-off-by: EwanHai --- target/i386/cpu.c | 6 +++--- 1 file

Re: [PATCH 1/2] qom: Rename Object::class into Object::klass

On Tue, 25 Jun 2024 at 03:20, Philippe Mathieu-Daudé wrote: > Since you are posting different C++ enablement cleanups, > I suggest you add a section in our docs/devel/style.rst > requesting to keep headers C++ compatible, by not using > C++ reserved keywords, etc... > > In particular because the m

Re: [PATCH 1/1] include/qemu: Provide a C++ compatible version of typeof_strip_qual

On Tue, 25 Jun 2024 at 07:19, Philippe Mathieu-Daudé wrote: > > On 25/6/24 08:05, Paolo Bonzini wrote: > > > > > > Il mar 25 giu 2024, 04:32 Roman Kiryanov > > ha scritto: > > > > Hi Philippe, thank you for looking. > > > > On Mon, Jun 24, 2024 at 7:27 PM Philippe

Re: [PATCH v3] target/i386/kvm: Refine VMX controls setting for backward compatibility

On Mon, Jun 24, 2024 at 05:58:06AM -0400, EwanHai wrote: > Date: Mon, 24 Jun 2024 05:58:06 -0400 > From: EwanHai > Subject: [PATCH v3] target/i386/kvm: Refine VMX controls setting for > backward compatibility > X-Mailer: git-send-email 2.34.1 > > Commit 4a910e1 ("target/i386: do not set unsuppor

Re: [PATCH 1/2] qom: Rename Object::class into Object::klass

On Tue, Jun 25, 2024 at 10:23:54AM +0100, Peter Maydell wrote: > On Tue, 25 Jun 2024 at 03:20, Philippe Mathieu-Daudé > wrote: > > Since you are posting different C++ enablement cleanups, > > I suggest you add a section in our docs/devel/style.rst > > requesting to keep headers C++ compatible, by

[PATCH v4] virtio-net: Notify the guest with the latest available idx

From: thomas Patch 06b12970174 ("virtio-net: fix network stall under load") added double-check to test whether the available buffer size can satisfy the request or not, in case the guest has added some buffers to the avail ring simultaneously after the first check. It will be lucky if the availa

Re: [PATCH v2 6/6] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs.

Hi Rajnesh, On 2024/6/19 下午 11:27, Rajnesh Kanwal wrote: CTR entries are accessed using ctrsource, ctrtarget and ctrdata registers using smcsrind/sscsrind extension. This commits extends the csrind extension to support CTR registers. ctrsource is accessible through xireg CSR, ctrtarget is acces

Re: [PATCH] i386: revert defaults to 'legacy-vm-type=true' for SEV(-ES) guests

On Mon, Jun 24, 2024 at 08:19:19PM -0500, Michael Roth wrote: > On Fri, Jun 14, 2024 at 11:39:24AM +0100, Daniel P. Berrangé wrote: > > The KVM_SEV_INIT2 ioctl was only introduced in Linux 6.10, which will > > only have been released for a bit over a month when QEMU 9.1 is > > released. > > > > Th

Re: [PATCH 1/1] include/qemu: Provide a C++ compatible version of typeof_strip_qual

On Tue, 25 Jun 2024 at 10:27, Peter Maydell wrote: > > On Tue, 25 Jun 2024 at 07:19, Philippe Mathieu-Daudé > wrote: > > > > On 25/6/24 08:05, Paolo Bonzini wrote: > > > > > > > > > Il mar 25 giu 2024, 04:32 Roman Kiryanov > > > ha scritto: > > > > > > Hi Philippe, t

Re: [PATCH v4] virtio-net: Notify the guest with the latest available idx

On Tue, Jun 25, 2024 at 05:48:51PM +0800, Wencheng Yang wrote: > From: thomas > > Patch 06b12970174 ("virtio-net: fix network stall under load") > added double-check to test whether the available buffer size > can satisfy the request or not, in case the guest has added > some buffers to the avail

Re: [PATCH 1/1] include/qemu: Provide a C++ compatible version of typeof_strip_qual

On Tue, Jun 25, 2024 at 11:16:16AM +0100, Peter Maydell wrote: > On Tue, 25 Jun 2024 at 10:27, Peter Maydell wrote: > > > > On Tue, 25 Jun 2024 at 07:19, Philippe Mathieu-Daudé > > wrote: > > > > > > On 25/6/24 08:05, Paolo Bonzini wrote: > > > > > > > > > > > > Il mar 25 giu 2024, 04:32 Roman K

Re: [PATCH v3 06/15] tests/qtest/bios-tables-test.c: Set "arch" for aarch64 tests

On Fri, 21 Jun 2024 17:28:57 +0530 Sunil V L wrote: > To search for expected AML files under ${arch}/${machine} path, set this > field for AARCH64 related test cases. > > Signed-off-by: Sunil V L Reviewed-by: Igor Mammedov > --- > tests/qtest/bios-tables-test.c | 8 > 1 file change

Re: [PATCH v3 05/15] tests/qtest/bios-tables-test.c: Add support for arch in path

On Fri, 21 Jun 2024 17:28:56 +0530 Sunil V L wrote: > Since machine name can be common for multiple architectures (ex: virt), > add "arch" in the path to search for expected AML files. Since the AML > files are still under old path, add support for searching with and > without arch in the path. >

Re: [PATCH v3 07/15] tests/qtest/bios-tables-test.c: Set "arch" for x86 tests

On Fri, 21 Jun 2024 17:28:58 +0530 Sunil V L wrote: > To search for expected AML files under ${arch}/${machine} path, set this > field for X86 related test cases. > > Signed-off-by: Sunil V L Reviewed-by: Igor Mammedov > --- > tests/qtest/bios-tables-test.c | 77

Re: [PATCH v3 09/15] tests/data/acpi/virt: Move ARM64 ACPI tables under aarch64/${machine} path

On Fri, 21 Jun 2024 17:29:00 +0530 Sunil V L wrote: > Same machine name can be used by different architectures. Hence, create > aarch64 folder and move all aarch64 related AML files for virt machine > inside. > > Signed-off-by: Sunil V L Reviewed-by: Igor Mammedov > --- > tests/data/acpi/{

Re: [PATCH v3 08/15] tests/data/acpi: Move x86 ACPI tables under x86/${machine} path

On Fri, 21 Jun 2024 17:28:59 +0530 Sunil V L wrote: > To support multiple architectures using same machine name, create x86 > folder and move all x86 related AML files for each machine type inside. > > Signed-off-by: Sunil V L Reviewed-by: Igor Mammedov > --- > tests/data/acpi/{ => x86}/mic

Re: [PATCH 1/2] migration: Implement dirty ring

Dear Peter Xu, Thank you for your feedback. > It looks like this patch will introduce a ring but still it keeps the > bitmaps around. > > Could you elaborate your motivation of this work? It’ll be interesting to > know whether you did any kind of measurement around it. First of all, I apologize

[PATCH] include: move typeof_strip_qual to compiler.h, use it in QAPI_LIST_LENGTH()

The typeof_strip_qual() is most useful for the atomic fetch-and-modify operations in atomic.h, but it can be used elsewhere as well. For example, QAPI_LIST_LENGTH() assumes that the argument is not const, which is not a requirement. Move the macro to compiler.h and, while at it, move it under #if

Re: [PATCH v3 14/15] tests/qtest/bios-tables-test.c: Enable basic testing for RISC-V

On Fri, 21 Jun 2024 17:29:05 +0530 Sunil V L wrote: > Add basic ACPI table test case for RISC-V. > > Signed-off-by: Sunil V L > Reviewed-by: Alistair Francis Reviewed-by: Igor Mammedov > --- > tests/qtest/bios-tables-test.c | 26 ++ > 1 file changed, 26 insertions(+

Re: [PATCH v2 1/2] copy-before-write: allow specifying minimum cluster size

On 28.05.24 15:01, Fiona Ebner wrote: In the context of backup fleecing, discarding the source will not work when the fleecing image has a larger granularity than the one used for block-copy operations (can happen if the backup target has smaller cluster size), because cbw_co_pdiscard_snapshot()

linux-user cannot allocate stack memory on riscv64 host due to non-zero guest_base

When running qemu-riscv64 on a riscv64 host executing a ET_EXEC riscv64 binary it cannot allocate memory for the stack: $ qemu-riscv64 -d page ./hello.riscv64 host mmap_min_addr=0x1 Locating guest address space @ 0x3ee000 page layout changed following mmap startend siz

Re: [PATCH v2 2/2] backup: add minimum cluster size to performance options

On 28.05.24 15:01, Fiona Ebner wrote: In the context of backup fleecing, discarding the source will not work when the fleecing image has a larger granularity than the one used for block-copy operations (can happen if the backup target has smaller cluster size), because cbw_co_pdiscard_snapshot()

Re: [PATCH RFC 2/2] migration: abort on destination if switchover limit exceeded

On 24/06/2024 20:41, Peter Xu wrote: > On Fri, Jun 21, 2024 at 07:32:21AM -0700, Elena Ufimtseva wrote: >> @@ -2659,6 +2698,18 @@ qemu_loadvm_section_start_full(QEMUFile *f, >> MigrationIncomingState *mis, >> if (!check_section_footer(f, se)) { >> return -EINVAL; >> @@ -2714,6 +2765

Re: [PATCH v2 1/2] copy-before-write: allow specifying minimum cluster size

On 28.05.24 15:01, Fiona Ebner wrote: +if (min_cluster_size > INT64_MAX) { +error_setg(errp, "min-cluster-size too large: %lu > %ld", + min_cluster_size, INT64_MAX); Better use PRIu64 and PRIi64 macros -- Best regards, Vladimir

Re: [PATCH 01/13] target/arm: Fix VCMLA Dd, Dn, Dm[idx]

On Tue, 25 Jun 2024 at 06:09, Richard Henderson wrote: > > The inner loop, bounded by eltspersegment, must not be > larger than the outer loop, bounded by elements. > > Cc: qemu-sta...@nongnu.org > Fixes: 18fc2405781 ("target/arm: Implement SVE fp complex multiply add > (indexed)") > Resolves: ht

Re: [PATCH 02/13] target/arm: Fix SQDMULH (by element) with Q=0

On Tue, 25 Jun 2024 at 06:09, Richard Henderson wrote: > > The inner loop, bounded by eltspersegment, must not be > larger than the outer loop, bounded by elements. > > Cc: qemu-sta...@nongnu.org > Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell thanks -- PMM

[PATCH v3 0/6] Introduce extension implied rules

From: Frank Chang Currently, the implied extensions are enabled and checked in riscv_cpu_validate_set_extensions(). However, the order of enabling the implied extensions must follow a strict sequence, which is error-prone. This patchset introduce extension implied rule helpers to enable the impl

[PATCH v3 1/6] target/riscv: Introduce extension implied rules definition

From: Frank Chang RISCVCPUImpliedExtsRule is created to store the implied rules. 'is_misa' flag is used to distinguish whether the rule is derived from the MISA or other extensions. 'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it stores the offset of the extension defined in RISCVCP

[PATCH v3 2/6] target/riscv: Introduce extension implied rule helpers

From: Frank Chang Introduce helpers to enable the extensions based on the implied rules. The implied extensions are enabled recursively, so we don't have to expand all of them manually. This also eliminates the old-fashioned ordering requirement. For example, Zvksg implies Zvks, Zvks implies Zvks

[PATCH v3 5/6] target/riscv: Add Zc extension implied rule

From: Frank Chang Zc extension has special implied rules that need to be handled separately. Signed-off-by: Frank Chang Reviewed-by: Jerry Zhang Jian Tested-by: Max Chou Reviewed-by: Daniel Henrique Barboza --- target/riscv/tcg/tcg-cpu.c | 34 ++ 1 file chang

[PATCH v3 6/6] target/riscv: Remove extension auto-update check statements

From: Frank Chang Remove the old-fashioned extension auto-update check statements as they are replaced by the extension implied rules. Signed-off-by: Frank Chang Reviewed-by: Jerry Zhang Jian Tested-by: Max Chou Reviewed-by: Daniel Henrique Barboza --- target/riscv/tcg/tcg-cpu.c | 119 -

[PATCH v3 4/6] target/riscv: Add multi extension implied rules

From: Frank Chang Add multi extension implied rules to enable the implied extensions of the multi extension recursively. Signed-off-by: Frank Chang Reviewed-by: Jerry Zhang Jian Tested-by: Max Chou Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 340

[PATCH v3 3/6] target/riscv: Add MISA extension implied rules

From: Frank Chang Add MISA extension implied rules to enable the implied extensions of MISA recursively. Signed-off-by: Frank Chang Reviewed-by: Jerry Zhang Jian Tested-by: Max Chou Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 50 +

Re: [PATCH 03/13] target/arm: Fix FJCVTZS vs flush-to-zero

On Tue, 25 Jun 2024 at 06:09, Richard Henderson wrote: > > Input denormals cause the Javascript inexact bit > (output to Z) to be set. > > Cc: qemu-sta...@nongnu.org > Fixes: 6c1f6f2733a ("target/arm: Implement ARMv8.3-JSConv") > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2375 > Signe

Re: [PATCH v3 14/15] tests/qtest/bios-tables-test.c: Enable basic testing for RISC-V

On Tue, 25 Jun 2024 13:19:59 +0200 Igor Mammedov wrote: > On Fri, 21 Jun 2024 17:29:05 +0530 > Sunil V L wrote: > > > Add basic ACPI table test case for RISC-V. > > > > Signed-off-by: Sunil V L > > Reviewed-by: Alistair Francis > > Reviewed-by: Igor Mammedov I take ack back for now, sin

[PATCH] hw/intc/ioapic: Delete a wrong IRQ redirection on I/O APIC

Before this commit, interruptions from i8254 which should be sent to IRQ0 were sent to IRQ2. After this commit, these are correctly sent to IRQ0. When I had an HPET timer generate interruptions once per second to test an HPET driver in my operating system on QEMU, I observed more frequent interrupt

[PATCH v5 2/3] vhost-user-blk: split vhost_user_blk_sync_config()

Split vhost_user_blk_sync_config() out from vhost_user_blk_handle_config_change(), to be reused in the following commit. Signed-off-by: Vladimir Sementsov-Ogievskiy --- hw/block/vhost-user-blk.c | 26 +++--- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/hw/bl

[PATCH v5 3/3] qapi: introduce device-sync-config

Add command to sync config from vhost-user backend to the device. It may be helpful when VHOST_USER_SLAVE_CONFIG_CHANGE_MSG failed or not triggered interrupt to the guest or just not available (not supported by vhost-user server). Command result is racy if allow it during migration. Let's allow th

[PATCH v5 0/3] vhost-user-blk: live resize additional APIs

v5: 03: drop extra check on is is runstate running Vladimir Sementsov-Ogievskiy (3): qdev-monitor: add option to report GenericError from find_device_state vhost-user-blk: split vhost_user_blk_sync_config() qapi: introduce device-sync-config hw/block/vhost-user-blk.c | 27 ++--

[PATCH v5 1/3] qdev-monitor: add option to report GenericError from find_device_state

Here we just prepare for the following patch, making possible to report GenericError as recommended. This patch doesn't aim to prevent further use of DeviceNotFound by future interfaces: - find_device_state() is used in blk_by_qdev_id() and qmp_get_blk() functions, which may lead to spread of

Re: [PATCH v3 14/15] tests/qtest/bios-tables-test.c: Enable basic testing for RISC-V

On Tue, Jun 25, 2024 at 02:05:58PM +0200, Igor Mammedov wrote: > On Tue, 25 Jun 2024 13:19:59 +0200 > Igor Mammedov wrote: > > > On Fri, 21 Jun 2024 17:29:05 +0530 > > Sunil V L wrote: > > > > > Add basic ACPI table test case for RISC-V. > > > > > > Signed-off-by: Sunil V L > > > Reviewed-by:

Re: [PATCH 12/13] target/arm: Convert FCMLA to decodetree

On Tue, 25 Jun 2024 at 06:09, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/a64.decode | 5 + > target/arm/tcg/translate-a64.c | 241 ++--- > 2 files changed, 76 insertions(+), 170 deletions(-) > > diff --git a/target/arm/

Re: [PATCH 06/13] target/arm: Convert SUDOT, USDOT to decodetree

On Tue, 25 Jun 2024 at 06:09, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/a64.decode | 3 +++ > target/arm/tcg/translate-a64.c | 35 -- > 2 files changed, 11 insertions(+), 27 deletions(-) Reviewed-by: Peter Maydell

Re: [PATCH 04/13] target/arm: Convert SQRDMLAH, SQRDMLSH to decodetree

On Tue, 25 Jun 2024 at 06:10, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/helper.h| 10 ++ > target/arm/tcg/a64.decode | 16 +++ > target/arm/tcg/translate-a64.c | 206 + > target/arm/tcg/vec_helper.c| 7

Re: [PATCH 08/13] target/arm: Convert BFMLALB, BFMLALT to decodetree

On Tue, 25 Jun 2024 at 06:10, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/a64.decode | 2 + > target/arm/tcg/translate-a64.c | 77 +- > 2 files changed, 31 insertions(+), 48 deletions(-) > Reviewed-by: Peter Maydell

Re: [PATCH 05/13] target/arm: Convert SDOT, UDOT to decodetree

On Tue, 25 Jun 2024 at 06:10, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/a64.decode | 7 + > target/arm/tcg/translate-a64.c | 54 ++ > 2 files changed, 35 insertions(+), 26 deletions(-) > Reviewed-by: Peter Mayd

Re: [PATCH 13/13] target/arm: Delete dead code from disas_simd_indexed

On Tue, 25 Jun 2024 at 06:09, Richard Henderson wrote: > > The last insns in this block, MLA and MLS, were converted > with f80701cb44d, and this code should have been removed then. "MLA, MLS, SQDMULH, SQRDMULH, were converted with f80701cb44d and f80701cb44d33", I think, since there's still code

Re: [PATCH 11/13] target/arm: Convert FCADD to decodetree

On Tue, 25 Jun 2024 at 06:09, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/a64.decode | 3 +++ > target/arm/tcg/translate-a64.c | 33 ++--- > 2 files changed, 13 insertions(+), 23 deletions(-) > Reviewed-by: Peter Maydell

Re: [PATCH 07/13] target/arm: Convert BFDOT to decodetree

On Tue, 25 Jun 2024 at 06:09, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/a64.decode | 2 ++ > target/arm/tcg/translate-a64.c | 20 +--- > 2 files changed, 7 insertions(+), 15 deletions(-) Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH 09/13] target/arm: Convert BFMMLA, SMMLA, UMMLA, USMMLA to decodetree

On Tue, 25 Jun 2024 at 06:09, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/a64.decode | 4 > target/arm/tcg/translate-a64.c | 36 -- > 2 files changed, 12 insertions(+), 28 deletions(-) > Reviewed-by: Peter Mayde

Re: [PATCH 10/13] target/arm: Add data argument to do_fp3_vector

On Tue, 25 Jun 2024 at 06:10, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/translate-a64.c | 52 +- > 1 file changed, 26 insertions(+), 26 deletions(-) Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH v3] target/i386/kvm: Refine VMX controls setting for backward compatibility

On 6/25/24 05:49, Zhao Liu wrote: diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 7ad8072748..a7c6c5b2d0 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -2386,6 +2386,7 @@ void kvm_arch_do_init_vcpu(X86CPU *cpu) static int kvm_get_supported_feature_msrs(KVM

Re: [PULL 00/46] virtio: features,fixes

On Tue, 4 Jun 2024 at 20:06, Michael S. Tsirkin wrote: > > virtio: features,fixes > > A bunch of improvements: > - vhost dirty log is now only scanned once, not once per device > - virtio and vhost now support VIRTIO_F_NOTIFICATION_D

[PATCH] hw/i386/intel_iommu: Block CFI when necessary

According to Intel VT-d specification 5.1.4, CFI must be blocked when Extended Interrupt Mode is enabled or Compatibility format interrupts are disabled. Signed-off-by: Yuke Peng --- hw/i386/intel_iommu.c | 28 hw/i386/trace-events | 1 + include/hw

[PATCH v2 0/2] ui/cocoa: Adds native absolute pointer support

This change implements passing guest cursors through to the native Cocoa host NSCursor on macOS when using absolute pointing device input. The first pass at this was based purely on NSCursor, which drew some criticism due to the somewhat complex nature of the code which was required to generate co

[PATCH v2 2/2] ui/cocoa: Adds NSCursor absolute pointer support

When pointer input is absolute, use the native macOS host’s Cocoa NSCursor to render the guest’s cursor. The rendered cursor is no longer cropped to the guest viewport, and the correct cursor image is passed to anything tapping into the host system’s native cursor. (such as remote access) The CALa

[PATCH v2 1/2] ui/cocoa: Minor fixes to CALayer based cursors

This change fixes some object lifetime issues. (Unreleased reference counts) Signed-off-by: Phil Dennis-Jordan --- ui/cocoa.m | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/ui/cocoa.m b/ui/cocoa.m index 06ca114800..cca987eac7 100644 --- a/ui/cocoa.m +++ b/ui/coco

Re: [PATCH v3] target/i386/kvm: Refine VMX controls setting for backward compatibility

[snip] > > Additionally, has_msr_vmx_vmfunc has the similar compat issue. I think > > it deserves a fix, too. > > > > -Zhao > Thanks for your reply. In fact, I've tried to process has_msr_vmx_vmfunc in > the same > way as has_msr_vmx_procbased_ctls in this patch, but when I tested on Linux > kern

Re: [RFC PATCH] cxl: avoid duplicating report from MCE & device

在 2024/6/22 1:51, Dan Williams 写道: Shiyang Ruan wrote: Background: Since CXL device is a memory device, while CPU consumes a poison page of CXL device, it always triggers a MCE by interrupt (INT18), no matter which-First path is configured. This is the first report. Then currently, in FW-Fi

Re: [PULL 00/46] virtio: features,fixes

On Tue, Jun 25, 2024 at 02:06:04PM +0100, Peter Maydell wrote: > On Tue, 4 Jun 2024 at 20:06, Michael S. Tsirkin wrote: > > > > virtio: features,fixes > > > > A bunch of improvements: > > - vhost dirty log is now only scanned once, n

Re: Help improve 32-bit testing

On 6/25/24 00:11, Thomas Huth wrote: On 25/06/2024 01.33, Richard Henderson wrote: Hiya, I've just discovered a 32-bit build issue that is probably 3 weeks old. While we still support 32-bit builds at all, I would request that we improve our cross-i686 testing.  For instance: we have cross-i6

Re: [PATCH v3 14/15] tests/qtest/bios-tables-test.c: Enable basic testing for RISC-V

On Tue, 25 Jun 2024 17:59:33 +0530 Sunil V L wrote: > On Tue, Jun 25, 2024 at 02:05:58PM +0200, Igor Mammedov wrote: > > On Tue, 25 Jun 2024 13:19:59 +0200 > > Igor Mammedov wrote: > > > > > On Fri, 21 Jun 2024 17:29:05 +0530 > > > Sunil V L wrote: > > > > > > > Add basic ACPI table test

Re: Help improve 32-bit testing

On 6/25/24 00:57, Philippe Mathieu-Daudé wrote: Hi Richard, On 25/6/24 01:33, Richard Henderson wrote: Hiya, I've just discovered a 32-bit build issue that is probably 3 weeks old. How and what did you notice? https://lore.kernel.org/qemu-devel/91f19b8d-387a-47cd-b7cc-19cdf4442...@linaro.o

Re: [PATCH v4 5/9] target/arm: Make some MTE helpers widely available

On 24/6/24 09:47, Philippe Mathieu-Daudé wrote: Hi Gustavo, On 24/6/24 07:30, Gustavo Romero wrote: Make the MTE helpers allocation_tag_mem_probe, load_tag1, and store_tag1 available to other subsystems. Again, you can make them available externally by removing the static scope. I'm not keen

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