[PATCH ats_vtd 17/22] atc: generic ATC that can be used by PCIe devices that support SVM

As the SVM-capable devices will need to cache translations, we provide an first implementation. This cache uses a two-level design based on hash tables. The first level is indexed by a PASID and the second by a virtual addresse. Signed-off-by: Clément Mathieu--Drif --- util/atc.c | 211 ++

[PATCH ats_vtd 22/22] intel_iommu: add support for ATS

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 75 -- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 73 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 496bed9447..2e78ebe6d2 100644

[PATCH ats_vtd 16/22] intel_iommu: fill the PASID field when creating an instance of IOMMUTLBEntry

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 9 + 1 file changed, 9 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index a42938aacd..f08c3e8f00 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2187,6 +2187,9 @@ static bool v

[PATCH ats_vtd 12/22] pci: add a pci-level initialization function for iommu notifiers

We add a convenient way to initialize an device-iotlb notifier. This is meant to be used by ATS-capable devices. pci_device_iommu_memory_region_pasid is introduces in this commit and will be used in several other SVM-related functions exposed in the PCI API. Signed-off-by: Clément Mathieu--Drif

[PATCH ats_vtd 09/22] pci: cache the bus mastering status in the device

Signed-off-by: Clément Mathieu--Drif --- hw/pci/pci.c| 24 ++-- include/hw/pci/pci_device.h | 1 + 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index c8a8aab306..51feede3cf 100644 --- a/hw/pci/pci.c +++ b/hw/pci/

[PATCH ats_vtd 18/22] atc: add unit tests

Signed-off-by: Clément Mathieu--Drif --- tests/unit/meson.build | 1 + tests/unit/test-atc.c | 527 + 2 files changed, 528 insertions(+) create mode 100644 tests/unit/test-atc.c diff --git a/tests/unit/meson.build b/tests/unit/meson.build index 26c109c

Re: [PATCH v12 00/13] Support blob memory and venus on qemu

Dmitry Osipenko writes: > Hello, > > This series enables Vulkan Venus context support on virtio-gpu. > > All virglrender and almost all Linux kernel prerequisite changes > needed by Venus are already in upstream. For kernel there is a pending > KVM patchset that fixes mapping of compound pages ne

[PATCH ats_vtd 03/22] intel_iommu: return page walk level even when the translation fails

We use this information in vtd_do_iommu_translate to populate the IOMMUTLBEntry and indicate the correct page mask. This prevents ATS devices from sending many useless translation requests when a megapage or gigapage iova is not mapped to a physical address. Signed-off-by: Clément Mathieu--Drif -

[PATCH ats_vtd 02/22] intel_iommu: make types match

The 'level' field in vtd_iotlb_key is an uint8_t. We don't need to store level as an int in vtd_lookup_iotlb (avoids a 'loosing precision' warning). VTDIOTLBPageInvInfo.mask is used in binary operations with addresses. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 2

[PATCH ats_vtd 21/22] intel_iommu: set the address mask even when a translation fails

Implements the behavior defined in section 10.2.3.5 of PCIe spec rev 5. This is needed by devices that support ATS. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_

[PATCH ats_vtd 04/22] intel_iommu: do not consider wait_desc as an invalid descriptor

Signed-off-by: Clément Mathieu--Drif Reviewed-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 5 + 1 file changed, 5 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index a2b275016c..f71c04d370 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3476,6

[PATCH ats_vtd 10/22] pci: add IOMMU operations to get address spaces and memory regions with PASID

Signed-off-by: Clément Mathieu--Drif --- hw/pci/pci.c | 19 +++ include/hw/pci/pci.h | 34 ++ 2 files changed, 53 insertions(+) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 51feede3cf..3fe47d4002 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci

Re: [PATCH v3 2/5] ppc/pnv: Extend SPI model

On Tue, 2024-05-21 at 08:18 +0200, Cédric Le Goater wrote: > On 5/21/24 08:11, Chalapathi V wrote: > > On 18-05-2024 01:24, Miles Glenn wrote: > > > Chalapathi, > > > > > > I'm having trouble seeing the benefit of breaking this commit out > > > from > > > patch 1/5. It seems like the two should b

Re: [PATCH v2 0/3] docs: define policy forbidding use of "AI" / LLM code generators

On Thu, 16 May 2024 at 12:23, Daniel P. Berrangé wrote: > > This patch kicks the hornet's nest of AI / LLM code generators. > > With the increasing interest in code generators in recent times, > it is inevitable that QEMU contributions will include AI generated > code. Thus far we have remained si

Re: [PATCH] docs/system/target-arm: Re-alphabetize board list

On 5/20/24 07:14, Peter Maydell wrote: The board list in target-arm.rst is supposed to be in alphabetical order by the title text of each file (which is not the same as alphabetical order by filename). A few items had got out of order; correct them. The entry for "Facebook Yosemite v3.5 Platfor

RE: [PATCH V10 7/8] gdbstub: Add helper function to unregister GDB register space

Hi Alex, > From: Alex Bennée > Sent: Tuesday, May 21, 2024 1:45 PM > To: Salil Mehta > > Salil Mehta writes: > > > Add common function to help unregister the GDB register space. This > > shall be done in context to the CPU unrealization. > > > > Signed-off-by: Salil Mehta > > Test

Re: [PATCH v12 00/13] Support blob memory and venus on qemu

Alex Bennée writes: > Dmitry Osipenko writes: > >> Hello, >> >> This series enables Vulkan Venus context support on virtio-gpu. >> >> All virglrender and almost all Linux kernel prerequisite changes >> needed by Venus are already in upstream. For kernel there is a pending >> KVM patchset that fi

Re: [PATCH 0/4] testing/next: purging remaining centos 8 bits

On 5/21/24 05:53, Alex Bennée wrote: Alex Bennée (4): ci: remove centos-steam-8 customer runner docs/devel: update references to centos to later version tests/vm: update centos.aarch64 image to 9 tests/vm: remove plain centos image Reviewed-by: Richard Henderson r~

Re: [PATCH V10 7/8] gdbstub: Add helper function to unregister GDB register space

Salil Mehta writes: > Hi Alex, > >> From: Alex Bennée >> Sent: Tuesday, May 21, 2024 1:45 PM >> To: Salil Mehta >> >> Salil Mehta writes: >> >> > Add common function to help unregister the GDB register space. This >> > shall be done in context to the CPU unrealization. >> > >> > Si

Re: [PATCH v2 01/12] target/ppc: Make checkstop actually stop the system

Reviewed-by: Glenn Miles Thanks, Glenn On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote: > checkstop state does not halt the system, interrupts continue to be > serviced, and other CPUs run. Make it stop the machine with > qemu_system_guest_panicked. > > Signed-off-by: Nicholas Piggin

Re: [PATCH v2 02/12] target/ppc: improve checkstop logging

Reviewed-by: Glenn Miles Thanks, Glenn On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote: > Change the logging not to print to stderr as well, because a > checkstop is a guest error (or perhaps a simulated machine error) > rather than a QEMU error, so send it to the log. > > Update the

Re: [PATCH v2 04/12] target/ppc: BookE DECAR SPR is 32-bit

Reviewed-by: Glenn Miles Thanks, Glenn On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote: > The DECAR SPR is 32-bits width. > > Signed-off-by: Nicholas Piggin > --- > target/ppc/cpu_init.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/ppc/cpu_init.c

Re: [PATCH v2 03/12] target/ppc: Implement attn instruction on BookS 64-bit processors

Looks like this patch is failing to apply to the current master head? Thanks, Glenn On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote: > attn is an implementation-specific instruction that on POWER (and G5/ > 970) can be enabled with a HID bit (disabled = illegal), and > executing > it ca

Re: [PATCH v2 06/12] target/ppc: Add PPR32 SPR

Reviewed-by: Glenn Miles Thanks, Glenn On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote: > PPR32 provides access to the upper half of PPR. > > Signed-off-by: Nicholas Piggin > --- > target/ppc/cpu.h| 1 + > target/ppc/spr_common.h | 2 ++ > target/ppc/cpu_init.c | 12

Re: [PATCH v2 08/12] target/ppc: Add SMT support to simple SPRs

Reviewed-by: Glenn Miles Thanks, Glenn On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote: > AMOR, MMCRC, HRMOR, TSCR, HMEER, RPR SPRs are per-core or per-LPAR > registers with simple (generic) implementations. > > Signed-off-by: Nicholas Piggin > --- > target/ppc/cpu_init.c | 12 +

Re: [PATCH v2 09/12] target/ppc: Add SMT support to PTCR SPR

Reviewed-by: Glenn Miles Thanks, Glenn On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote: > PTCR is a per-core register. > > Signed-off-by: Nicholas Piggin > --- > target/ppc/misc_helper.c | 16 ++-- > target/ppc/translate.c | 4 > 2 files changed, 18 insertions(+)

Re: [PATCH 57/57] target/arm: Convert SQDMULH, SQRDMULH to decodetree

On Mon, 6 May 2024 at 02:10, Richard Henderson wrote: > > These are the last instructions within disas_simd_three_reg_same > and disas_simd_scalar_three_reg_same, so remove them. > > Signed-off-by: Richard Henderson > --- > target/arm/helper.h| 10 ++ > target/arm/tcg/a64.decode

[PATCH] target/i386: Add x-amd-ccx-size property

According to AMD64 Architecture Programmer's Manual volume 3, information about the cache topology is exposed by 0x801D CPUID leaf, and 0x801E CPUID leaf is exposing information about the topology of the entire processor. For example, CPUID on the real EPYC Milan 7713 shows: * 0x801D_E

Re: [PATCH v2 11/12] target/ppc: Implement SPRC/SPRD SPRs

Reviewed-by: Glenn Miles Thanks, Glenn On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote: > This implements the POWER SPRC/SPRD SPRs, and SCRATCH0-7 registers > that > can be accessed via these indirect SPRs. > > SCRATCH registers only provide storage, but they are used by firmware > fo

Re: [PATCH v2 10/12] target/ppc: Implement LDBAR, TTR SPRs

Reviewed-by: Glenn Miles Thanks, Glenn On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote: > LDBAR, TTR are a Power-specific SPRs. These simple implementations > are enough for IBM proprietary firmware for now. > > Signed-off-by: Nicholas Piggin > --- > target/ppc/cpu.h | 2 ++ >

Re: [PATCH 32/57] target/arm: Inline scalar SUQADD and USQADD

On Mon, 6 May 2024 at 02:08, Richard Henderson wrote: > > This eliminates the last uses of these neon helpers. > Incorporate the MO_64 expanders as an option to the vector expander. > > Signed-off-by: Richard Henderson > +/* > + * Set @res to the correctly saturated result. > + * Set @qc non-ze

Re: [PATCH v2 07/12] target/ppc: add helper to write per-LPAR SPRs

Reviewed-by: Glenn Miles Thanks, Glenn On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote: > An SPR can be either per-thread, per-core, or per-LPAR. Per-LPAR > means > per-thread or per-core, depending on 1LPAR mode. > > Signed-off-by: Nicholas Piggin > --- > target/ppc/spr_common.h |

Re: [PATCH v2 12/12] target/ppc: add SMT support to msgsnd broadcast

Reviewed-by: Glenn Miles Thanks, Glenn On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote: > msgsnd has a broadcast mode that sends hypervisor doorbells to all > threads belonging to the same core as the target. A "subcore" mode > sends to all or one thread depending on 1LPAR mode. > > S

Re: [PATCH v2 02/12] target/ppc: improve checkstop logging

On 5/20/24 18:30, Nicholas Piggin wrote: Change the logging not to print to stderr as well, because a checkstop is a guest error (or perhaps a simulated machine error) rather than a QEMU error, so send it to the log. Update the checkstop message, and log CPU registers too. Signed-off-by: Nichol

Re: [PATCH v2 03/12] target/ppc: Implement attn instruction on BookS 64-bit processors

On 5/20/24 18:30, Nicholas Piggin wrote: diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index c358927211..2532408be0 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -3025,6 +3031,12 @@ static inline int check_pow_nocheck(CPUPPCState *env) return 1; } +/* attn enable check

Re: [PATCH v2 06/12] target/ppc: Add PPR32 SPR

On 5/20/24 18:30, Nicholas Piggin wrote: +void spr_write_ppr32(DisasContext *ctx, int sprn, int gprn) +{ +TCGv t0 = tcg_temp_new(); + +tcg_gen_shli_tl(t0, cpu_gpr[gprn], 32); +gen_store_spr(SPR_PPR, t0); +spr_store_dump_spr(SPR_PPR); +} The documentation isn't clear on whether t

RE: [PATCH V10 7/8] gdbstub: Add helper function to unregister GDB register space

> From: Alex Bennée > Sent: Tuesday, May 21, 2024 4:23 PM > To: Salil Mehta > > Salil Mehta writes: > > > Hi Alex, > > > >> From: Alex Bennée > >> Sent: Tuesday, May 21, 2024 1:45 PM > >> To: Salil Mehta > >> > >> Salil Mehta writes: > >> > >> > Add common function to he

Re: [PATCH 32/57] target/arm: Inline scalar SUQADD and USQADD

On 5/21/24 09:46, Peter Maydell wrote: On Mon, 6 May 2024 at 02:08, Richard Henderson wrote: This eliminates the last uses of these neon helpers. Incorporate the MO_64 expanders as an option to the vector expander. Signed-off-by: Richard Henderson +/* + * Set @res to the correctly satura

Re: [PATCH 57/57] target/arm: Convert SQDMULH, SQRDMULH to decodetree

On 5/21/24 09:16, Peter Maydell wrote: +void HELPER(neon_sqrdmulh_idx_s)(void *vd, void *vn, void *vm, + void *vq, uint32_t desc) +{ +intptr_t i, j, opr_sz = simd_oprsz(desc); +int idx = simd_data(desc); +int32_t *d = vd, *n = vn, *m = (int32_t *)vm + H

[PATCH] Hyperv: Correct kvm_hv_handle_exit return value

From: donsheng This bug fix addresses the incorrect return value of kvm_hv_handle_exit for KVM_EXIT_HYPERV_SYNIC, which should be EXCP_INTERRUPT. Handling of KVM_EXIT_HYPERV_SYNIC in QEMU needs to be synchronous. This means that async_synic_update should run in the current QEMU vCPU thread befor

[PATCH v3 2/4] target/hexagon: idef-parser remove undefined functions

Signed-off-by: Anton Johansson Reviewed-by: Taylor Simpson --- target/hexagon/idef-parser/parser-helpers.h | 13 - 1 file changed, 13 deletions(-) diff --git a/target/hexagon/idef-parser/parser-helpers.h b/target/hexagon/idef-parser/parser-helpers.h index 7c58087169..2087d534a9 100

[PATCH v3 3/4] target/hexagon: idef-parser fix leak of init_list

gen_inst_init_args() is called for instructions using a predicate as an rvalue. Upon first call, the list of arguments which might need initialization init_list is freed to indicate that they have been processed. For instructions without an rvalue predicate, gen_inst_init_args() isn't called and in

[PATCH v3 0/4] target/hexagon: Minor idef-parser cleanup

Was running idef-parser with valgrind and noticed we were leaking the init_list GArray, which is used to hold instruction arguments that may need initialization. This patchset fixes the leak, removes unused macros and undefined functions, and simplifies gen_inst_init_args() to only handle predicat

[PATCH v3 1/4] target/hexagon: idef-parser remove unused defines

Before switching to GArray/g_string_printf we used fixed size arrays for output buffers and instructions arguments among other things. Macros defining the sizes of these buffers were left behind, remove them. Signed-off-by: Anton Johansson Reviewed-by: Taylor Simpson --- target/hexagon/idef-pa

[PATCH v3 4/4] target/hexagon: idef-parser simplify predicate init

Only predicate instruction arguments need to be initialized by idef-parser. This commit removes registers from the init_list and simplifies gen_inst_init_args() slightly. Signed-off-by: Anton Johansson Reviewed-by: Taylor Simpson --- target/hexagon/idef-parser/idef-parser.y| 2 -- target/h

[PATCH] accel/tcg: Init tb size and icount before plugin_gen_tb_end

When passing disassembly data to plugin callbacks, translator_st_len relies on db->tb->size having been set. Fixes: 4c833c60e047 ("disas: Use translator_st to get disassembly data") Reported-by: Bernhard Beschow Signed-off-by: Richard Henderson --- accel/tcg/translator.c | 8 1 file ch

Re: [PATCH-for-9.1 v2 2/3] migration: Remove RDMA protocol handling

On Fri, May 17, 2024 at 03:01:59PM +0200, Yu Zhang wrote: > Hello Michael and Peter, Hi, > > Exactly, not so compelling, as I did it first only on servers widely > used for production in our data center. The network adapters are > > Ethernet controller: Broadcom Inc. and subsidiaries NetXtreme

Re: [PATCH] hw/core/machine: move compatibility flags for VirtIO-net USO to machine 8.1

On Fri, May 17, 2024 at 09:53:36AM +0200, Fiona Ebner wrote: > Migration from an 8.2 or 9.0 binary to an 8.1 binary with machine > version 8.1 can fail with: > > > kvm: Features 0x1c0010130afffa7 unsupported. Allowed features: 0x10179bfffe7 > > kvm: Failed to load virtio-net:virtio > > kvm: error

Re: [PATCH v3 2/4] target/hexagon: idef-parser remove undefined functions

On 5/21/2024 3:16 PM, Anton Johansson via wrote: Signed-off-by: Anton Johansson Reviewed-by: Taylor Simpson --- Reviewed-by: Brian Cain target/hexagon/idef-parser/parser-helpers.h | 13 - 1 file changed, 13 deletions(-) diff --git a/target/hexagon/idef-parser/parser-help

Re: [PATCH v3 3/4] target/hexagon: idef-parser fix leak of init_list

On 5/21/2024 3:16 PM, Anton Johansson via wrote: gen_inst_init_args() is called for instructions using a predicate as an rvalue. Upon first call, the list of arguments which might need initialization init_list is freed to indicate that they have been processed. For instructions without an rvalu

Re: [PATCH v3 1/4] target/hexagon: idef-parser remove unused defines

On 5/21/2024 3:16 PM, Anton Johansson via wrote: Before switching to GArray/g_string_printf we used fixed size arrays for output buffers and instructions arguments among other things. Macros defining the sizes of these buffers were left behind, remove them. Signed-off-by: Anton Johansson Rev

Re: [PATCH v3 4/4] target/hexagon: idef-parser simplify predicate init

On 5/21/2024 3:16 PM, Anton Johansson via wrote: Only predicate instruction arguments need to be initialized by idef-parser. This commit removes registers from the init_list and simplifies gen_inst_init_args() slightly. Signed-off-by: Anton Johansson Reviewed-by: Taylor Simpson --- Reviewe

Re: [PATCH v7 09/12] hw/cxl/events: Add qmp interfaces to add/release dynamic capacity extents

>From 9d6d774ec973d22c0f662b32385345a88b14cc55 Mon Sep 17 00:00:00 2001 From: Fan Ni Date: Tue, 20 Feb 2024 09:48:31 -0800 Subject: [PATCH 11/14] hw/cxl/events: Add qmp interfaces to add/release dynamic capacity extents To simulate FM functionalities for initiating Dynamic Capacity Add (Opcode

Re: [PATCH v7 09/12] hw/cxl/events: Add qmp interfaces to add/release dynamic capacity extents

On Mon, May 20, 2024 at 05:50:12PM +0100, Jonathan Cameron wrote: > On Wed, 1 May 2024 15:29:31 -0700 > fan wrote: > > > From 873f59ec06c38645768ada452d9b18920a34723e Mon Sep 17 00:00:00 2001 > > From: Fan Ni > > Date: Tue, 20 Feb 2024 09:48:31 -0800 > > Subject: [PATCH] hw/cxl/events: Add qmp i

Re: [PATCH v12 00/13] Support blob memory and venus on qemu

On 5/21/24 17:57, Alex Bennée wrote: > Alex Bennée writes: > >> Dmitry Osipenko writes: >> >>> Hello, >>> >>> This series enables Vulkan Venus context support on virtio-gpu. >>> >>> All virglrender and almost all Linux kernel prerequisite changes >>> needed by Venus are already in upstream. For

Re: [PATCH v12 10/13] virtio-gpu: Move fence_poll timer to VirtIOGPUGL

On 5/20/24 06:51, Akihiko Odaki wrote: > On 2024/05/20 6:27, Dmitry Osipenko wrote: >> Move fence_poll timer to VirtIOGPUGL for consistency with cmdq_resume_bh >> that are used only by GL device. >> >> Signed-off-by: Dmitry Osipenko > > Thanks for refacotoring. > > Please move this before "[PATC

Re: [PATCH V10 1/8] accel/kvm: Extract common KVM vCPU {creation,parking} code

On Tue May 21, 2024 at 9:32 AM AEST, Salil Mehta wrote: > KVM vCPU creation is done once during the vCPU realization when Qemu vCPU > thread > is spawned. This is common to all the architectures as of now. > > Hot-unplug of vCPU results in destruction of the vCPU object in QOM but the > correspond

Re: [PATCH V9 6/8] physmem: Add helper function to destroy CPU AddressSpace

On Mon May 20, 2024 at 8:55 PM AEST, Salil Mehta wrote: > > From: Nicholas Piggin > > Sent: Monday, May 20, 2024 9:19 AM > > > > On Mon May 20, 2024 at 7:06 AM AEST, Salil Mehta wrote: > > > Virtual CPU Hot-unplug leads to unrealization of a CPU object. This > > > also involves destruction

Re: [PATCH v2 03/12] target/ppc: Implement attn instruction on BookS 64-bit processors

Ah sorry, it's on top of some of Chinmay's decodetree series which is causing a couple of minor rejects. Thanks, Nick On Wed May 22, 2024 at 1:41 AM AEST, Miles Glenn wrote: > Looks like this patch is failing to apply to the current master head? > > Thanks, > > Glenn > > On Tue, 2024-05-21 at 11:

Re: [PATCH v2 03/12] target/ppc: Implement attn instruction on BookS 64-bit processors

On Wed May 22, 2024 at 3:34 AM AEST, Richard Henderson wrote: > On 5/20/24 18:30, Nicholas Piggin wrote: > > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > > index c358927211..2532408be0 100644 > > --- a/target/ppc/cpu.h > > +++ b/target/ppc/cpu.h > > @@ -3025,6 +3031,12 @@ static inline int ch

Re: [PATCH v3 1/6] hw/loongarch: Refine acpi srat table for numa memory

在 2024/5/15 下午5:39, Bibo Mao 写道: One LoongArch virt machine platform, there is limitation for memory map information. The minimum memory size is 256M and minimum memory size for numa node0 is 256M also. With qemu numa qtest, it is possible that memory size of numa node0 is 128M. Limitations for

Re: [PATCH v2 06/12] target/ppc: Add PPR32 SPR

On Wed May 22, 2024 at 3:40 AM AEST, Richard Henderson wrote: > On 5/20/24 18:30, Nicholas Piggin wrote: > > +void spr_write_ppr32(DisasContext *ctx, int sprn, int gprn) > > +{ > > +TCGv t0 = tcg_temp_new(); > > + > > +tcg_gen_shli_tl(t0, cpu_gpr[gprn], 32); > > +gen_store_spr(SPR_PPR,

Re: [PATCH v3 2/6] hw/loongarch: Refine fadt memory table for numa memory

在 2024/5/15 下午5:39, Bibo Mao 写道: One LoongArch virt machine platform, there is limitation for memory map information. The minimum memory size is 256M and minimum memory size for numa node0 is 256M also. With qemu numa qtest, it is possible that memory size of numa node0 is 128M. Limitations for

[PATCH v3] target/ppc: Add PPR32 SPR

PPR32 provides access to the upper half of PPR. Signed-off-by: Nicholas Piggin --- v3: - Don't clobber lower half of PPR. - Add spr_load_dump_spr (spr_store_dump_spr was already there). target/ppc/cpu.h| 1 + target/ppc/spr_common.h | 2 ++ target/ppc/cpu_init.c | 12 t

[PATCH RISU v2 7/8] sparc64: Add a few logical insns

Just a token to verify the script is working. Signed-off-by: Richard Henderson --- sparc64.risu | 30 ++ 1 file changed, 30 insertions(+) create mode 100644 sparc64.risu diff --git a/sparc64.risu b/sparc64.risu new file mode 100644 index 000..b45ea86 --- /dev/nu

[PATCH RISU v2 1/8] risu: Allow use of ELF test files

By using elf files, we make it easier to disassemble the test file, to match comparison failures to code. Signed-off-by: Richard Henderson --- risu.c | 57 - 1 file changed, 52 insertions(+), 5 deletions(-) diff --git a/risu.c b/risu.c ind

[PATCH RISU v2 4/8] risu: Add initial sparc64 support

Best effort for both Linux and Solaris as a host, since the gcc compile farm has more working Sparc Solaris hosts than Sparc Linux hosts. What's missing is a value for %gsr from Solaris. This could complicate comparison of VIS instructions. Signed-off-by: Richard Henderson --- Makefile

[PATCH RISU v2 0/8] ELF and Sparc64 support

Let risu accept elf test files, adjusted from v1. Adjust risugen to invoke the assembler and linker, with a cross-compiler prefix if needed. Add some sparc64 testing which utilizes this. r~ Richard Henderson (8): risu: Allow use of ELF test files Build elf test cases instead of raw binaries

[PATCH RISU v2 2/8] Build elf test cases instead of raw binaries

For test_arch64.s and test_arm.s, use '.inst' so that the risu control insns are marked as instructions for disassembly. For test_i386.S, split the data to be loaded into the data section; fix an error aligning the data: 16 not 2**16. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard He

[PATCH RISU v2 6/8] risugen: Add sparc64 support

Signed-off-by: Richard Henderson --- risugen| 10 +- risugen_common.pm | 50 +- risugen_sparc64.pm | 385 + 3 files changed, 443 insertions(+), 2 deletions(-) create mode 100644 risugen_sparc64.pm diff --git a/risugen b/risugen inde

[PATCH RISU v2 8/8] sparc64: Add VIS1 instructions

Signed-off-by: Richard Henderson --- sparc64.risu | 91 1 file changed, 91 insertions(+) diff --git a/sparc64.risu b/sparc64.risu index b45ea86..10a8510 100644 --- a/sparc64.risu +++ b/sparc64.risu @@ -28,3 +28,94 @@ XOR_r SPARC 10 r

[PATCH RISU v2 5/8] risugen: Be explicit about print destinations

Printing directly to STDOUT and STDERR will allow the print destination to be selected elsewhere. Signed-off-by: Richard Henderson --- risugen_common.pm | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/risugen_common.pm b/risugen_common.pm index 71ee996..520

[PATCH RISU v2 3/8] Introduce host_context_t

Most hosts pass ucontext_t as the third parameter of signal handlers. In one existing usage, loongarch64 is using the kernel's struct ucontext instead of libc's ucontext_t. This is probably a simple mistake that could be fixed, but the structure member names differ, so the change would not be com

[PATCH 2/2] target/ppc: Tidy pmu_count_insns implementation

Merge the user-only and full implementations together, and only call translator_io_start() and only create and set the label when necessary. Signed-off-by: Nicholas Piggin --- target/ppc/translate.c | 55 +- 1 file changed, 28 insertions(+), 27 deletions(-

[PATCH 0/2] target/ppc: Fix PMU instruction counting

The crux of the problem being that dynamic exits from a TB would not count instructions previously executed in the TB. I don't know how important it is for PMU to count instructions exactly, however for instruction replay this can lead to different counts for the same execution (e.g., because TBs c

[PATCH 1/2] target/ppc: Fix PMC5 instruction counting

PMC5 does not count instructions correctly when single stepping the target with gdb, or when taking exceptions. The single-stepping inaccuracy is a problem for reverse debugging (because the PMC5 value can go out of sync between executions of the same trace). AFAIKS the current instruction count s

[PATCH v2 03/20] vfio/helpers: Use g_autofree in vfio_set_irq_signaling()

Local pointer irq_set is freed before return from vfio_set_irq_signaling(). Use 'g_autofree' to avoid the g_free() calls. Signed-off-by: Zhenzhong Duan --- hw/vfio/helpers.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/vfio/helpers.c b/hw/vfio/helpers.c index 47b4096

[PATCH v2 10/20] vfio/pci: Make vfio_populate_device() return a bool

Since vfio_populate_device() takes an 'Error **' argument, best practices suggest to return a bool. See the qapi/error.h Rules section. By this chance, pass errp directly to vfio_populate_device() to avoid calling error_propagate(). Signed-off-by: Zhenzhong Duan --- hw/vfio/pci.c | 21 +

[PATCH v2 17/20] vfio: Use g_autofree in all call site of vfio_get_region_info()

There are some exceptions when pointer to vfio_region_info is reused. In that case, the pointed memory is freed manually. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan --- hw/vfio/helpers.c | 7 ++- hw/vfio/igd.c | 5 ++--- hw/vfio/pci.c | 13 +++-- 3 files

[PATCH v2 15/20] vfio/pci-quirks: Make vfio_pci_igd_opregion_init() return bool

This is to follow the coding standand in qapi/error.h to return bool for bool-valued functions. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan Reviewed-by: Cédric Le Goater --- hw/vfio/pci.h| 6 +++--- hw/vfio/igd.c| 3 +-- hw/vfio/pci-quirks.c | 8 hw/vf

[PATCH v2 08/20] vfio/pci: Make vfio_intx_enable_kvm() return a bool

Since vfio_intx_enable_kvm() takes an 'Error **' argument, best practices suggest to return a bool. See the qapi/error.h Rules section. Signed-off-by: Zhenzhong Duan Reviewed-by: Cédric Le Goater --- hw/vfio/pci.c | 15 --- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git

[PATCH v2 11/20] vfio/pci: Make vfio_intx_enable() return bool

This is to follow the coding standand in qapi/error.h to return bool for bool-valued functions. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan Reviewed-by: Cédric Le Goater --- hw/vfio/pci.c | 19 --- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/

[PATCH v2 12/20] vfio/pci: Make vfio_populate_vga() return bool

This is to follow the coding standand in qapi/error.h to return bool for bool-valued functions. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan Reviewed-by: Cédric Le Goater --- hw/vfio/pci.h | 2 +- hw/vfio/igd.c | 2 +- hw/vfio/pci.c | 11 +-- 3 files changed, 7 insert

[PATCH v2 19/20] vfio/ccw: Drop local @err in vfio_ccw_realize()

Use @errp to fetch error information directly and drop the local variable @err. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan --- hw/vfio/ccw.c | 21 ++--- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/hw/vfio/ccw.c b/hw/vfio/ccw.c index 2600e62e

[PATCH v2 20/20] vfio/ccw: Fix the missed unrealize() call in error path

When get name failed, we should call unrealize() so that vfio_ccw_realize() is self contained. Fixes: 909a6254eda ("vfio/ccw: Make vfio cdev pre-openable by passing a file handle") Signed-off-by: Zhenzhong Duan --- hw/vfio/ccw.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --gi

[PATCH v2 04/20] vfio/helpers: Make vfio_set_irq_signaling() return bool

This is to follow the coding standand in qapi/error.h to return bool for bool-valued functions. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan Reviewed-by: Cédric Le Goater --- include/hw/vfio/vfio-common.h | 4 ++-- hw/vfio/ap.c | 8 +++ hw/vfio/ccw.c

[PATCH v2 02/20] vfio/display: Make vfio_display_*() return bool

This is to follow the coding standand in qapi/error.h to return bool for bool-valued functions. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan Reviewed-by: Cédric Le Goater --- hw/vfio/pci.h | 2 +- hw/vfio/display.c | 20 ++-- hw/vfio/pci.c | 3 +-- 3 f

[PATCH v2 06/20] vfio/platform: Make vfio_populate_device() and vfio_base_device_init() return bool

This is to follow the coding standand in qapi/error.h to return bool for bool-valued functions. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan Reviewed-by: Cédric Le Goater --- hw/vfio/platform.c | 40 +--- 1 file changed, 17 insertions(+), 23

[PATCH v2 05/20] vfio/helpers: Make vfio_device_get_name() return bool

This is to follow the coding standand in qapi/error.h to return bool for bool-valued functions. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan Reviewed-by: Cédric Le Goater --- include/hw/vfio/vfio-common.h | 2 +- hw/vfio/ap.c | 2 +- hw/vfio/ccw.c

[PATCH v2 01/20] vfio/display: Fix error path in call site of ramfb_setup()

vfio_display_dmabuf_init() and vfio_display_region_init() calls ramfb_setup() without checking its return value. So we may run into a situation that vfio_display_probe() succeed but errp is set. This is risky and may lead to assert failure in error_setv(). Cc: Gerd Hoffmann Fixes: b290659fc3d ("

[PATCH v2 13/20] vfio/pci: Make capability related functions return bool

The functions operating on capability don't have a consistent return style. Below functions are in bool-valued functions style: vfio_msi_setup() vfio_msix_setup() vfio_add_std_cap() vfio_add_capabilities() Below two are integer-valued functions: vfio_add_vendor_specific_cap() vfio_setup_pcie_cap(

[PATCH v2 07/20] vfio/ccw: Make vfio_ccw_get_region() return a bool

Since vfio_populate_device() takes an 'Error **' argument, best practices suggest to return a bool. See the qapi/error.h Rules section. Signed-off-by: Zhenzhong Duan Reviewed-by: Cédric Le Goater --- hw/vfio/ccw.c | 15 +++ 1 file changed, 7 insertions(+), 8 deletions(-) diff --git

[PATCH v2 00/20] VFIO: misc cleanups part2

Hi This is the last round of cleanup series to change functions in hw/vfio/ to return bool when the error is passed through errp parameter. The first round is at https://lists.gnu.org/archive/html/qemu-devel/2024-05/msg01147.html I see Cédric is also working on some migration stuff cleanup, so

[PATCH v2 09/20] vfio/pci: Make vfio_pci_relocate_msix() and vfio_msix_early_setup() return a bool

Since vfio_pci_relocate_msix() and vfio_msix_early_setup() takes an 'Error **' argument, best practices suggest to return a bool. See the qapi/error.h Rules section. By this chance, pass errp directly to vfio_msix_early_setup() to avoid calling error_propagate(). Signed-off-by: Zhenzhong Duan --

RE: [PATCH 02/16] vfio/display: Make vfio_display_*() return bool

>-Original Message- >From: Cédric Le Goater >Subject: Re: [PATCH 02/16] vfio/display: Make vfio_display_*() return bool > >On 5/15/24 10:20, Zhenzhong Duan wrote: >> This is to follow the coding standand in qapi/error.h to return bool >> for bool-valued functions. >> >> Suggested-by: Céd

[PATCH v2 14/20] vfio/pci: Use g_autofree for vfio_region_info pointer

Pointer opregion is freed after vfio_pci_igd_opregion_init(). Use 'g_autofree' to avoid the g_free() calls. Signed-off-by: Zhenzhong Duan Reviewed-by: Cédric Le Goater --- hw/vfio/pci.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index c33

[PATCH v2 16/20] vfio/pci-quirks: Make vfio_add_*_cap() return bool

This is to follow the coding standand in qapi/error.h to return bool for bool-valued functions. Include below functions: vfio_add_virt_caps() vfio_add_nv_gpudirect_cap() vfio_add_vmd_shadow_cap() Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan Reviewed-by: Cédric Le Goater --- hw

[PATCH v2 18/20] vfio/igd: Use g_autofree in vfio_probe_igd_bar4_quirk()

Pointer opregion, host and lpc are allocated and freed in vfio_probe_igd_bar4_quirk(). Use g_autofree to automatically free them. Signed-off-by: Zhenzhong Duan --- hw/vfio/igd.c | 27 --- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/hw/vfio/igd.c b/hw/v

[PATCH] virtio-pci: Fix the use of an uninitialized irqfd.

The crash was reported in MAC OS and NixOS, here is the link for this bug https://gitlab.com/qemu-project/qemu/-/issues/2334 https://gitlab.com/qemu-project/qemu/-/issues/2321 The root cause is that the function virtio_pci_set_guest_notifiers() only initializes the irqfd when the use_guest_notifie

Re: [PULL 10/38] tests/qtest/migration: Add a test for the analyze-migration script

On 21/05/2024 14.46, Fabiano Rosas wrote: Alex Bennée writes: Juan Quintela writes: From: Fabiano Rosas Add a smoke test that migrates to a file and gives it to the script. It should catch the most annoying errors such as changes in the ram flags. After code has been merged it becomes wa

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