Reviewed-by: Glenn Miles <mil...@linux.ibm.com>
Thanks,
Glenn
On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote:
> PTCR is a per-core register.
>
> Signed-off-by: Nicholas Piggin <npig...@gmail.com>
> ---
> target/ppc/misc_helper.c | 16 ++++++++++++++--
> target/ppc/translate.c | 4 ++++
> 2 files changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
> index 6f419c9346..a67930d031 100644
> --- a/target/ppc/misc_helper.c
> +++ b/target/ppc/misc_helper.c
> @@ -173,6 +173,7 @@ void helper_store_sdr1(CPUPPCState *env,
> target_ulong val)
> void helper_store_ptcr(CPUPPCState *env, target_ulong val)
> {
> if (env->spr[SPR_PTCR] != val) {
> + CPUState *cs = env_cpu(env);
> PowerPCCPU *cpu = env_archcpu(env);
> target_ulong ptcr_mask = PTCR_PATB | PTCR_PATS;
> target_ulong patbsize = val & PTCR_PATS;
> @@ -194,8 +195,19 @@ void helper_store_ptcr(CPUPPCState *env,
> target_ulong val)
> return;
> }
>
> - env->spr[SPR_PTCR] = val;
> - tlb_flush(env_cpu(env));
> + if (cs->nr_threads == 1 || !(env->flags &
> POWERPC_FLAG_SMT_1LPAR)) {
> + env->spr[SPR_PTCR] = val;
> + tlb_flush(cs);
> + } else {
> + CPUState *ccs;
> +
> + THREAD_SIBLING_FOREACH(cs, ccs) {
> + PowerPCCPU *ccpu = POWERPC_CPU(ccs);
> + CPUPPCState *cenv = &ccpu->env;
> + cenv->spr[SPR_PTCR] = val;
> + tlb_flush(ccs);
> + }
> + }
> }
> }
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index c688551434..76f829ad12 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -971,6 +971,10 @@ void spr_write_hior(DisasContext *ctx, int sprn,
> int gprn)
> }
> void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
> {
> + if (!gen_serialize_core(ctx)) {
> + return;
> + }
> +
> gen_helper_store_ptcr(tcg_env, cpu_gpr[gprn]);
> }
>
