Re: hw/usb/hcd-ohci: Fix #1510, #303: pid not IN or OUT

2024-05-10 Thread Cord Amfmgm
On Thu, May 9, 2024 at 3:37 PM BALATON Zoltan wrote: > On Thu, 9 May 2024, Cord Amfmgm wrote: > > On Thu, May 9, 2024 at 12:48 PM Peter Maydell > > wrote: > > > >> On Wed, 8 May 2024 at 16:29, Cord Amfmgm wrote: > >>> On Wed, May 8, 2024 at 3:45 AM Thomas Huth wrote: > > Your Signed-

Re: [RFC 0/2] Identify aliased maps in vdpa SVQ iova_tree

2024-05-10 Thread Eugenio Perez Martin
On Fri, May 10, 2024 at 6:29 AM Jason Wang wrote: > > On Thu, May 9, 2024 at 3:10 PM Eugenio Perez Martin > wrote: > > > > On Thu, May 9, 2024 at 8:27 AM Jason Wang wrote: > > > > > > On Thu, May 9, 2024 at 1:16 AM Eugenio Perez Martin > > > wrote: > > > > > > > > On Wed, May 8, 2024 at 4:29 

[PATCH v3] hw/virtio: Fix obtain the buffer id from the last descriptor

2024-05-10 Thread Wafer
The virtio-1.3 specification writes: 2.8.6 Next Flag: Descriptor Chaining Buffer ID is included in the last descriptor in the list. If the feature (_F_INDIRECT_DESC) has been negotiated, install only one descriptor in the virt

Re: [PATCH 4/6] virtio: virtqueue_ordered_flush - VIRTIO_F_IN_ORDER support

2024-05-10 Thread Eugenio Perez Martin
On Mon, May 6, 2024 at 5:06 PM Jonah Palmer wrote: > > Add VIRTIO_F_IN_ORDER feature support for virtqueue_flush operations. > > The goal of the virtqueue_flush operation when the VIRTIO_F_IN_ORDER > feature has been negotiated is to write elements to the used/descriptor > ring in-order and then u

Re: [RFC QEMU PATCH v9 1/2] virtio-pci: only reset pm state during resetting

2024-05-10 Thread Chen, Jiqian
Hi, On 2024/4/16 15:01, Jiqian Chen wrote: > Fix bug imported by 27ce0f3afc9dd25d21b43bbce505157afd93d111 > (fix Power Management Control Register for PCI Express virtio devices) > > Only state of PM_CTRL is writable. > Only when flag VIRTIO_PCI_FLAG_INIT_PM is set, need to reset state. > > Sign

Re: [PATCH V1 24/26] seccomp: cpr-exec blocker

2024-05-10 Thread Daniel P . Berrangé
On Mon, Apr 29, 2024 at 08:55:33AM -0700, Steve Sistare wrote: > cpr-exec mode needs permission to exec. Block it if permission is denied. > > Signed-off-by: Steve Sistare > --- > include/sysemu/seccomp.h | 1 + > system/qemu-seccomp.c| 10 -- > system/vl.c | 6 ++

Re: [PATCH v3] target/i386: Fix CPUID encoding of Fn8000001E_ECX

2024-05-10 Thread Michael Tokarev
09.05.2024 17:11, Daniel P. Berrangé wrote: On Thu, May 09, 2024 at 04:54:16PM +0300, Michael Tokarev wrote: 03.05.2024 20:46, Babu Moger wrote: diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 08c7de416f..46235466d7 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -81,6 +81,7 @@ GlobalProper

Re: [PATCH v3] target/i386: Fix CPUID encoding of Fn8000001E_ECX

2024-05-10 Thread Daniel P . Berrangé
On Fri, May 10, 2024 at 11:05:44AM +0300, Michael Tokarev wrote: > 09.05.2024 17:11, Daniel P. Berrangé wrote: > > On Thu, May 09, 2024 at 04:54:16PM +0300, Michael Tokarev wrote: > > > 03.05.2024 20:46, Babu Moger wrote: > > > > > diff --git a/hw/i386/pc.c b/hw/i386/pc.c > > > > index 08c7de416f.

Re: [PULL 05/26] hw/remote/vfio-user: Fix config space access byte order

2024-05-10 Thread Michael Tokarev
08.05.2024 20:44, Philippe Mathieu-Daudé wrote: From: Mattias Nissler PCI config space is little-endian, so on a big-endian host we need to perform byte swaps for values as they are passed to and received from the generic PCI config space access machinery. Is this a material for stable? Than

Re: [PATCH v4 03/12] libvhost-user: mask F_INFLIGHT_SHMFD if memfd is not supported

2024-05-10 Thread Stefano Garzarella
On Wed, May 08, 2024 at 12:39:33PM GMT, Philippe Mathieu-Daudé wrote: On 8/5/24 09:44, Stefano Garzarella wrote: libvhost-user will panic when receiving VHOST_USER_GET_INFLIGHT_FD message if MFD_ALLOW_SEALING is not defined, since it's not able to create a memfd. VHOST_USER_GET_INFLIGHT_FD is u

Re: [PATCH] target/riscv: Remove experimental prefix from "B" extension

2024-05-10 Thread Andrew Jones
On Thu, May 09, 2024 at 02:23:42PM GMT, Daniel Henrique Barboza wrote: > > > On 5/8/24 08:22, Andrew Jones wrote: > > On Tue, May 07, 2024 at 11:27:21AM GMT, Rob Bradford wrote: > > > This extension has now been ratified: > > > https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be > >

Re: [PATCH 1/3] target/riscv: Save counter values during countinhibit update

2024-05-10 Thread Andrew Jones
On Thu, May 09, 2024 at 01:26:56PM GMT, Atish Kumar Patra wrote: > On Thu, May 2, 2024 at 5:39 AM Andrew Jones wrote: > > > > On Tue, Apr 30, 2024 at 03:00:45PM GMT, Daniel Henrique Barboza wrote: > > > > > > > > > On 4/29/24 16:28, Atish Patra wrote: > > > > Currently, if a counter monitoring cyc

Re: [PATCH 3/4] virtio-gpu: use a VMState variant for the scanout field

2024-05-10 Thread Marc-André Lureau
Hi On Wed, May 8, 2024 at 12:01 AM Peter Xu wrote: > > On Tue, May 07, 2024 at 03:19:19PM +0400, marcandre.lur...@redhat.com wrote: > > From: Marc-André Lureau > > > > Depending on the version, use v1 or v2 of the scanout VM state. > > > > Signed-off-by: Marc-André Lureau > > --- > > hw/displa

Re: [PATCH] hw/loongarch/virt.c: Fixes memory leak in ramName during loop iterations

2024-05-10 Thread Philippe Mathieu-Daudé
Hi R. On 9/5/24 15:28, R.Samarasekara wrote: This patch fixes a memory leak in the ramName variable within the hw/loongarch/virt.c file. The leak occurs due to repeated calls to g_strdup_printf within a loop, causing memory allocated for ramName on previous iterations to be unfreed. Signed-off-

Re: [PATCH] target/i386: move prefetch and multi-byte UD/NOP to new decoder

2024-05-10 Thread Zhao Liu
On Thu, May 09, 2024 at 05:37:55PM +0200, Paolo Bonzini wrote: > Date: Thu, 9 May 2024 17:37:55 +0200 > From: Paolo Bonzini > Subject: [PATCH] target/i386: move prefetch and multi-byte UD/NOP to new > decoder > X-Mailer: git-send-email 2.45.0 > > These are trivial to add, and moving them to the

Re: [PATCH v4 08/12] libvhost-user: enable it on any POSIX system

2024-05-10 Thread Stefano Garzarella
On Wed, May 08, 2024 at 12:36:30PM GMT, Philippe Mathieu-Daudé wrote: On 8/5/24 09:44, Stefano Garzarella wrote: The vhost-user protocol is not really Linux-specific so let's enable libvhost-user for any POSIX system. Compiling it on macOS and FreeBSD some problems came up: - avoid to include l

Re: [PATCH v4 09/12] contrib/vhost-user-blk: enable it on any POSIX system

2024-05-10 Thread Stefano Garzarella
On Wed, May 08, 2024 at 12:32:08PM GMT, Philippe Mathieu-Daudé wrote: On 8/5/24 09:44, Stefano Garzarella wrote: Let's make the code more portable by adding defines from block/file-posix.c to support O_DIRECT in other systems (e.g. macOS). vhost-user-server.c is a dependency, let's enable it fo

Re: [PATCH] tests/tcg: cover lzcnt/tzcnt/popcnt

2024-05-10 Thread Zhao Liu
On Thu, May 09, 2024 at 05:25:32PM +0200, Paolo Bonzini wrote: > Date: Thu, 9 May 2024 17:25:32 +0200 > From: Paolo Bonzini > Subject: [PATCH] tests/tcg: cover lzcnt/tzcnt/popcnt > X-Mailer: git-send-email 2.45.0 > > Signed-off-by: Paolo Bonzini > --- > tests/tcg/i386/test-i386.c | 25

[PATCH] tcg/loongarch64: Fill out tcg_out_{ld,st} for vector regs

2024-05-10 Thread Richard Henderson
TCG register spill/fill uses tcg_out_ld/st with all types, not necessarily going through INDEX_op_{ld,st}_vec. Cc: qemu-sta...@nongnu.org Fixes: 16288ded944 ("tcg/loongarch64: Lower basic tcg vec ops to LSX") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2336 Signed-off-by: Richard Hende

Re: [PATCH 13/13] tests/qtest: arm: fix operation in a build without any boards or devices

2024-05-10 Thread Philippe Mathieu-Daudé
On 9/5/24 19:00, Paolo Bonzini wrote: ARM/aarch64 are easy to fix because they already have to pass a machine type by hand. Just guard the tests with a check that the machine actually exists. Signed-off-by: Paolo Bonzini --- tests/qtest/arm-cpu-features.c | 4 tests/qtest/migration-tes

Re: [PULL 0/8] s390x and misc patches

2024-05-10 Thread Richard Henderson
On 5/10/24 08:39, Thomas Huth wrote: The following changes since commit 36fa7c686e9eac490002ffc439c4affaa352c17c: gitlab: Update msys2-64bit runner tags (2024-05-09 05:46:21 +0200) are available in the Git repository at: https://gitlab.com/thuth/qemu.git tags/pull-request-2024-05-10 fo

Re: [PATCH 03/13] s390: move css_migration_enabled from machine to css.c

2024-05-10 Thread Paolo Bonzini
On Fri, May 10, 2024 at 7:38 AM Thomas Huth wrote: > I think this is wrong: By adding this to ccw_machine_2_9_class_options the > variable now always gets set to false, even for newer machines, since the > *class_options functions are part of the "class_init" which is always done. > You have to ad

Re: [PATCH] target/i386: fix operand size for DATA16 REX.W POPCNT

2024-05-10 Thread Richard Henderson
On 5/9/24 17:25, Paolo Bonzini wrote: According to the manual, 32-bit vs 64-bit is governed by REX.W and REX ignores the 0x66 prefix. This can be confirmed with this program: #include int main() { int x = 0x1234; int y; asm("popcntl %1, %0" : "=r" (y)

Re: [PATCH] target/i386: rdpkru/wrpkru are no-prefix instructions

2024-05-10 Thread Richard Henderson
On 5/9/24 17:25, Paolo Bonzini wrote: Reject 0x66/0xf3/0xf2 in front of them. Cc:qemu-sta...@nongnu.org Signed-off-by: Paolo Bonzini --- target/i386/tcg/translate.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PATCH v4 10/12] hostmem: add a new memory backend based on POSIX shm_open()

2024-05-10 Thread Stefano Garzarella
On Wed, May 08, 2024 at 01:59:33PM GMT, Markus Armbruster wrote: Stefano Garzarella writes: shm_open() creates and opens a new POSIX shared memory object. A POSIX shared memory object allows creating memory backend with an associated file descriptor that can be shared with external processes (

Re: [PATCH] target/i386: move prefetch and multi-byte UD/NOP to new decoder

2024-05-10 Thread Richard Henderson
On 5/9/24 17:37, Paolo Bonzini wrote: +[0x18] = X86_OP_ENTRY1(NOP, nop,v), /* prefetch/reserved NOP */ +[0x19] = X86_OP_ENTRY1(NOP, nop,v), /* reserved NOP */ +[0x1c] = X86_OP_ENTRY1(NOP, nop,v), /* reserved NOP */ +[0x1d] = X86_OP_ENTRY1(NOP, nop,v), /* reserved NOP */ +

Re: [PATCH v2 18/33] disas: Split disas.c

2024-05-10 Thread Richard Henderson
On 5/8/24 17:26, Philippe Mathieu-Daudé wrote: @@ -2,13 +2,17 @@   #define QEMU_DISAS_H   /* Disassemble this for me please... (debugging). */ +#ifdef CONFIG_TCG   void disas(FILE *out, const void *code, size_t size);   void target_disas(FILE *out, CPUState *cpu, uint64_t code, size_t size); +#en

Re: [PULL 05/26] hw/remote/vfio-user: Fix config space access byte order

2024-05-10 Thread Philippe Mathieu-Daudé
On 10/5/24 10:18, Michael Tokarev wrote: 08.05.2024 20:44, Philippe Mathieu-Daudé wrote: From: Mattias Nissler PCI config space is little-endian, so on a big-endian host we need to perform byte swaps for values as they are passed to and received from the generic PCI config space access machine

Re: [PATCH v4 08/12] libvhost-user: enable it on any POSIX system

2024-05-10 Thread Philippe Mathieu-Daudé
On 10/5/24 10:56, Stefano Garzarella wrote: On Wed, May 08, 2024 at 12:36:30PM GMT, Philippe Mathieu-Daudé wrote: On 8/5/24 09:44, Stefano Garzarella wrote: The vhost-user protocol is not really Linux-specific so let's enable libvhost-user for any POSIX system. Alternatively add in subproje

Re: [RFC PATCH v3 3/5] KVM: x86: Add notifications for Heki policy configuration and violation

2024-05-10 Thread Nicolas Saenz Julienne
On Tue May 7, 2024 at 4:16 PM UTC, Sean Christopherson wrote: > > If yes, that would indeed require a *lot* of work for something we're not > > sure will be accepted later on. > > Yes and no. The AWS folks are pursuing VSM support in KVM+QEMU, and SVSM > support > is trending toward the paired VM

Re: [PATCH] tcg/loongarch64: Fill out tcg_out_{ld, st} for vector regs

2024-05-10 Thread gaosong
在 2024/5/10 下午5:12, Richard Henderson 写道: TCG register spill/fill uses tcg_out_ld/st with all types, not necessarily going through INDEX_op_{ld,st}_vec. Cc: qemu-sta...@nongnu.org Fixes: 16288ded944 ("tcg/loongarch64: Lower basic tcg vec ops to LSX") Resolves: https://gitlab.com/qemu-project/qem

Re: [PATCH 06/13] xen: initialize legacy backends from xen_bus_init()

2024-05-10 Thread Philippe Mathieu-Daudé
On 9/5/24 19:00, Paolo Bonzini wrote: Prepare for moving the calls to xen_be_register() under the control of xen_bus_init(), using the normal xen_backend_init() method that is used by the "modern" backends. This requires the xenstore global variable to be initialized, which is done by xen_be_ini

Re: [RFC QEMU PATCH v9 1/2] virtio-pci: only reset pm state during resetting

2024-05-10 Thread Michael S. Tsirkin
On Tue, Apr 16, 2024 at 03:01:26PM +0800, Jiqian Chen wrote: > Fix bug imported by 27ce0f3afc9dd25d21b43bbce505157afd93d111 > (fix Power Management Control Register for PCI Express virtio devices) should be: 27ce0f3afc9dd ("fix Power Management Control Register for PCI Express virtio devices"

Re: [PATCH 3/4] virtio-gpu: use a VMState variant for the scanout field

2024-05-10 Thread Michael S. Tsirkin
On Tue, May 07, 2024 at 03:19:19PM +0400, marcandre.lur...@redhat.com wrote: > From: Marc-André Lureau > > Depending on the version, use v1 or v2 of the scanout VM state. > > Signed-off-by: Marc-André Lureau > --- > hw/display/virtio-gpu.c | 22 +- > 1 file changed, 17 inse

Re: [PATCH 1/6] virtio: Add bool to VirtQueueElement

2024-05-10 Thread Jonah Palmer
On 5/9/24 8:32 AM, Eugenio Perez Martin wrote: On Mon, May 6, 2024 at 5:06 PM Jonah Palmer wrote: Add the boolean 'filled' member to the VirtQueueElement structure. The use of this boolean will signify if the element has been written to the used / descriptor ring or not. This boolean is use

Re: [PATCH v3] block: Use LVM tools for LV block device truncation

2024-05-10 Thread Alexander Ivanov
ping Is there any update of the patch status? Thank you. On 3/15/24 09:58, Alexander Ivanov wrote: If a block device is an LVM logical volume we can resize it using standard LVM tools. Add a helper to detect if a device is a DM device. In raw_co_truncate() check if the block device is DM and

Re: [PATCH v2 09/15] hw/riscv/riscv-iommu: add s-stage and g-stage support

2024-05-10 Thread Frank Chang
Hi Daniel, Daniel Henrique Barboza 於 2024年3月8日 週五 上午12:09寫道: > > From: Tomasz Jeznach > > Add support for s-stage (sv32, sv39, sv48, sv57 caps) and g-stage > (sv32x4, sv39x4, sv48x4, sv57x4 caps). Most of the work is done in the > riscv_iommu_spa_fetch() function that now has to consider how man

Re: [PATCH v8 01/11] linux-headers: Update to Linux v6.9-rc3

2024-05-10 Thread Alex Bennée
Dmitry Osipenko writes: > Update kernel headers to get new VirtIO-GPU capsets, in particular the > Venus capset. > > Signed-off-by: Huang Rui > Signed-off-by: Dmitry Osipenko > --- > hw/i386/x86.c | 8 - > include/standard-headers/asm-x86/bootparam.h | 17 +-

Re: [RFC PATCH 0/1] pci: allocate a PCI ID for RISC-V IOMMU

2024-05-10 Thread Frank Chang
Hi Daniel, Daniel Henrique Barboza 於 2024年5月8日 週三 下午8:42寫道: > > > > On 5/7/24 12:44, Peter Maydell wrote: > > On Fri, 3 May 2024 at 13:43, Daniel Henrique Barboza > > wrote: > >> > >> Hi, > >> > >> In this RFC I want to check with Gerd and others if it's ok to add a PCI > >> id for the RISC-V IO

[PATCH v2 0/7] hw/xen: Simplify legacy backends handling

2024-05-10 Thread Philippe Mathieu-Daudé
Respin of Paolo's Xen patches from https://lore.kernel.org/qemu-devel/20240509170044.190795-1-pbonz...@redhat.com/ rebased on one of my cleanup branches making backend structures const. Treat xenfb as other backends. Paolo Bonzini (2): hw/xen: initialize legacy backends from xen_bus_init() hw/

[PATCH v2 2/7] hw/xen: Constify XenLegacyDevice::XenDevOps

2024-05-10 Thread Philippe Mathieu-Daudé
XenDevOps @ops is not updated, mark it const. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/xen/xen_pvdev.h | 2 +- hw/xen/xen-legacy-backend.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/hw/xen/xen_pvdev.h b/include/hw/xen/xen_pvdev.h index ddad4b9f36.

[PATCH v2 3/7] hw/xen: Constify xenstore_be::XenDevOps

2024-05-10 Thread Philippe Mathieu-Daudé
XenDevOps @ops is not updated, mark it const. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/xen/xen-legacy-backend.h | 2 +- hw/xen/xen-legacy-backend.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/hw/xen/xen-legacy-backend.h b/include/hw/xen

[PATCH v2 5/7] hw/xen: initialize legacy backends from xen_bus_init()

2024-05-10 Thread Philippe Mathieu-Daudé
From: Paolo Bonzini Prepare for moving the calls to xen_be_register() under the control of xen_bus_init(), using the normal xen_backend_init() method that is used by the "modern" backends. This requires the xenstore global variable to be initialized, which is done by xen_be_init(). To ensure th

[PATCH v2 4/7] hw/xen: Make XenDevOps structures const

2024-05-10 Thread Philippe Mathieu-Daudé
Keep XenDevOps structures in .rodata. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/xen/xen-legacy-backend.h | 8 hw/9pfs/xen-9p-backend.c| 2 +- hw/display/xenfb.c | 4 ++-- hw/usb/xen-usb.c| 4 ++-- 4 files changed, 9 insertions(

[PATCH v2 6/7] hw/xen: register legacy backends via xen_backend_init

2024-05-10 Thread Philippe Mathieu-Daudé
From: Paolo Bonzini It is okay to register legacy backends in the middle of xen_bus_init(). All that the registration does is record the existence of the backend in xenstore. This makes it possible to remove them from the build without introducing undefined symbols in xen_be_init(). It also rem

[PATCH v2 7/7] hw/xen: Register framebuffer backend via xen_backend_init()

2024-05-10 Thread Philippe Mathieu-Daudé
Align the framebuffer backend with the other legacy ones, register it via xen_backend_init() when '-vga xenfb' is used. It is safe because MODULE_INIT_XEN_BACKEND is called in xen_bus_realize(), long after CLI processing initialized the vga_interface_type variable. Signed-off-by: Philippe Mathieu-

[PATCH v2 1/7] hw/xen: Remove declarations left over in 'xen-legacy-backend.h'

2024-05-10 Thread Philippe Mathieu-Daudé
'xen_blkdev_ops' was removed in commit 19f87870ba ("xen: remove the legacy 'xen_disk' backend"), 'xen_netdev_ops' in commit 25967ff69f ("hw/xen: update Xen PV NIC to XenDevice model") and 'xen_console_ops' in commit 9b77374690 ("hw/xen: update Xen console to XenDevice model"). Remove them. Signed-

Re: [PATCH 07/13] xen: register legacy backends via xen_backend_init

2024-05-10 Thread Philippe Mathieu-Daudé
On 9/5/24 19:00, Paolo Bonzini wrote: It is okay to register legacy backends in the middle of xen_bus_init(). All that the registration does is record the existence of the backend in xenstore. This makes it possible to remove them from the build without introducing undefined symbols in xen_be_in

Re: [PATCH 2/6] virtio: virtqueue_pop - VIRTIO_F_IN_ORDER support

2024-05-10 Thread Jonah Palmer
On 5/9/24 9:13 AM, Eugenio Perez Martin wrote: On Mon, May 6, 2024 at 5:06 PM Jonah Palmer wrote: Add VIRTIO_F_IN_ORDER feature support in virtqueue_split_pop and virtqueue_packed_pop. VirtQueueElements popped from the available/descritpor ring are added to the VirtQueue's used_elems array

Re: [PATCH v2 6/7] hw/xen: register legacy backends via xen_backend_init

2024-05-10 Thread Philippe Mathieu-Daudé
On 10/5/24 12:49, Philippe Mathieu-Daudé wrote: From: Paolo Bonzini It is okay to register legacy backends in the middle of xen_bus_init(). All that the registration does is record the existence of the backend in xenstore. This makes it possible to remove them from the build without introducin

Re: [PATCH v4 11/12] tests/qtest/vhost-user-blk-test: use memory-backend-shm

2024-05-10 Thread Philippe Mathieu-Daudé
On 8/5/24 09:44, Stefano Garzarella wrote: `memory-backend-memfd` is available only on Linux while the new `memory-backend-shm` can be used on any POSIX-compliant operating system. Let's use it so we can run the test in multiple environments. Signed-off-by: Stefano Garzarella --- tests/qtest/

Re: [PATCH v8 07/11] virtio-gpu: Support suspension of commands processing

2024-05-10 Thread Akihiko Odaki
On 2024/05/09 21:39, Dmitry Osipenko wrote: On 5/5/24 09:37, Akihiko Odaki wrote: On 2024/05/02 4:02, Dmitry Osipenko wrote: On 4/27/24 08:48, Akihiko Odaki wrote: The VIRTIO_GPU_FILL_CMD() macro returns void and this macro is used by every function processing commands. Changing process_cmd()

Re: [PATCH v2 03/15] hw/riscv: add RISC-V IOMMU base emulation

2024-05-10 Thread Frank Chang
Hi Daniel, Daniel Henrique Barboza 於 2024年5月8日 週三 下午7:16寫道: > > Hi Frank, > > I'll reply with that I've done so far. Still missing some stuff: > > On 5/2/24 08:37, Frank Chang wrote: > > Hi Daniel, > > > > Daniel Henrique Barboza 於 2024年3月8日 週五 > > 上午12:04寫道: > >> > >> From: Tomasz Jeznach > >

Re: [PATCH v2 11/15] hw/riscv/riscv-iommu: add DBG support

2024-05-10 Thread Frank Chang
Hi Daniel, Daniel Henrique Barboza 於 2024年5月6日 週一 下午9:06寫道: > > Hi Frank, > > On 5/6/24 01:09, Frank Chang wrote: > > Hi Daniel, > > > > Daniel Henrique Barboza 於 2024年3月8日 週五 > > 上午12:05寫道: > >> > >> From: Tomasz Jeznach > >> > >> DBG support adds three additional registers: tr_req_iova, tr_r

Re: [PATCH v2 02/15] hw/riscv: add riscv-iommu-bits.h

2024-05-10 Thread Frank Chang
Reviewed-by: Frank Chang Daniel Henrique Barboza 於 2024年3月8日 週五 上午12:07寫道: > > From: Tomasz Jeznach > > This header will be used by the RISC-V IOMMU emulation to be added > in the next patch. Due to its size it's being sent in separate for > an easier review. > > One thing to notice is that thi

Re: [PATCH] target/i386: fix operand size for DATA16 REX.W POPCNT

2024-05-10 Thread Zhao Liu
On Thu, May 09, 2024 at 05:25:26PM +0200, Paolo Bonzini wrote: > Date: Thu, 9 May 2024 17:25:26 +0200 > From: Paolo Bonzini > Subject: [PATCH] target/i386: fix operand size for DATA16 REX.W POPCNT > X-Mailer: git-send-email 2.45.0 > > According to the manual, 32-bit vs 64-bit is governed by REX.

Re: [PATCH] target/riscv: Remove experimental prefix from "B" extension

2024-05-10 Thread Daniel Henrique Barboza
On 5/10/24 05:29, Andrew Jones wrote: On Thu, May 09, 2024 at 02:23:42PM GMT, Daniel Henrique Barboza wrote: On 5/8/24 08:22, Andrew Jones wrote: On Tue, May 07, 2024 at 11:27:21AM GMT, Rob Bradford wrote: This extension has now been ratified: https://jira.riscv.org/browse/RVS-2006 so the

Re: [PATCH v2 09/15] hw/riscv/riscv-iommu: add s-stage and g-stage support

2024-05-10 Thread Andrew Jones
On Fri, May 10, 2024 at 06:36:51PM GMT, Frank Chang wrote: ... > > static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, RISCVIOMMUContext > > *ctx, > > -IOMMUTLBEntry *iotlb) > > +IOMMUTLBEntry *iotlb, bool gpa) > > { > > +dma_addr_t addr, base; > > +uint64_t satp, gatp, pte; > >

Re: [PATCH v2 00/15] riscv: QEMU RISC-V IOMMU Support

2024-05-10 Thread Frank Chang
Hi Daniel, Thanks for the upstream work. Sorry that it took a while for me to review the patchset. Please let me know if you need any help from us to update the IOMMU model. We would like to see it merged for QEMU 9.1.0. Regards, Frank Chang Daniel Henrique Barboza 於 2024年3月8日 週五 上午12:04寫道: >

[RFC PATCH] scripts/update-linux-header.sh: be more src tree friendly

2024-05-10 Thread Alex Bennée
Running "install_headers" in the Linux source tree is fairly unfriendly as out-of-tree builds will start complaining about the kernel source being non-pristine. As we have a temporary directory for the install we should also do the build step here. So now we have: $tmpdir/ $blddir/ $hdrd

Re: [PATCH 09/13] i386: pc: remove unnecessary MachineClass overrides

2024-05-10 Thread Zhao Liu
On Thu, May 09, 2024 at 07:00:40PM +0200, Paolo Bonzini wrote: > Date: Thu, 9 May 2024 19:00:40 +0200 > From: Paolo Bonzini > Subject: [PATCH 09/13] i386: pc: remove unnecessary MachineClass overrides > X-Mailer: git-send-email 2.45.0 > > There is no need to override these fields of MachineClass

Re: [PATCH 3/4] virtio-gpu: use a VMState variant for the scanout field

2024-05-10 Thread Marc-André Lureau
Hi Michael On Fri, May 10, 2024 at 2:26 PM Michael S. Tsirkin wrote: > > On Tue, May 07, 2024 at 03:19:19PM +0400, marcandre.lur...@redhat.com wrote: > > From: Marc-André Lureau > > > > Depending on the version, use v1 or v2 of the scanout VM state. > > > > Signed-off-by: Marc-André Lureau > >

Re: [PATCH 08/13] i386: correctly select code in hw/i386 that depends on other components

2024-05-10 Thread Zhao Liu
On Thu, May 09, 2024 at 07:00:39PM +0200, Paolo Bonzini wrote: > Date: Thu, 9 May 2024 19:00:39 +0200 > From: Paolo Bonzini > Subject: [PATCH 08/13] i386: correctly select code in hw/i386 that depends > on other components > X-Mailer: git-send-email 2.45.0 > > fw_cfg.c and vapic.c are currently

Re: [PATCH 3/6] virtio: virtqueue_ordered_fill - VIRTIO_F_IN_ORDER support

2024-05-10 Thread Jonah Palmer
On 5/9/24 10:08 AM, Eugenio Perez Martin wrote: On Mon, May 6, 2024 at 5:05 PM Jonah Palmer wrote: Add VIRTIO_F_IN_ORDER feature support for virtqueue_fill operations. The goal of the virtqueue_fill operation when the VIRTIO_F_IN_ORDER feature has been negotiated is to search for this now-

Re: [PATCH 10/13] hw/i386: split x86.c in multiple parts

2024-05-10 Thread Zhao Liu
On Thu, May 09, 2024 at 07:00:41PM +0200, Paolo Bonzini wrote: > Date: Thu, 9 May 2024 19:00:41 +0200 > From: Paolo Bonzini > Subject: [PATCH 10/13] hw/i386: split x86.c in multiple parts > X-Mailer: git-send-email 2.45.0 > > Keep the basic X86MachineState definition in x86.c. Move out function

Re: [PATCH 11/13] hw/i386: move rtc-reset-reinjection command out of hw/rtc

2024-05-10 Thread Zhao Liu
On Thu, May 09, 2024 at 07:00:42PM +0200, Paolo Bonzini wrote: > Date: Thu, 9 May 2024 19:00:42 +0200 > From: Paolo Bonzini > Subject: [PATCH 11/13] hw/i386: move rtc-reset-reinjection command out of > hw/rtc > X-Mailer: git-send-email 2.45.0 > > The rtc-reset-reinjection QMP command is specifi

Re: [PATCH 12/13] i386: select correct components for no-board build

2024-05-10 Thread Zhao Liu
On Thu, May 09, 2024 at 07:00:43PM +0200, Paolo Bonzini wrote: > Date: Thu, 9 May 2024 19:00:43 +0200 > From: Paolo Bonzini > Subject: [PATCH 12/13] i386: select correct components for no-board build > X-Mailer: git-send-email 2.45.0 > > The local APIC is a part of the CPU and has callbacks that

Re: [PATCH v5 00/32] Misc PPC exception and BookE MMU clean ups

2024-05-10 Thread BALATON Zoltan
On Thu, 9 May 2024, BALATON Zoltan wrote: This series does some further clean up mostly around BookE MMU to untangle it from other MMU models. It also contains some other changes that I've come up with while working on this. The Simplify ppc_booke_xlate() part 1 and part 2 patches could be squash

Re: [PATCH v14 0/6] ui/console: Private QemuDmaBuf struct

2024-05-10 Thread Marc-André Lureau
Hi On Wed, May 8, 2024 at 10:01 PM wrote: > > From: Dongwon Kim > > This series introduces privacy enhancements to the QemuDmaBuf struct > and its contained data to bolster security. it accomplishes this by > introducing of helper functions for allocating, deallocating, and > accessing individua

Re: [PATCH] target/i386: remove PCOMMIT from TCG, deprecate property

2024-05-10 Thread Zhao Liu
On Wed, May 08, 2024 at 05:44:21PM +0200, Paolo Bonzini wrote: > Date: Wed, 8 May 2024 17:44:21 +0200 > From: Paolo Bonzini > Subject: [PATCH] target/i386: remove PCOMMIT from TCG, deprecate property > X-Mailer: git-send-email 2.45.0 > > The PCOMMIT instruction was never included in any physical

Re: [PATCH 6/7] target/ppc: Remove unused struct 'mmu_ctx_hash32'

2024-05-10 Thread BALATON Zoltan
On Sun, 5 May 2024, BALATON Zoltan wrote: On Sun, 5 May 2024, Dr. David Alan Gilbert wrote: I think it's use was removed by Commit 5883d8b296 ("mmu-hash*: Don't use full ppc_hash{32, 64}_translate() path for get_phys_page_debug()") Signed-off-by: Dr. David Alan Gilbert Reviewed-by: BALATON Z

Re: [PATCH 6/7] target/ppc: Remove unused struct 'mmu_ctx_hash32'

2024-05-10 Thread Dr. David Alan Gilbert
* BALATON Zoltan (bala...@eik.bme.hu) wrote: > On Sun, 5 May 2024, BALATON Zoltan wrote: > > On Sun, 5 May 2024, Dr. David Alan Gilbert wrote: > > > I think it's use was removed by > > > Commit 5883d8b296 ("mmu-hash*: Don't use full ppc_hash{32, > > > 64}_translate() path for get_phys_page_debug()"

Re: [PATCH 4/6] virtio: virtqueue_ordered_flush - VIRTIO_F_IN_ORDER support

2024-05-10 Thread Jonah Palmer
On 5/10/24 3:48 AM, Eugenio Perez Martin wrote: On Mon, May 6, 2024 at 5:06 PM Jonah Palmer wrote: Add VIRTIO_F_IN_ORDER feature support for virtqueue_flush operations. The goal of the virtqueue_flush operation when the VIRTIO_F_IN_ORDER feature has been negotiated is to write elements to

[PATCH v3 2/5] block/mirror: replace is_none_mode with sync_mode in MirrorBlockJob struct

2024-05-10 Thread Fiona Ebner
It is more flexible and is done in preparation to support specifying a working bitmap for mirror jobs. In particular, this makes it possible to assert that @sync_mode=full when a bitmap is used. That assertion is just to be sure, of course the mirror QMP commands will be made to fail earlier with a

[PATCH v3 3/5] mirror: allow specifying working bitmap

2024-05-10 Thread Fiona Ebner
From: John Snow for the mirror job. The bitmap's granularity is used as the job's granularity. The new @bitmap parameter is marked unstable in the QAPI and can currently only be used for @sync=full mode. Clusters initially dirty in the bitmap as well as new writes are copied to the target. Usi

[PATCH 0/5] target/riscv: Support RISC-V privilege 1.13 spec

2024-05-10 Thread Fea.Wang
Based on the change log for the RISC-V privilege 1.13 spec, add the support for ss1p13. Ref:https://github.com/riscv/riscv-isa-manual/blob/a7d93c9/src/priv-preface.adoc?plain=1#L40-L72 Lists what to do without clarification or document format. * Redefined misa.MXL to be read-only, making MXLEN a

[PATCH 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0

2024-05-10 Thread Fea.Wang
Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in SMSTATEEN0 that controls access to the hedeleg. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 10 ++ 2 files changed, 11 insertions(+) diff --git a/targ

[PATCH 5/5] target/riscv: Reserve exception codes for sw-check and hw-err

2024-05-10 Thread Fea.Wang
Based on the priv-1.13.0, add the exception codes for Software-check and Hardware-error. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang --- target/riscv/cpu_bits.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index f888025c59..f037f72

[PATCH v3 4/5] iotests: add test for bitmap mirror

2024-05-10 Thread Fiona Ebner
From: Fabian Grünbichler heavily based on/practically forked off iotest 257 for bitmap backups, but: - no writes to filter node 'mirror-top' between completion and finalization, as those seem to deadlock? - extra set of reference/test mirrors to verify that writes in parallel with active mirror

[PATCH v3 1/5] qapi/block-core: avoid the re-use of MirrorSyncMode for backup

2024-05-10 Thread Fiona Ebner
Backup supports all modes listed in MirrorSyncMode, while mirror does not. Introduce BackupSyncMode by copying the current MirrorSyncMode and drop the variants mirror does not support from MirrorSyncMode as well as the corresponding manual check in mirror_start(). A consequence is also tighter int

[PATCH v3 0/5] mirror: allow specifying working bitmap

2024-05-10 Thread Fiona Ebner
Changes from v2 (discussion here [2]): * Cluster size caveats only apply to non-COW diff image, adapt the cluster size check and documentation accordingly. * In the IO test, use backing files (rather than stand-alone diff images) in combination with copy-mode=write-blocking and larger cluster

[PATCH v3 5/5] blockdev: mirror: check for target's cluster size when using bitmap

2024-05-10 Thread Fiona Ebner
When using mirror with a bitmap and the target does not do COW and is is a diff image, i.e. one that should only contain the delta and was not synced to previously, a too large cluster size for the target can be problematic. In particular, when the mirror sends data to the target aligned to the job

[PATCH 2/5] target/riscv: Support the version for ss1p13

2024-05-10 Thread Fea.Wang
Add RISC-V privilege 1.13 support. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang --- target/riscv/cpu.c | 6 +- target/riscv/cpu.h | 4 +++- target/riscv/cpu_cfg.h | 1 + target/riscv/tcg/tcg-cpu.c | 4 4 files changed, 13 insertions(+), 2 deletions(-) diff --gi

Problem with bypass iommu

2024-05-10 Thread Aaron Lu
Hi, When bypass iommu is used together with split irqchip, during boot, kernel would dump 2 callstacks(see attached) and the results are pci devices attached to root bus will fall back to using IOAPIC instead of MSIx. This problem was initally noticed by Juro. This only happens with kernel-irqchi

[PATCH 4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32

2024-05-10 Thread Fea.Wang
Based on privileged spec 1.13, the RV32 needs to implement MEDELEGH and HEDELEGH for exception codes 32-47 for reserving and exception codes 48-63 for custom use. Add the CSR number though the implementation is just reading zero and writing ignore. Besides, for accessing HEDELEGH, it should be cont

[PATCH 1/5] target/riscv: Reuse the conversion function of priv_spec and string

2024-05-10 Thread Fea.Wang
From: Jim Shu Public the conversion function of priv_spec and string in cpu.h, so that tcg-cpu.c could also use it. Signed-off-by: Jim Shu Signed-off-by: Fea.Wang Reviewed-by: Frank Chang --- target/riscv/cpu.c | 4 ++-- target/riscv/cpu.h | 3 +++ target/riscv/tcg/tcg-cpu.

Re: [PATCH v6 4/7] migration/multifd: add qpl compression method

2024-05-10 Thread Fabiano Rosas
Yuan Liu writes: > add the Query Processing Library (QPL) compression method > > Introduce the qpl as a new multifd migration compression method, it can > use In-Memory Analytics Accelerator(IAA) to accelerate compression and > decompression, which can not only reduce network bandwidth requiremen

[PATCH v2 2/2] ppc/pnv: Implement ADU access to LPC space

2024-05-10 Thread Nicholas Piggin
One of the functions of the ADU is indirect memory access engines that send and receive data via ADU registers. This implements the ADU LPC memory access functionality sufficiently for IBM proprietary firmware to access the UART and print characters to the serial port as it does on real hardware.

[PATCH v2 1/2] ppc/pnv: Begin a more complete ADU LPC model for POWER9/10

2024-05-10 Thread Nicholas Piggin
This implements a framework for an ADU unit model. The ADU unit actually implements XSCOM, which is the bridge between MMIO and PIB. However it also includes control and status registers and other functions that are exposed as PIB (xscom) registers. To keep things simple, pnv_xscom.c remains the

[PATCH v2 0/2] ppc/pnv: ADU model for POWER9/10

2024-05-10 Thread Nicholas Piggin
These patches adds the framework for a proper ADU model rather than putting registers into the xscom default ops, and implements ADU's indirect LPC access functionality which IBM's proprietary firmware uses to provide consoles on UARTs. Patch 1 should be quite a simple hooking up the xscom address

[PATCH 2/3] hw/arm: Connect OTP device to BCM2835

2024-05-10 Thread Rayhan Faizel
Signed-off-by: Rayhan Faizel --- hw/arm/bcm2835_peripherals.c | 13 - include/hw/arm/bcm2835_peripherals.h | 3 ++- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c index 1695d8b453..7d735bb56c 100644

[PATCH 1/3] hw/nvram: Add BCM2835 OTP device

2024-05-10 Thread Rayhan Faizel
The OTP device registers are currently stubbed. For now, the device houses the OTP rows which will be accessed directly by other peripherals. Signed-off-by: Rayhan Faizel --- hw/nvram/bcm2835_otp.c | 187 + hw/nvram/meson.build | 1 + include/h

[PATCH 0/3] Initial support for One-Time Programmable Memory (OTP) in BCM2835

2024-05-10 Thread Rayhan Faizel
All BCM2835 boards have on-board OTP memory with 66 32-bit rows. Usually, its contents are accessible via mailbox commands. Rayhan Faizel (3): hw/nvram: Add BCM2835 OTP device hw/arm: Connect OTP device to BCM2835 hw/misc: Implement mailbox properties for customer OTP and device specific

[PATCH 3/3] hw/misc: Implement mailbox properties for customer OTP and device specific private keys

2024-05-10 Thread Rayhan Faizel
Four mailbox properties are implemented as follows: 1. Customer OTP: GET_CUSTOMER_OTP and SET_CUSTOMER_OTP 2. Device-specific private key: GET_PRIVATE_KEY and SET_PRIVATE_KEY. The customer OTP is located in the rows 36-43. The device-specific private key is located in the rows 56-63. The customer

RE: [PATCH v6 4/7] migration/multifd: add qpl compression method

2024-05-10 Thread Liu, Yuan1
> -Original Message- > From: Fabiano Rosas > Sent: Friday, May 10, 2024 10:12 PM > To: Liu, Yuan1 ; pet...@redhat.com > Cc: qemu-devel@nongnu.org; Liu, Yuan1 ; Zou, Nanhai > > Subject: Re: [PATCH v6 4/7] migration/multifd: add qpl compression method > > Yuan Liu writes: > > > add the Q

[PATCH] ppc/pnv: Implement POWER9 LPC PSI serirq outputs and auto-clear function

2024-05-10 Thread Nicholas Piggin
The POWER8 LPC ISA device irqs all get combined and reported to the line connected the PSI LPCHC irq. POWER9 changed this so only internal LPC host controller irqs use that line, and the device irqs get routed to 4 new lines connected to PSI SERIRQ0-3. POWER9 also introduced a new feature that aut

Re: [PATCH V8 1/8] accel/kvm: Extract common KVM vCPU {creation,parking} code

2024-05-10 Thread Philippe Mathieu-Daudé
On 8/5/24 12:46, Salil Mehta wrote: Hi Phillipe, Sorry, I missed this mail earlier. From: Philippe Mathieu-Daudé Sent: Friday, May 3, 2024 7:23 PM To: Salil Mehta ; qemu-devel@nongnu.org; qemu-...@nongnu.org On 3/5/24 17:57, Salil Mehta wrote: > Hi Philippe, > >> From: P

Re: [PATCH 00/45] target/hppa: Misc improvements

2024-05-10 Thread Philippe Mathieu-Daudé
Cc'ing Helge & Sven as I'm going to skip this series. Suggestion: -- >8 -- diff --git a/MAINTAINERS b/MAINTAINERS index 1b79767d61..be7535b55e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -254,6 +254,8 @@ F: target/hexagon/gen_idef_parser_funcs.py HPPA (PA-RISC) TCG CPUs M: Richard Henderson

[PATCH v2 3/4] target/hexagon: idef-parser fix leak of init_list

2024-05-10 Thread Anton Johansson via
gen_inst_init_args() is called for instructions using a predicate as an rvalue. Upon first call, the list of arguments which might need initialization init_list is freed to indicate that they have been processed. For instructions without an rvalue predicate, gen_inst_init_args() isn't called and in

[PATCH v2 2/4] target/hexagon: idef-parser remove undefined functions

2024-05-10 Thread Anton Johansson via
Signed-off-by: Anton Johansson Reviewed-by: Taylor Simpson --- target/hexagon/idef-parser/parser-helpers.h | 13 - 1 file changed, 13 deletions(-) diff --git a/target/hexagon/idef-parser/parser-helpers.h b/target/hexagon/idef-parser/parser-helpers.h index 7c58087169..2087d534a9 100

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