These patches adds the framework for a proper ADU model rather than putting registers into the xscom default ops, and implements ADU's indirect LPC access functionality which IBM's proprietary firmware uses to provide consoles on UARTs.
Patch 1 should be quite a simple hooking up the xscom address space. Patch 2 implements one of the memory access functions of the ADU that drives access to LPC address space from XSCOM register operations which is non-trivial but there are similar examples already in tree. Since v1: - Changed to GPL-2.0-or-later - Added an assertion for adu-lpc link - Renamed funcions to pnv_lpc_opb_ prefix rather than pnv_opb_lpc_ - Removed the unnecessary ADU class Thanks, Nick Nicholas Piggin (2): ppc/pnv: Begin a more complete ADU LPC model for POWER9/10 ppc/pnv: Implement ADU access to LPC space include/hw/ppc/pnv_adu.h | 32 ++++++ include/hw/ppc/pnv_chip.h | 3 + include/hw/ppc/pnv_lpc.h | 5 + include/hw/ppc/pnv_xscom.h | 6 ++ hw/ppc/pnv.c | 20 ++++ hw/ppc/pnv_adu.c | 206 +++++++++++++++++++++++++++++++++++++ hw/ppc/pnv_lpc.c | 12 +-- hw/ppc/pnv_xscom.c | 9 -- hw/ppc/meson.build | 1 + hw/ppc/trace-events | 4 + 10 files changed, 283 insertions(+), 15 deletions(-) create mode 100644 include/hw/ppc/pnv_adu.h create mode 100644 hw/ppc/pnv_adu.c -- 2.43.0
