The TCG-specific code from the system generic cpu_exit()
is equivalent of tcg_cpu_exit(). Define the AccelOpsClass
exit_vcpu_thread() handler to it, making cpu_exit() generic.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/tcg-accel-ops.c | 2 ++
system/cpus.c | 3 ---
2 files c
TaskState is specific to TCG user emulation, move it
to AccelCPUState.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/vcpu-state.h | 6 --
include/hw/core/cpu.h | 2 --
bsd-user/main.c| 2 +-
linux-user/main.c | 2 +-
linux-user/syscall.c | 2 +-
5 files changed, 7 inser
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/translate-all.c | 9 -
accel/tcg/user-exec.c | 8
2 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 83cc14fbde..fdf6d8ac19 100644
--- a/accel/tcg/trans
@jmp_env is specific to TCG accelerator, move it to its AccelCPUState.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/internal-common.h | 1 +
accel/tcg/tcg-accel-ops.h | 1 +
accel/tcg/vcpu-state.h | 2 ++
include/hw/core/cpu.h | 1 -
accel/tcg/cpu-exec-common.c | 2 +-
accel/
Forward declare TaskState in "qemu/typedefs.h" so we can
use it in generic headers like "hw/cpu/core.h".
Signed-off-by: Philippe Mathieu-Daudé
---
bsd-user/qemu.h | 4 ++--
include/qemu/typedefs.h | 1 +
linux-user/qemu.h | 4 ++--
3 files changed, 5 insertions(+), 4 deletions(-)
Keep all user emulation headers under the same user/ directory.
Signed-off-by: Philippe Mathieu-Daudé
---
bsd-user/qemu.h | 2 +-
include/{exec => }/user/thunk.h | 8 ++--
linux-user/user-internals.h | 2 +-
linux-user/thunk.c | 2 +-
4 files changed, 9 inser
While each user emulation implentation defines its own
TaskState structure, both use the same get_task_state()
declaration, in particular in common code (such gdbstub).
Declare the method once in "accel/tcg/vcpu-state.h".
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/vcpu-state.h | 18
@iommu_notifiers is specific to TCG system emulation, move it to
AccelCPUState.
Restrict TCG specific code in system/physmem.c, adding an empty
stub for tcg_register_iommu_notifier().
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/vcpu-state.h | 3 +++
include/hw/core/cpu.h | 3 ---
sys
All user emulation headers are now under include/user/.
Signed-off-by: Philippe Mathieu-Daudé
---
scripts/coverity-scan/COMPONENTS.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/coverity-scan/COMPONENTS.md
b/scripts/coverity-scan/COMPONENTS.md
index 91be8d1c36..1
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 22 ++
include/qemu/plugin.h | 2 +-
accel/tcg/plugin-gen.c | 8 +---
hw/core/cpu-common.c | 2 +-
plugins/core.c | 8
5 files changed, 21 insertions(+), 21 deletions(-)
diff --git
@mem_io_pc is specific to TCG system emulation, move it to
AccelCPUState.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/vcpu-state.h| 3 +++
include/hw/core/cpu.h | 2 --
accel/tcg/cputlb.c| 2 +-
accel/tcg/tcg-accel-ops.c | 1 +
hw/core/cpu-common.c | 1 -
hw/misc/mip
The @can_do_io field got moved from CPUState to
CPUNegativeOffsetState in commit 464dacf609 ("accel/tcg:
Move can_do_io to CPUNegativeOffsetState").
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include
I /think/ this check added in commit 4e4fa6c12d ("accel/tcg:
Complete cpu initialization before registration") is now
unnecessary, but I don't have the WASM reproducer mentioned
in:
https://lore.kernel.org/qemu-devel/20221027141856.w5umjgklawgu7pqv@heavy/
to confirm. Ilya, do you mind testing? If s
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/vcpu-state.h | 7 +++
accel/tcg/tcg-accel-ops-mttcg.c | 2 ++
accel/tcg/tcg-accel-ops-rr.c| 2 ++
3 files changed, 11 insertions(+)
diff --git a/accel/tcg/vcpu-state.h b/accel/tcg/vcpu-state.h
index e407d914df..d0dd1bbff8 10064
Both @icount_budget and @icount_extra fields are specific
to TCG accelerator, move them to its AccelCPUState.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/vcpu-state.h | 4
include/hw/core/cpu.h| 3 ---
accel/tcg/cpu-exec.c | 14 +++---
acc
@tcg_cflags is specific to TCG accelerator, move it to
its AccelCPUState.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/vcpu-state.h | 2 ++
include/hw/core/cpu.h | 4 +---
accel/tcg/cpu-exec.c | 6 +++---
linux-user/main.c | 2 +-
4 files changed, 7 insertions(+), 7 deletions(-)
Get the TaskState pointer calling get_task_state().
Signed-off-by: Philippe Mathieu-Daudé
---
gdbstub/gdbstub.c | 3 ++-
gdbstub/user-target.c | 4 ++--
linux-user/syscall.c | 4 ++--
3 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
index
On 29/4/24 00:08, Richard Henderson wrote:
On 4/28/24 14:49, Philippe Mathieu-Daudé wrote:
cpu_loop_exit_requested() is specific to TCG, move it
to "exec/translate-all.h".
Signed-off-by: Philippe Mathieu-Daudé
---
include/exec/exec-all.h | 17 -
include/exec/translate-a
@tb_jmp_cache is specific to TCG accelerator, move it to
its AccelCPUState.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/tb-jmp-cache.h | 4 ++--
accel/tcg/vcpu-state.h| 2 ++
include/hw/core/cpu.h | 2 --
include/qemu/typedefs.h | 1 -
accel/tcg/cpu-exec.c | 7 +++
ac
So far we don't support icount on user emulation.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/cpu-exec.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 84fd041aec..1f618f6c2e 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cp
IcountDecr union, the CPUTLB* structures and the
"exec/tlb-common.h" header are only required for
TCG.
Signed-off-by: Philippe Mathieu-Daudé
---
include/exec/tlb-common.h | 4
include/hw/core/cpu.h | 9 ++---
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/include/ex
@cflags_next_tb is specific to TCG accelerator, move it to
its AccelCPUState.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/vcpu-state.h| 2 ++
include/hw/core/cpu.h | 1 -
accel/tcg/cpu-exec.c | 12 ++--
accel/tcg/tb-maint.c | 4 ++--
accel/tcg/tcg-accel-ops.c
On 29/4/24 00:14, Philippe Mathieu-Daudé wrote:
Finish extracting TCG fields from CPUState:
- Extract tcg_cpu_exit() from cpu_exit()
- Introduce AccelOpsClass::exit_vcpu_thread()
- cpu_exit() calls exit_vcpu_thread=tcg_cpu_exit for TCG
- Forward declare TaskState and more uses of get_task_state()
Hi,
The KVM/QEMU community call is at:
https://meet.jit.si/kvmcallmeeting
@
30/4/2024 14:00 UTC
Are there any agenda items for the sync-up?
Alex maintains the invite on our Linaro project calendar here:
https://calendar.google.com/calendar/event?action=TEMPLATE&tmeid=MWd2dWI5NDM1bzdocn
The following changes since commit 03555199b63aa1fbce24d16287e141c33f572a24:
net/slirp: Use newer slirp_*_hostxfwd API (2024-04-29 02:04:58 +0200)
are available in the Git repository at:
https://people.debian.org/~sthibault/qemu.git tags/samuel-thibault
for you to fetch changes up to 035551
From: Nicholas Ngai
libslirp provides a newer slirp_*_hostxfwd API meant for
address-agnostic forwarding instead of the is_udp parameter which is
limited to just TCP/UDP.
This paves the way for IPv6 and Unix socket support.
Signed-off-by: Nicholas Ngai
Signed-off-by: Samuel Thibault
Tested-by
Samuel Thibault, le dim. 28 avril 2024 19:23:03 +0200, a ecrit:
> Thomas Weißschuh, le jeu. 22 févr. 2024 11:44:13 +0100, a ecrit:
> > On Tue, Mar 22, 2022 at 06:58:36PM -0700, Nicholas Ngai wrote:
> > > Pinging this. It’s a bit old, though the patch still applies cleanly to
> > > master as far as
On 4/28/24 15:14, Philippe Mathieu-Daudé wrote:
Keep all user emulation headers under the same user/ directory.
Signed-off-by: Philippe Mathieu-Daudé
---
bsd-user/qemu.h | 2 +-
include/{exec => }/user/thunk.h | 8 ++--
linux-user/user-internals.h | 2 +-
linux-user/
On 4/28/24 15:14, Philippe Mathieu-Daudé wrote:
All user emulation headers are now under include/user/.
Signed-off-by: Philippe Mathieu-Daudé
---
scripts/coverity-scan/COMPONENTS.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/coverity-scan/COMPONENTS.md
b/scr
On 4/28/24 15:14, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/translate-all.c | 9 -
accel/tcg/user-exec.c | 8
2 files changed, 8 insertions(+), 9 deletions(-)
Reviewed-by: Richard Henderson
r~
diff --git a/accel/tcg/translat
On 4/28/24 15:14, Philippe Mathieu-Daudé wrote:
We will introduce a per-accelerator vCPU exit() handler
for system emulation. Duplicate cpu_exit() because the
handler won't be accessible from user emulation.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/user-exec.c | 8
hw/cor
On 4/28/24 15:14, Philippe Mathieu-Daudé wrote:
Extract tcg_cpu_exit() from the user cpu_exit() implementation.
In few commits we will re-use it in the system one (via a
per-accel handler).
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/internal-common.h | 2 ++
accel/tcg/translate-all.
On 4/28/24 15:14, Philippe Mathieu-Daudé wrote:
Introduce a per-accelerator handler that can be call
when a vCPU exits.
Signed-off-by: Philippe Mathieu-Daudé
---
include/sysemu/accel-ops.h | 1 +
system/cpus.c | 3 +++
2 files changed, 4 insertions(+)
Reviewed-by: Richard Hen
On 4/28/24 15:14, Philippe Mathieu-Daudé wrote:
The TCG-specific code from the system generic cpu_exit()
is equivalent of tcg_cpu_exit(). Define the AccelOpsClass
exit_vcpu_thread() handler to it, making cpu_exit() generic.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/tcg-accel-ops.c |
On 4/28/24 15:14, Philippe Mathieu-Daudé wrote:
Forward declare TaskState in "qemu/typedefs.h" so we can
use it in generic headers like "hw/cpu/core.h".
Signed-off-by: Philippe Mathieu-Daudé
---
bsd-user/qemu.h | 4 ++--
include/qemu/typedefs.h | 1 +
linux-user/qemu.h | 4 ++-
On 4/28/24 15:14, Philippe Mathieu-Daudé wrote:
While each user emulation implentation defines its own
TaskState structure, both use the same get_task_state()
declaration, in particular in common code (such gdbstub).
Declare the method once in "accel/tcg/vcpu-state.h".
Signed-off-by: Philippe Ma
On 4/28/24 15:14, Philippe Mathieu-Daudé wrote:
Get the TaskState pointer calling get_task_state().
Signed-off-by: Philippe Mathieu-Daudé
---
gdbstub/gdbstub.c | 3 ++-
gdbstub/user-target.c | 4 ++--
linux-user/syscall.c | 4 ++--
3 files changed, 6 insertions(+), 5 deletions(-)
Rev
On Fri, Apr 26, 2024 at 04:32:18PM +0200, Cédric le Goater wrote:
> On 4/26/24 13:00, Aditya Gupta wrote:
> > Make Power11 as default cpu type for 'pseries' and 'powernv' machine type,
> > with Power11 being the newest supported Power processor in QEMU.
>
> This is too early. We should merge Power
On Wed, Apr 24, 2024 at 3:17 PM Zhijian Li (Fujitsu)
wrote:
>
>
> On 24/04/2024 12:52, mii wrote:
> >
> > On 2024/04/24 10:28, Yong Huang wrote:
> >>
> >>
> >> On Tue, Apr 23, 2024 at 9:35 PM Peter Xu wrote:
> >>
> >> On Tue, Apr 23, 2024 at 09:13:08AM +, Masato Imai wrote:
> >> > Wh
On Sun, Apr 28, 2024 at 2:41 AM Michael Tokarev wrote:
>
> 27.04.2024 18:17, Andrew Jones :
> > I wrote instructions [2] for how to cross-compile without a full
> > environment/container once. It might be better for quick, local testing.
> >
> > [2]
> > https://lore.kernel.org/qemu-riscv/2023072
On Thu, Apr 25, 2024 at 12:29 AM Andrew Jones wrote:
>
> Implementing wrs.nto to always just return is consistent with the
> specification, as the instruction is permitted to terminate the
> stall for any reason, but it's not useful for virtualization, where
> we'd like the guest to trap to the hy
On Thu, Apr 25, 2024 at 12:29 AM Andrew Jones wrote:
>
> Implementing wrs.nto to always just return is consistent with the
> specification, as the instruction is permitted to terminate the
> stall for any reason, but it's not useful for virtualization, where
> we'd like the guest to trap to the hy
On Thu, Apr 25, 2024 at 6:26 AM Daniel Henrique Barboza
wrote:
>
> Commit d424db2354 removed an instance of strerrorname_np() because it
> was breaking building with musl libc. A recent RISC-V patch ended up
> re-introducing it again by accident.
>
> Put this function in the baddies list in checkp
On Thu, Apr 25, 2024 at 6:27 AM Daniel Henrique Barboza
wrote:
>
> Commit d424db2354 excluded some strerrorname_np() instances because they
> break musl libc builds. Another instance happened to slip by via commit
> d4ff3da8f4.
>
> Remove it before it causes trouble again.
>
> Fixes: d4ff3da8f4 (t
On Fri, Apr 26, 2024 at 1:51 AM Daniel Henrique Barboza
wrote:
>
> SBI defines a Debug Console extension "DBCN" that will, in time, replace
> the legacy console putchar and getchar SBI extensions.
>
> The appeal of the DBCN extension is that it allows multiple bytes to be
> read/written in the SBI
On Mon, Apr 1, 2024 at 10:44 PM Cheng Yang wrote:
>
> Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
> to set the address of initrd in FDT to support 64-bit address.
>
> Signed-off-by: Cheng Yang
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/riscv/boot.c | 4 ++--
> 1 file
On Thu, Apr 11, 2024 at 9:34 PM Clément Léger wrote:
>
> When icount is enabled, rather than returning the virtual CPU time, we
> should return the instruction count itself. Add an instructions bool
> parameter to get_ticks() to correctly return icount_get_raw() when
> icount_enabled() == 1 and in
在 2024/4/29 上午2:59, Richard Henderson 写道:
On 4/28/24 01:51, Song Gao wrote:
we load initrd ramdisk after kernel_high address
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-Id: <20240426091551.2397867-3-gaos...@loongson.cn>
---
hw/loongarch/boot.c | 29 -
On Mon, Apr 22, 2024 at 11:59 PM Clément Léger wrote:
>
> The current semihost exception number (16) is a reserved number (range
> [16-17]). The upcoming double trap specification uses that number for
> the double trap exception. Since the privileged spec (Table 22) defines
> ranges for custom use
The following changes since commit fd87be1dada5672f877e03c2ca8504458292c479:
Merge tag 'accel-20240426' of https://github.com/philmd/qemu into staging
(2024-04-26 15:28:13 -0700)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240429
for yo
fdt adds pch msi controller, we use 'loongson,pch-msi-1.0'.
See:
https://github.com/torvalds/linux/blob/v6.7/drivers/irqchip/irq-loongson-pch-msi.c
https://lore.kernel.org/r/20200528152757.1028711-6-jiaxun.y...@flygoat.com
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-Id: <2024042609155
Move some boot functions to boot.c and struct
loongarch_boot_info into struct LoongArchMachineState.
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20240426091551.2397867-2-gaos...@loongson.cn>
---
hw/loongarch/boot.c | 128 ++
Add init_systab and set boot_info->a2
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-Id: <20240426091551.2397867-6-gaos...@loongson.cn>
---
hw/loongarch/boot.c | 22 +
include/hw/loongarch/boot.h | 48 +
2 files changed, 70 inse
fdt adds cpu interrupt controller node,
we use 'loongson,cpu-interrupt-controller'.
See:
https://github.com/torvalds/linux/blob/v6.7/drivers/irqchip/irq-loongarch-cpu.c
https://lore.kernel.org/r/20221114113824.1880-2-liupei...@loongson.cn
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-Id
This patch adds pcie irq_map node for FDT.
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-Id: <20240426091551.2397867-15-gaos...@loongson.cn>
---
hw/loongarch/virt.c | 73 ++---
1 file changed, 69 insertions(+), 4 deletions(-)
diff --git a/hw/loon
Add init_cmline and set boot_info->a0, a1
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-Id: <20240426091551.2397867-5-gaos...@loongson.cn>
---
hw/loongarch/boot.c | 30 ++
include/hw/loongarch/virt.h | 2 ++
target/loongarch/cpu.h | 2 ++
3 fil
The right fdt memory node like [1], not [2]
[1]
memory@0 {
device_type = "memory";
reg = <0x00 0x00 0x00 0x1000>;
};
[2]
memory@0 {
device_type = "memory";
reg = <0x02 0x00 0x02 0x1000>;
};
uart node need interrupts and interrupt-parent cells.
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-Id: <20240426091551.2397867-17-gaos...@loongson.cn>
---
hw/loongarch/virt.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch
rtc node need interrupts and interrupt-parent cells.
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-Id: <20240426091551.2397867-18-gaos...@loongson.cn>
---
hw/loongarch/virt.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loonga
fdt adds Extend I/O Interrupt Controller,
we use 'loongson,ls2k2000-eiointc'.
See:
https://github.com/torvalds/linux/blob/v6.7/drivers/irqchip/irq-loongson-eiointc.c
https://lore.kernel.org/r/764e02d924094580ac0f1d15535f4b98308705c6.1683279769.git.zhoubin...@loongson.cn
Signed-off-by: Song Gao
R
This patch removes the unused fdt irqchip node.
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-Id: <20240426091551.2397867-16-gaos...@loongson.cn>
---
hw/loongarch/virt.c | 31 +--
1 file changed, 1 insertion(+), 30 deletions(-)
diff --git a/hw/loongarch/virt
we load initrd ramdisk after kernel_high address
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-Id: <20240426091551.2397867-3-gaos...@loongson.cn>
---
hw/loongarch/boot.c | 28 +++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/hw/loongarch/boot.c
The efi_system_table adds a efi_initrd configuration table.
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-Id: <20240426091551.2397867-8-gaos...@loongson.cn>
---
hw/loongarch/boot.c | 23 +--
include/hw/loongarch/boot.h | 9 +
2 files changed, 30 inse
fdt adds pch pic controller, we use 'loongson,pch-pic-1.0'
See:
https://github.com/torvalds/linux/blob/v6.7/drivers/irqchip/irq-loongson-pch-pic.c
https://lore.kernel.org/r/20200528152757.1028711-4-jiaxun.y...@flygoat.com
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-Id: <20240426091551
Load the slave CPU boot code at pflash0 and set
the slave CPU elf_address to VIRT_FLASH0_BASE.
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-Id: <20240426091551.2397867-4-gaos...@loongson.cn>
---
hw/loongarch/boot.c | 62 -
1 file changed, 61
The efi_system_table adds a efi_fdt configuration table.
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-Id: <20240426091551.2397867-9-gaos...@loongson.cn>
---
hw/loongarch/boot.c | 11 +++
hw/loongarch/virt.c | 6 ++
include/hw/loongarch/boot.h | 4
inc
The efi_system_table adds a efi_boot_memmap configuration table.
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-Id: <20240426091551.2397867-7-gaos...@loongson.cn>
---
hw/loongarch/boot.c | 40 +
hw/loongarch/virt.c | 11 ++
incl
On Mon, Apr 22, 2024 at 11:59 PM Clément Léger wrote:
>
> The current semihost exception number (16) is a reserved number (range
> [16-17]). The upcoming double trap specification uses that number for
> the double trap exception. Since the privileged spec (Table 22) defines
> ranges for custom use
On Tue, Apr 23, 2024 at 3:15 AM Daniel Henrique Barboza
wrote:
>
> Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
> enabled, will fail with a kernel oops SIGILL right at the start. The
> reason is that we can't expose zkr without implementing the SEED CSR.
> Disabling zkr i
On Wed, Apr 17, 2024 at 9:05 AM Daniel Henrique Barboza
wrote:
>
> We're not setting (s/m)tval when triggering breakpoints of type 2
> (mcontrol) and 6 (mcontrol6). According to the debug spec section
> 5.7.12, "Match Control Type 6":
>
> "The Privileged Spec says that breakpoint exceptions that o
On Wed, Apr 17, 2024 at 9:05 AM Daniel Henrique Barboza
wrote:
>
> Privileged spec section 4.1.9 mentions:
>
> "When a trap is taken into S-mode, stval is written with
> exception-specific information to assist software in handling the trap.
> (...)
>
> If stval is written with a nonzero value whe
On Wed, Apr 17, 2024 at 9:05 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> This new version has a change suggested by Richard in v2. No other
> changes made.
>
> Changes from v2:
> - patch 2:
> - use tcg_constant_tl() instead of loading a temp and doing a
> movi_tl()
> - v2 link:
> https://
For the following events (ARM IHI 0070 F.b - 7.3 Event records):
- F_TRANSLATION
- F_ACCESS
- F_PERMISSION
- F_ADDR_SIZE
If fault occurs at stage 2, S2 == 1 and:
- If translating an IPA for a transaction (whether by input to
stage 2-only configuration, or after successful stage 1 translation
Currently, QEMU supports emulating either stage-1 or stage-2 SMMUs
but not nested instances.
This patch series adds support for nested translation in SMMUv3,
this is controlled by property “arm-smmuv3.stage=nested”, and
advertised to guests as (IDR0.S1P == 1 && IDR0.S2P == 2)
Main changes(architec
This patch adds support for nested(combined) TLB entries.
The main function combine_tlb() is not used here but in the next
patches, but to simplify the patches it is introduced first.
Main changes:
1) New entry added in the TLB, parent_perm, for nested TLB, holds the
stage-2 permission, this ca
Use the new SMMU property to make the SMMU OAS match the CPU PARANGE.
That's according to SMMU manual ARM IHI 0070F.b:
6.3.6 SMMU_IDR5, OAS must match the system physical address size.
Signed-off-by: Mostafa Saleh
---
hw/arm/virt.c | 14 --
target/arm/cpu.h | 2 ++
target
smmuv3_translate() does everything from STE/CD parsing to TLB lookup
and PTW.
Soon, when nesting is supported, stage-1 data (tt, CD) needs to be
translated using stage-2.
Split smmuv3_translate() to 3 functions:
- smmu_translate(): in smmu-common.c, which does the TLB lookup, PTW,
TLB insertio
On Mon, Apr 15, 2024 at 4:53 PM Yong-Xuan Wang wrote:
>
> The hart bit setting is different with Linux AIA driver[1] when the number
> of hart is power of 2. For example, when the guest has 4 harts, the
> estimated result of AIA driver is 2, whereas we pass 3 to RISC-V/KVM. Since
> only 2 bits are
The SMMUv3 spec (ARM IHI 0070 F.b - 7.3 Event records) defines the
class of events faults as:
CLASS: The class of the operation that caused the fault:
- 0b00: CD, CD fetch.
- 0b01: TTD, Stage 1 translation table fetch.
- 0b10: IN, Input address
However, this value was not set and left as 0 which
QEMU doesn's support memory attributes, so FWB is NOP, this
might change in the future if memory attributre would be supported.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmuv3.c | 8
1 file changed, 8 insertions(+)
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 88f6473d33..8a11e41
In the previous patch, comine_tlb() was added which combines 2 TLB
entries into one, which chooses the granule and level from the
smallest entry.
This means that a nested translation, an entry can be cached with the
granule of stage-2 and not stage-1.
However, the lookup for an IOVA in nested con
IOMMUTLBEvent only understands IOVA, for stage-2 only SMMUs keep
the implementation, while only notify for stage-1 invalidation
in case of nesting.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmuv3.c | 23 +++
hw/arm/trace-events | 2 +-
2 files changed, 16 insertions(+), 9
When nested translation is requested, do the following:
- Translate stage-1 IPA using stage-2 to a physical address.
- Translate stage-1 table walks using stage-2.
- Combine both to create a single TLB entry using the logic
introduced before.
For stage-1 table translation, the spec (ARM IHI 007
With nesting, we would need to invalidate IPAs without
over-invalidating stage-1 IOVAs. This can be done by
distinguishing IPAs in the TLBs by having ASID=-1.
To achieve that, rework the invalidation for IPAs to have a
separate function, while for IOVA invalidation ASID=-1 means
invalidate for all
Everything is in place, add the last missing bits:
- Handle fault checking according to the actual PTW event and not the
the translation stage.
- Consolidate parsing of STE cfg and setting translation stage.
Advertise nesting if stage requested is "nested".
Signed-off-by: Mostafa Saleh
---
hw
Currently, translation stage is represented as an int, where 1 is stage-1 and
2 is stage-2, when nested is added, 3 would be confusing to represent nesting,
so we use an enum instead.
While keeping the same values, this is useful for:
- Doing tricks with bit masks, where BIT(0) is stage-1 and BIT
Add property that sets the OAS of the SMMU, this in not used in this
patch.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmuv3-internal.h | 3 ++-
hw/arm/smmuv3.c | 29 -
include/hw/arm/smmuv3.h | 1 +
3 files changed, 31 insertions(+), 2 deletions(-)
diff --
SMMUv3 OAS is hardcoded to 44 bits, for nested configurations that
can be a problem as stage-2 might be shared with the CPU which might
have different PARANGE, and according to SMMU manual ARM IHI 0070F.b:
6.3.6 SMMU_IDR5, OAS must match the system physical address size.
This patch doesn't cha
From: Jeuk Kim
It fixes the buffer overflow vulnerability in the ufs device.
The bug was detected by sanitizers.
You can reproduce it by:
cat << EOF |\
qemu-system-x86_64 \
-display none -machine accel=qtest -m 512M -M q35 -nodefaults -drive \
file=null-co://,if=none,id=disk0 -device ufs,id=ufs
From: Jeuk Kim
The following changes since commit fd87be1dada5672f877e03c2ca8504458292c479:
Merge tag 'accel-20240426' of https://github.com/philmd/qemu into staging
(2024-04-26 15:28:13 -0700)
are available in the Git repository at:
https://gitlab.com/jeuk20.kim/qemu.git tags/pull-ufs-20
Some commands need rework for nesting, as they used to assume S1
and S2 are mutually exclusive:
- CMD_TLBI_NH_ASID: Consider VMID if stage-2 is supported
- CMD_TLBI_NH_ALL: Consider VMID if stage-2 is supported, otherwise
invalidate everything, this required a new vmid invalidation
function fo
According to the SMMU architecture specification (ARM IHI 0070 F.b),
in “3.4 Address sizes”
The address output from the translation causes a stage 1 Address Size
fault if it exceeds the range of the effective IPA size for the given CD.
However, this check was missing.
There is already a s
ASID and VMID used to be uint16_t in the translation config, however,
in other contexts they can be int as -1 in case of TLB invalidation,
to represent all(don’t care).
When stage-2 was added asid was set to -1 in stage-2 and vmid to -1
in stage-1 configs. However, that meant they were set as (6553
According to ARM SMMU architecture specification (ARM IHI 0070 F.b),
In "5.2 Stream Table Entry":
[51:6] S1ContextPtr
If Config[1] == 1 (stage 2 enabled), this pointer is an IPA translated by
stage 2 and the programmed value must be within the range of the IAS.
In "5.4.1 CD notes":
The transla
On Mon, Apr 22, 2024 at 4:53 PM Christoph Müllner
wrote:
>
> The th.sxstatus CSR can be used to identify available custom extension
> on T-Head CPUs. The CSR is documented here:
>
> https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc
>
> An important property of
On Thu, Mar 28, 2024 at 12:25 PM Jason Chien wrote:
>
> This patch series adds the support for Zve32x and Zvx64x and makes vector
> registers visible in GDB if any of the V/Zve*/Zvk* extensions is enabled.
>
> v2:
> Rebase onto riscv-to-apply.next (commit 385e575).
> v3:
> Spuash patch 2 i
On Mon, Mar 25, 2024 at 12:18 PM Huang Tao wrote:
>
> In RVV and vcrypto instructions, the masked and tail elements are set to 1s
> using vext_set_elems_1s function if the vma/vta bit is set. It is the element
> agnostic policy.
>
> However, this function can't deal the big endian situation. This
On Thu, Mar 14, 2024 at 7:23 PM Huang Tao wrote:
>
> In this patch, we modify the decoder to be a freely composable data
> structure instead of a hardcoded one. It can be dynamically builded up
> according to the extensions.
> This approach has several benefits:
> 1. Provides support for heterogen
On Fri, Mar 15, 2024 at 11:09 PM Sunil V L wrote:
>
> To test ACPI tables, edk2 needs to be booted with a disk image having
> EFI partition. This image is created using UefiTestToolsPkg.
Can we document exactly how this is generated?
Alistair
>
> Signed-off-by: Sunil V L
> ---
> .../bios-tabl
On Fri, Mar 15, 2024 at 11:09 PM Sunil V L wrote:
>
> Existing AARCH64 virt test functions do not have AARCH64 in their name.
> To add RISC-V virt related test cases, better to rename existing
> functions to indicate they are ARM only.
>
> Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
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