Re: [PATCH] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63

[Alistair Francis]

On Mon, Apr 22, 2024 at 11:59 PM Clément Léger <cle...@rivosinc.com> wrote:
>
> The current semihost exception number (16) is a reserved number (range
> [16-17]). The upcoming double trap specification uses that number for
> the double trap exception. Since the privileged spec (Table 22) defines
> ranges for custom uses change the semihosting exception number to 63
> which belongs to the range [48-63] in order to avoid any future
> collisions with reserved exception.
>
> Signed-off-by: Clément Léger <cle...@rivosinc.com>

Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>

Alistair

>
> ---
>  target/riscv/cpu_bits.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index fc2068ee4d..74318a925c 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -670,11 +670,11 @@ typedef enum RISCVException {
>      RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
>      RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
>      RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
> -    RISCV_EXCP_SEMIHOST = 0x10,
>      RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
>      RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
>      RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
>      RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
> +    RISCV_EXCP_SEMIHOST = 0x3f,
>  } RISCVException;
>
>  #define RISCV_EXCP_INT_FLAG                0x80000000
> --
> 2.43.0
>
>