From: aidaleuc
Signed-off-by: aidaleuc
---
qga/commands-common-ssh.c | 50 +++
qga/commands-common-ssh.h | 10
qga/commands-posix-ssh.c | 47 +---
qga/meson.build | 1 +
4 files changed, 62 insertions(+), 4
From: aidaleuc
Signed-off-by: aidaleuc
---
qga/commands-windows-ssh.c | 712 +
qga/commands-windows-ssh.h | 26 ++
qga/meson.build| 7 +-
qga/qapi-schema.json | 17 +-
4 files changed, 750 insertions(+), 12 deletions(-)
create mode 1006
Am 20.04.24 um 07:40 schrieb Mark Cave-Ayland:
> On 20/04/2024 02:21, Richard Henderson wrote:
>
>> On 4/19/24 12:51, Mark Cave-Ayland wrote:
>>> The various Intel CPU manuals claim that SGDT and SIDT can write
>>> either 24-bits
>>> or 32-bits depending upon the operand size, but this is incorrect
On Wed, Apr 17, 2024 at 09:33:33PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> We leak global_filename, and do not close global_file. Let's fix that.
What is the goal?
Leaking global_filename does not cause unbounded memory consumption. I
guess the goal in freeing global_filename is to keep leak
On 4/22/24 10:45, Daniel Henrique Barboza wrote:
Palmer, Anup,
On 4/22/24 10:58, Clément Léger wrote:
The current semihost exception number (16) is a reserved number (range
[16-17]). The upcoming double trap specification uses that number for
the double trap exception. Since the privileged spec
On 4/22/24 16:44, Richard Henderson wrote:
On 4/22/24 10:45, Daniel Henrique Barboza wrote:
Palmer, Anup,
On 4/22/24 10:58, Clément Léger wrote:
The current semihost exception number (16) is a reserved number (range
[16-17]). The upcoming double trap specification uses that number for
the d
Signed-off-by: Bernhard Beschow
---
hw/i386/pc_sysfw.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/i386/pc_sysfw.c b/hw/i386/pc_sysfw.c
index 3efabbbab2..87b5bf59d6 100644
--- a/hw/i386/pc_sysfw.c
+++ b/hw/i386/pc_sysfw.c
@@ -41,8 +41,7 @@
#define FLASH_SECTOR_SIZ
In the -bios case the "isa-bios" memory region is an alias to the BIOS mapped
to the top of the 4G memory boundary. Do the same in the -pflash case to have
common behavior. This also makes pflash commands work in the "isa-bios" region
which some real-world legacy bioses rely on.
Note that in the s
Now that the -bios and -pflash code paths work the same it is possible to have a
common implementation.
While at it convert the magic number 0x10 (== 1MiB) to increase readability.
Signed-off-by: Bernhard Beschow
---
include/hw/i386/x86.h | 2 ++
hw/i386/pc_sysfw.c| 28
This series changes the "isa-bios" MemoryRegion to be an alias rather than a
copy in the pflash case. This fixes issuing pflash commands in the isa-bios
region which matches real hardware and which some real-world legacy bioses I'm
running rely on. Furthermore, aliasing in the isa-bios area is alre
Given that memory_region_set_readonly() is a no-op when the readonlyness is
already as requested it is possible to simplify the pattern
if (condition) {
foo(true);
}
to
foo(condition);
which is shorter and allows to see the invariant of the code more easily.
Signed-off-by: Bernhard B
On Mon, 22 Apr 2024 17:20, Philippe Mathieu-Daudé
wrote:
Since VirtIO devices can change endianness at runtime,
we need to use the device endianness, not the target
one.
Cc: qemu-sta...@nongnu.org
Fixes: eb9ad377bb ("virtio-sound: handle control messages and streams")
Signed-off-by: Philippe Ma
On 22/4/24 19:09, Richard Henderson wrote:
On 4/22/24 10:07, Richard Henderson wrote:
For cpus using PMSA, when the MPU is disabled, the default memory
type is Normal, Non-cachable.
Fixes: 59754f85ed3 ("target/arm: Do memory type alignment check when
translation disabled")
Reported-by: Clémen
On Mon, Apr 22, 2024 at 04:20:56PM +0200, Philippe Mathieu-Daudé wrote:
> Since VirtIO devices can change endianness at runtime,
> we need to use the device endianness, not the target
> one.
>
> Cc: qemu-sta...@nongnu.org
> Fixes: eb9ad377bb ("virtio-sound: handle control messages and streams")
>
On 22/4/24 23:02, Michael S. Tsirkin wrote:
On Mon, Apr 22, 2024 at 04:20:56PM +0200, Philippe Mathieu-Daudé wrote:
Since VirtIO devices can change endianness at runtime,
we need to use the device endianness, not the target
one.
Cc: qemu-sta...@nongnu.org
Fixes: eb9ad377bb ("virtio-sound: handl
On Mon, Apr 22, 2024 at 11:07:21PM +0200, Philippe Mathieu-Daudé wrote:
> On 22/4/24 23:02, Michael S. Tsirkin wrote:
> > On Mon, Apr 22, 2024 at 04:20:56PM +0200, Philippe Mathieu-Daudé wrote:
> > > Since VirtIO devices can change endianness at runtime,
> > > we need to use the device endianness,
The VIRTIO Sound Device conforms with the Virtio spec v1.2,
thus only use little endianness.
Remove the suspicious target_words_bigendian() noticed during
code review.
Cc: qemu-sta...@nongnu.org
Fixes: eb9ad377bb ("virtio-sound: handle control messages and streams")
Signed-off-by: Philippe Mathie
From: Breno Leitao
commit 059a49aa2e25c58f90b50151f109dd3c4cdb3a47 upstream.
There is a bug when setting the RSS options in virtio_net that can break
the whole machine, getting the kernel into an infinite loop.
Running the following command in any QEMU virtual machine with virtionet
will reprod
Ping.
I would appreciate comments on this series. Thanks,
Yong
On Mon, Apr 8, 2024 at 8:08 PM Hyman Huang wrote:
> This patchset fixes the crash of VMs configured with the CDROM device
> on the destination during live migration. See the commit message for
> details.
>
> The previous patchset do
On Mon, Apr 22, 2024 at 12:38 PM John Snow wrote:
>
> On Mon, Apr 22, 2024 at 5:20 AM Markus Armbruster wrote:
> >
> > John Snow writes:
> >
> > > On Fri, Apr 19, 2024, 10:45 AM Markus Armbruster
> > > wrote:
> > >
> > >> John Snow writes:
> > >>
> > >> > This series adds a new qapi-domain ex
From: Dongwon Kim
'fence_fd' needs to be validated always before being referenced
And the passing condition should include '== 0' as 0 is a valid
value for the file descriptor.
Suggested-by: Marc-André Lureau
Cc: Philippe Mathieu-Daudé
Cc: Daniel P. Berrangé
Cc: Vivek Kasireddy
Signed-off-by
From: Dongwon Kim
To complete privatizing process of QemuDmaBuf, QemuDmaBuf struct def
is moved to dmabuf.c
Suggested-by: Marc-André Lureau
Cc: Philippe Mathieu-Daudé
Cc: Daniel P. Berrangé
Cc: Vivek Kasireddy
Signed-off-by: Dongwon Kim
---
include/ui/dmabuf.h | 19 +--
ui/
From: Dongwon Kim
This series introduces privacy enhancements to the QemuDmaBuf struct
and its contained data to bolster security. it accomplishes this by
introducing of helper functions for allocating, deallocating, and
accessing individual fields within the struct and replacing all direct
refer
From: Dongwon Kim
This commit updates all occurrences where these fields were
set directly have been updated to utilize helper functions.
v7: removed prefix, "dpy_gl_" from all helpers
v8: Introduction of helpers was removed as those were already added
by the previous commit
Suggested-by:
From: Dongwon Kim
New header and source files are added for containing QemuDmaBuf struct
definition and newly introduced helpers for creating/freeing the struct
and accessing its data.
v10: Change the license type for both dmabuf.h and dmabuf.c from MIT to
GPL to be in line with QEMU's defa
From: Dongwon Kim
This commit introduces utility functions for the creation and deallocation
of QemuDmaBuf instances. Additionally, it updates all relevant sections
of the codebase to utilize these new utility functions.
v7: remove prefix, "dpy_gl_" from all helpers
qemu_dmabuf_free() return
From: Dongwon Kim
This commit updates all instances where fields within the QemuDmaBuf
struct are directly accessed, replacing them with calls to these new
helper functions.
v6: fix typos in helper names in ui/spice-display.c
v7: removed prefix, "dpy_gl_" from all helpers
v8: Introduction of h
On 22/04/2024 19:03, Philippe Mathieu-Daudé wrote:
> On 22/4/24 17:52, CLEMENT MATHIEU--DRIF wrote:
>> The 'level' field in vtd_iotlb_key is an uint8_t.
>> We don't need to store level as an int in vtd_lookup_iotlb
>>
>> Signed-off-by: Clément Mathieu--Drif
>> ---
>> hw/i386/intel_iommu.c | 2 +
On 22/04/2024 18:59, Philippe Mathieu-Daudé wrote:
> On 22/4/24 17:52, CLEMENT MATHIEU--DRIF wrote:
>> This piece of code can be shared by both IOTLB invalidation and
>> PASID-based IOTLB invalidation
>>
>> Signed-off-by: Clément Mathieu--Drif
>> ---
>> hw/i386/intel_iommu.c | 57 ++
On Tue, Apr 9, 2024 at 11:46 AM yang.zhang wrote:
>
> From: "yang.zhang"
>
> Since only root APLICs can have hw IRQ lines, aplic->parent should
> be initialized first.
>
> Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
> Reviewed-by: Daniel Henrique Barboza
> Signed-off-by:
+ qemu-devel
On 4/23/24 11:40, Harsh Prateek Bora wrote:
On ppc64, the PowerVM hypervisor runs with limited memory and a VCPU
creation during hotplug may fail during kvm_ioctl for KVM_CREATE_VCPU,
leading to termination of guest since errp is set to &error_fatal while
calling kvm_init_vcpu. This
Moving the following instructions to decodetree :
mul{ld, ldo, hd, hdu}[.]: XO-form
madd{hd, hdu, ld} : VA-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,o
The handler methods for divw[u] instructions internally use Rc(ctx->opcode),
for extraction of Rc field of instructions, which poses a problem if we move
the above said instructions to decodetree, as the ctx->opcode field is not
popluated in decodetree. Hence, making it decodetree compatible, so th
Moving the following instructions to decodetree specification :
mulli : D-form
mul{lw, lwo, hw, hwu}[.]: XO-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the
Moving the following instructions to decodetree specification :
cmp{rb, eqb}, t{w, d} : X-form
t{w, d}i: D-form
isel: A-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, whic
Moving the below instructions to decodetree specification :
divd[u, e, eu][o][.]: XO-form
mod{sd, ud} : X-form
With this patch, all the fixed-point arithmetic instructions have been
moved to decodetree.
The changes were verified by validating that the tcg ops gener
Moving all fixed-point instructions of the following type to decodetree
specification : arithmetic, compare, trap, select and logical.
Change log :
v2 : Implemented code clean-ups as per comments by Richard in
patches 1/8, 5/8 and 7/8 of v1.
v1 :
https://lore.kernel.org/qemu-devel/202404160
Moving the below instructions to decodetree specification :
andi[s]., {ori, xori}[s]: D-form
{and, andc, nand, or, orc, nor, xor, eqv}[.],
exts{b, h, w}[.], cnt{l, t}z{w, d}[.],
popcnt{b, w, d}, prty{w, d}, cmp, bpermd : X-form
With
Moving the following instructions to decodetree specification :
divw[u, e, eu][o][.] : XO-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
Review
Moving the below instructions to decodetree specification :
neg[o][.] : XO-form
mod{sw, uw}, darn : X-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag
+ Nick
Hi Salil,
I have posted a patch [1] for ppc which based on this refactoring patch.
I see there were some comments from Vishnu on this patch.
Are we expecting any further updates on this patch before merge?
Thanks
Harsh
[1]
https://lore.kernel.org/qemu-devel/a0f9b2fc-4c8a-4c37-bc36-26bba
On Mon, Apr 22, 2024 at 9:25 PM wrote:
> From: aidaleuc
>
> Signed-off-by: aidaleuc
> ---
> qga/commands-windows-ssh.c | 712 +
> qga/commands-windows-ssh.h | 26 ++
> qga/meson.build| 7 +-
> qga/qapi-schema.json | 17 +-
> 4 files cha
Hi Everyone,
We see few features like movdiri, movdiri64b, cldemote are present on
SapphireRapid nodes and are also mentioned as supported in intel manual. But
these are missing from the QEMU definition of SapphireRapid CPUs
https://github.com/qemu/qemu/commit/7eb061b06e97af9a8da7f31b839d78997
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