Re: [PATCH v8 2/6] ui/console: new dmabuf.h and dmabuf.c for QemuDmaBuf struct and helpers

2024-04-22 Thread Daniel P . Berrangé
On Fri, Apr 19, 2024 at 11:59:48AM -0700, dongwon@intel.com wrote: > From: Dongwon Kim > > New header and source files are added for containing QemuDmaBuf struct > definition and newly introduced helpers for creating/freeing the struct > and accessing its data. > > Suggested-by: Marc-André L

Re: [PATCH 0/3] Remove useless architecture prefix from the CPU list

2024-04-22 Thread Daniel P . Berrangé
On Sat, Apr 20, 2024 at 07:46:03AM +0200, Thomas Huth wrote: > Printing an architecture prefix in front of each CPU name is not helpful > at all: It is confusing for the users since they don't know whether they > have to specify these letters for the "-cpu" parameter, too, and it also > takes some

Re: [PATCH v4] target/riscv/kvm/kvm-cpu.c: kvm_riscv_handle_sbi() fail with vendor-specific SBI

2024-04-22 Thread Andrew Jones
On Mon, Apr 22, 2024 at 01:55:31PM +1000, Alistair Francis wrote: > On Sat, Apr 13, 2024 at 9:26 PM Alexei Filippov > wrote: > > > > kvm_riscv_handle_sbi() may return not supported return code to not trigger > > qemu abort with vendor-specific sbi. > > > > Added SBI related return code's defines.

Re: [PATCH 0/3] Remove useless architecture prefix from the CPU list

2024-04-22 Thread Thomas Huth
On 22/04/2024 10.03, Daniel P. Berrangé wrote: On Sat, Apr 20, 2024 at 07:46:03AM +0200, Thomas Huth wrote: Printing an architecture prefix in front of each CPU name is not helpful at all: It is confusing for the users since they don't know whether they have to specify these letters for the "-cp

Re: [PATCH 0/3] hw/cxl/cxl-cdat: Make cxl_doe_cdat_init() return boolean

2024-04-22 Thread Jonathan Cameron via
On Fri, 19 Apr 2024 17:40:07 +0200 Philippe Mathieu-Daudé wrote: > On 18/4/24 12:04, Zhao Liu wrote: > > From: Zhao Liu > > > > --- > > Zhao Liu (3): > >hw/cxl/cxl-cdat: Make ct3_load_cdat() return boolean > >hw/cxl/cxl-cdat: Make ct3_build_cdat() return boolean > >hw/cxl/cxl-cda

[PATCH] backends/cryptodev-builtin: Fix local_error leaks

2024-04-22 Thread Li Zhijian via
It seems that this error does not need to be propagated to the upper, directly output the error to avoid the leaks Closes: https://gitlab.com/qemu-project/qemu/-/issues/2283 Signed-off-by: Li Zhijian --- backends/cryptodev-builtin.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-)

Re: [RFC 1/2] iova_tree: add an id member to DMAMap

2024-04-22 Thread Eugenio Perez Martin
On Sat, Apr 20, 2024 at 1:50 AM Si-Wei Liu wrote: > > > > On 4/19/2024 1:29 AM, Eugenio Perez Martin wrote: > > On Thu, Apr 18, 2024 at 10:46 PM Si-Wei Liu wrote: > >> > >> > >> On 4/10/2024 3:03 AM, Eugenio Pérez wrote: > >>> IOVA tree is also used to track the mappings of virtio-net shadow > >>

Re: [PATCH 3/6] target/s390x/cpu_models: Make kvm_s390_get_host_cpu_model() return boolean

2024-04-22 Thread Zhao Liu
On Fri, Apr 19, 2024 at 11:08:22AM +0200, Philippe Mathieu-Daudé wrote: > Date: Fri, 19 Apr 2024 11:08:22 +0200 > From: Philippe Mathieu-Daudé > Subject: Re: [PATCH 3/6] target/s390x/cpu_models: Make > kvm_s390_get_host_cpu_model() return boolean > > On 19/4/24 10:44, Zhao Liu wrote: > > Hi Thom

Re: [PATCH v6 0/2] Implement SSH commands in QEMU GA for Windows

2024-04-22 Thread Konstantin Kostiuk
Hi Aidan, I tried these patches with OpenSSH Server installed from Windows Features and public key authorization does not work. Guest OS Windows Server 2022. Do you expect to use OpenSSH from Windows Features or not? As OpenSSH Server is a build feature for Server 2022 and new versions of Windows

Re: [PATCH 17/24] exec: Include missing 'qemu/log-for-trace.h' header in 'exec/log.h'

2024-04-22 Thread Philippe Mathieu-Daudé
On 21/4/24 18:44, Richard Henderson wrote: On 4/18/24 12:25, Philippe Mathieu-Daudé wrote: "exec/log.h" accesses the qemu_loglevel variable, which is declared in "qemu/log-for-trace.h". Signed-off-by: Philippe Mathieu-Daudé ---   include/exec/log.h | 1 +   1 file changed, 1 insertion(+) diff

Re: [PATCH 00/27] Add qapi-domain Sphinx extension

2024-04-22 Thread Markus Armbruster
John Snow writes: > On Fri, Apr 19, 2024, 10:45 AM Markus Armbruster wrote: > >> John Snow writes: >> >> > This series adds a new qapi-domain extension for Sphinx, which adds a >> > series of custom directives for documenting QAPI definitions. >> > >> > GitLab CI: https://gitlab.com/jsnow/qemu/

Re: Support Apple Silicon acceleration for x86 / x86_64 guests

2024-04-22 Thread Philippe Mathieu-Daudé
(Cc'ing Cameron in case someone at Apple can help) & @osy86 @rth7680 @agraf @akihiko.odaki My understanding is binaries need to be signed to enable TSO (like Rosetta 2), but as an open source project we can not sign the qemu-system-x86_64 binary, thus QEMU can't use TSO. IIUC we did the best

Re: [PATCH] vhost-user-test: no set non-blocking for cal fd less than 0.

2024-04-22 Thread Gavin Liu
Hi Michael, Thomas The reason is I want to merge this patch: https://lore.kernel.org/all/seypr06mb67561abd83633689b5037395ec...@seypr06mb6756.apcprd06.prod.outlook.com/ Compilation errors occur during CI : stderr: ** ERROR:../tests/qtest/vhost-user-test.c:4

Re: [PATCH] backends/cryptodev-builtin: Fix local_error leaks

2024-04-22 Thread Philippe Mathieu-Daudé
On 22/4/24 10:53, Li Zhijian wrote: It seems that this error does not need to be propagated to the upper, directly output the error to avoid the leaks Closes: https://gitlab.com/qemu-project/qemu/-/issues/2283 Signed-off-by: Li Zhijian --- backends/cryptodev-builtin.c | 9 + 1 file c

Re: [PATCH] target/arm: fix MPIDR value for ARM CPUs with SMT

2024-04-22 Thread Peter Maydell
On Sun, 21 Apr 2024 at 06:40, Richard Henderson wrote: > > --- a/target/arm/cpu.c > > +++ b/target/arm/cpu.c > > @@ -1314,8 +1314,18 @@ static void arm_cpu_dump_state(CPUState *cs, FILE > > *f, int flags) > > } > > } > > > > -uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz) > >

[PATCH v2] tests/unit: Remove debug statements in test-nested-aio-poll.c

2024-04-22 Thread Philippe Mathieu-Daudé
We have been running this test for almost a year; it is safe to remove its debug statements, which clutter CI jobs output: ▶ 88/100 /nested-aio-poll OK io_read 0x16bb26158 io_poll_true 0x16bb26158 > io_poll_ready io_read 0x16bb26164 < io_poll_ready io_poll_true

Re: [PATCH] hw/misc : Correct 5 spaces indents in stm32l4x5_exti

2024-04-22 Thread Philippe Mathieu-Daudé
On 21/4/24 16:14, Inès Varhol wrote: Signed-off-by: Inès Varhol --- hw/misc/stm32l4x5_exti.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) Reviewed-by: Philippe Mathieu-Daudé and queued, thanks!

[PATCH v5] target/riscv/kvm/kvm-cpu.c: kvm_riscv_handle_sbi() fail with vendor-specific sbi.

2024-04-22 Thread Alexei Filippov
kvm_riscv_handle_sbi() may return not supported return code to not trigger qemu abort with vendor-specific sbi. Add new error path to provide proper error in case of qemu_chr_fe_read_all() may not return sizeof(ch). Added SBI related return code's defines. Signed-off-by: Alexei Filippov --- ta

Re: [PATCH] target/arm: fix MPIDR value for ARM CPUs with SMT

2024-04-22 Thread Peter Maydell
On Mon, 22 Apr 2024 at 11:46, Peter Maydell wrote: > > On Sun, 21 Apr 2024 at 06:40, Richard Henderson > wrote: > > > --- a/target/arm/cpu.c > > > +++ b/target/arm/cpu.c > > > @@ -1314,8 +1314,18 @@ static void arm_cpu_dump_state(CPUState *cs, FILE > > > *f, int flags) > > > } > > > } >

Re: [PATCH v5] target/riscv/kvm/kvm-cpu.c: kvm_riscv_handle_sbi() fail with vendor-specific sbi.

2024-04-22 Thread Aleksei Filippov
On 22.04.2024 14:24, Alexei Filippov wrote: kvm_riscv_handle_sbi() may return not supported return code to not trigger qemu abort with vendor-specific sbi. Add new error path to provide proper error in case of qemu_chr_fe_read_all() may not return sizeof(ch). Added SBI related return code's

[PATCH v6] target/riscv/kvm/kvm-cpu.c: kvm_riscv_handle_sbi() fail with vendor-specific SBI

2024-04-22 Thread Alexei Filippov
kvm_riscv_handle_sbi() may return not supported return code to not trigger qemu abort with vendor-specific sbi. Add new error path to provide proper error in case of qemu_chr_fe_read_all() may not return sizeof(ch). Added SBI related return code's defines. Signed-off-by: Alexei Filippov --- Cha

Re: [PATCH 17/24] exec: Include missing 'qemu/log-for-trace.h' header in 'exec/log.h'

2024-04-22 Thread Philippe Mathieu-Daudé
On 22/4/24 11:05, Philippe Mathieu-Daudé wrote: On 21/4/24 18:44, Richard Henderson wrote: On 4/18/24 12:25, Philippe Mathieu-Daudé wrote: "exec/log.h" accesses the qemu_loglevel variable, which is declared in "qemu/log-for-trace.h". Signed-off-by: Philippe Mathieu-Daudé ---   include/exec/lo

Re: [PATCH v7 06/12] hw/mem/cxl_type3: Add host backend and address space handling for DC regions

2024-04-22 Thread Jonathan Cameron via
On Thu, 18 Apr 2024 16:10:57 -0700 nifan@gmail.com wrote: > From: Fan Ni > > Add (file/memory backed) host backend for DCD. All the dynamic capacity > regions will share a single, large enough host backend. Set up address > space for DC regions to support read/write operations to dynamic cap

Re: [PATCH v7 06/12] hw/mem/cxl_type3: Add host backend and address space handling for DC regions

2024-04-22 Thread Jonathan Cameron via
On Fri, 19 Apr 2024 13:27:59 -0400 Gregory Price wrote: > On Thu, Apr 18, 2024 at 04:10:57PM -0700, nifan@gmail.com wrote: > > From: Fan Ni > > > > Add (file/memory backed) host backend for DCD. All the dynamic capacity > > regions will share a single, large enough host backend. Set up addr

Re: [PATCH v7 09/12] hw/cxl/events: Add qmp interfaces to add/release dynamic capacity extents

2024-04-22 Thread Jonathan Cameron via
On Thu, 18 Apr 2024 16:11:00 -0700 nifan@gmail.com wrote: > From: Fan Ni > Hi Fan, Please expand CC list to include QAPI maintainers. +CC Markus and Micheal. Also, for future versions +CC Michael Tsirkin. I'm find rolling these up as a series with the precursors but if it is already some

Re: [PATCH v7 00/12] Enabling DCD emulation support in Qemu

2024-04-22 Thread Jonathan Cameron via
On Sat, 20 Apr 2024 16:35:46 -0400 Gregory Price wrote: > On Fri, Apr 19, 2024 at 11:43:14AM -0700, fan wrote: > > On Fri, Apr 19, 2024 at 02:24:36PM -0400, Gregory Price wrote: > > > > > > added review to all patches, will hopefully be able to add a Tested-by > > > tag early next week, along

Re: [PATCH] pythondeps.toml: warn about updates needed to docs/requirements.txt

2024-04-22 Thread Philippe Mathieu-Daudé
On 18/4/24 11:16, Paolo Bonzini wrote: docs/requirements.txt is expected by readthedocs and should be in sync with pythondeps.toml. Add a comment to both. Signed-off-by: Paolo Bonzini --- docs/requirements.txt | 3 +++ pythondeps.toml | 1 + 2 files changed, 4 insertions(+) Reviewe

Re: [PATCH v6] target/riscv/kvm/kvm-cpu.c: kvm_riscv_handle_sbi() fail with vendor-specific SBI

2024-04-22 Thread Andrew Jones
On Mon, Apr 22, 2024 at 02:42:54PM +0300, Alexei Filippov wrote: > kvm_riscv_handle_sbi() may return not supported return code to not > trigger qemu abort with vendor-specific sbi. > > Add new error path to provide proper error in case of > qemu_chr_fe_read_all() may not return sizeof(ch). I thin

[PATCH] docs/devel: fix minor typo in submitting-a-patch.rst

2024-04-22 Thread Manos Pitsidianakis
s/Resolved:/Resolves:/ Cc: qemu-triv...@nongnu.org Signed-off-by: Manos Pitsidianakis --- docs/devel/submitting-a-patch.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/devel/submitting-a-patch.rst b/docs/devel/submitting-a-patch.rst index c641d948f1..83e9092b8c 1006

Re: [PATCH] docs/devel: fix minor typo in submitting-a-patch.rst

2024-04-22 Thread Peter Maydell
On Mon, 22 Apr 2024 at 13:43, Manos Pitsidianakis wrote: > > s/Resolved:/Resolves:/ > > Cc: qemu-triv...@nongnu.org > Signed-off-by: Manos Pitsidianakis > --- > docs/devel/submitting-a-patch.rst | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/docs/devel/submitting-a-patc

Re: [RFC PATCH-for-8.0 3/3] hw/net/xilinx_ethlite: Replace tswap32() by be32_to_cpu()

2024-04-22 Thread Philippe Mathieu-Daudé
On 13/12/22 14:53, Peter Maydell wrote: On Tue, 13 Dec 2022 at 12:52, Philippe Mathieu-Daudé wrote: This partly revert commit d48751ed4f ("xilinx-ethlite: Simplify byteswapping to/from brams") which states the packet data is stored in big-endian. Signed-off-by: Philippe Mathieu-Daudé @@ -

Re: [PATCH] backends/cryptodev-builtin: Fix local_error leaks

2024-04-22 Thread 皮振伟
Hi, Please add the following message: Fixes: 2fda101de07("virtio-crypto: Support asynchronous mode") LGTM. Reviewed-by: zhenwei pi < pizhen...@bytedance.com> > From:"Li Zhijian" > Date:Mon, Apr 22, 2024, 16:50 > Subject:[External] [PATCH] backends/cryptodev-builtin: Fix local_error leaks > To:< are

[PATCH v1 0/4] virtio_snd_set_config: Fix #2296

2024-04-22 Thread Manos Pitsidianakis
Changing the number of streams via virtio_snd_set_config() did not re-configure the audio card, leaving it in an invalid state. Reported in https://gitlab.com/qemu-project/qemu/-/issues/2296 Manos Pitsidianakis (4): virtio-snd: add virtio_snd_is_config_valid() virtio-snd: factor card setup ou

[PATCH v1 1/4] virtio-snd: add virtio_snd_is_config_valid()

2024-04-22 Thread Manos Pitsidianakis
Factor out virtio_snd_config value validation in a separate function, in order to re-use it in follow up commits. Signed-off-by: Manos Pitsidianakis --- hw/audio/virtio-snd.c | 47 ++- 1 file changed, 29 insertions(+), 18 deletions(-) diff --git a/hw/audi

[PATCH v1 4/4] virtio_snd_set_config: validate and re-setup card

2024-04-22 Thread Manos Pitsidianakis
Validate new configuration values and re-setup audio card. Changing the number of streams via virtio_snd_set_config() did not re-configure the audio card, leaving it in an invalid state. This can be demonstrated by this heap buffer overflow: ```shell cat << EOF | qemu-system-x86_64 -display none

[PATCH v1 2/4] virtio-snd: factor card setup out of realize func

2024-04-22 Thread Manos Pitsidianakis
Extract audio card setup logic out of the device realize callback so that it can be re-used in follow up commits. Signed-off-by: Manos Pitsidianakis --- hw/audio/virtio-snd.c | 72 --- 1 file changed, 41 insertions(+), 31 deletions(-) diff --git a/hw/audi

[PATCH v1 3/4] virtio-snd: factor card removal out of unrealize()

2024-04-22 Thread Manos Pitsidianakis
Extract audio card removal logic out of the device unrealize callback so that it can be re-used in follow up commits. Signed-off-by: Manos Pitsidianakis --- hw/audio/virtio-snd.c | 20 ++-- 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/hw/audio/virtio-snd.c b/hw/

Re: [PATCH 0/3] target/arm: Make the counter frequency default 1GHz for new CPUs, machines

2024-04-22 Thread Peter Maydell
On Fri, 19 Apr 2024 at 19:46, Peter Maydell wrote: > > In previous versions of the Arm architecture, the frequency of the > generic timers as reported in CNTFRQ_EL0 could be any IMPDEF value, > and for QEMU we picked 62.5MHz, giving a timer tick period of 16ns. > In Armv8.6, the architecture stand

[PATCH] hw/arm/npcm7xx: Store derivative OTP fuse key in little endian

2024-04-22 Thread Philippe Mathieu-Daudé
Use little endian for derivative OTP fuse key. Cc: qemu-sta...@nongnu.org Fixes: c752bb079b ("hw/nvram: NPCM7xx OTP device model") Suggested-by: Avi Fishman Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/npcm7xx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/arm/np

Re: [RFC PATCH 1/3] target/riscv: change RISCV_EXCP_SEMIHOST exception number

2024-04-22 Thread Clément Léger
On 22/04/2024 05:25, Alistair Francis wrote: > On Thu, Apr 18, 2024 at 11:40 PM Clément Léger wrote: >> >> The double trap specification defines the double trap exception number >> to be 16 which is actually used by the internal semihosting one. Change >> it to some other value. >> >> Signed-of

[PATCH] hw/audio/virtio-snd: Use device endianness instead of target one

2024-04-22 Thread Philippe Mathieu-Daudé
Since VirtIO devices can change endianness at runtime, we need to use the device endianness, not the target one. Cc: qemu-sta...@nongnu.org Fixes: eb9ad377bb ("virtio-sound: handle control messages and streams") Signed-off-by: Philippe Mathieu-Daudé --- hw/audio/virtio-snd.c | 8 +--- 1 file

Re: [PATCH v3 21/49] i386/sev: Introduce "sev-common" type to encapsulate common SEV state

2024-04-22 Thread Markus Armbruster
Michael Roth writes: > Currently all SEV/SEV-ES functionality is managed through a single > 'sev-guest' QOM type. With upcoming support for SEV-SNP, taking this > same approach won't work well since some of the properties/state > managed by 'sev-guest' is not applicable to SEV-SNP, which will ins

Re: [PATCH] hw/audio/virtio-snd: Use device endianness instead of target one

2024-04-22 Thread Philippe Mathieu-Daudé
On 22/4/24 15:04, Philippe Mathieu-Daudé wrote: Since VirtIO devices can change endianness at runtime, we need to use the device endianness, not the target one. Cc: qemu-sta...@nongnu.org Fixes: eb9ad377bb ("virtio-sound: handle control messages and streams") Signed-off-by: Philippe Mathieu-Daud

[PATCH] target/riscv/kvm: tolerate KVM disable ext errors

2024-04-22 Thread Daniel Henrique Barboza
Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr enabled, will fail with a kernel oops SIGILL right at the start. The reason is that we can't expose zkr without implementing the SEED CSR. Disabling zkr in the guest would be a workaround, but if the KVM doesn't allow it we'll e

[PATCH v2] hw/audio/virtio-snd: Use device endianness instead of target one

2024-04-22 Thread Philippe Mathieu-Daudé
Since VirtIO devices can change endianness at runtime, we need to use the device endianness, not the target one. Cc: qemu-sta...@nongnu.org Fixes: eb9ad377bb ("virtio-sound: handle control messages and streams") Signed-off-by: Philippe Mathieu-Daudé --- hw/audio/virtio-snd.c | 8 +--- 1 file

Re: [PATCH v1 1/4] virtio-snd: add virtio_snd_is_config_valid()

2024-04-22 Thread Philippe Mathieu-Daudé
Hi Manos, On 22/4/24 14:52, Manos Pitsidianakis wrote: Factor out virtio_snd_config value validation in a separate function, in order to re-use it in follow up commits. Signed-off-by: Manos Pitsidianakis --- hw/audio/virtio-snd.c | 47 ++- 1 file chan

Re: [PATCH v1 2/4] virtio-snd: factor card setup out of realize func

2024-04-22 Thread Philippe Mathieu-Daudé
On 22/4/24 14:52, Manos Pitsidianakis wrote: Extract audio card setup logic out of the device realize callback so that it can be re-used in follow up commits. Signed-off-by: Manos Pitsidianakis --- hw/audio/virtio-snd.c | 72 --- 1 file changed, 41 ins

Re: [PATCH v1 3/4] virtio-snd: factor card removal out of unrealize()

2024-04-22 Thread Philippe Mathieu-Daudé
On 22/4/24 14:52, Manos Pitsidianakis wrote: Extract audio card removal logic out of the device unrealize callback so that it can be re-used in follow up commits. Signed-off-by: Manos Pitsidianakis --- hw/audio/virtio-snd.c | 20 ++-- 1 file changed, 14 insertions(+), 6 delet

Re: [PATCH 0/3] target/arm: Make the counter frequency default 1GHz for new CPUs, machines

2024-04-22 Thread Marcin Juszkiewicz
W dniu 22.04.2024 o 14:56, Peter Maydell pisze: On Fri, 19 Apr 2024 at 19:46, Peter Maydell wrote: The upshot is that the only CPU type that changes is 'max'; but any new type we add in future (whether v8.6 or not) will also get the new 1GHz default (assuming we spot in code review any attemp

Re: [PATCH] target/riscv/kvm: tolerate KVM disable ext errors

2024-04-22 Thread Andrew Jones
On Mon, Apr 22, 2024 at 10:12:53AM -0300, Daniel Henrique Barboza wrote: > Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr > enabled, will fail with a kernel oops SIGILL right at the start. The > reason is that we can't expose zkr without implementing the SEED CSR. > Disablin

[PATCH] target/riscv/kvm: Fix exposure of Zkr

2024-04-22 Thread Andrew Jones
The Zkr extension may only be exposed to KVM guests if the VMM implements the SEED CSR. Use the same implementation as TCG. Without this patch, running with a KVM which does not forward the SEED CSR access to QEMU will result in an ILL exception being injected into the guest (this results in Linux

Re: [PATCH v2] hw/audio/virtio-snd: Use device endianness instead of target one

2024-04-22 Thread Manos Pitsidianakis
On Mon, 22 Apr 2024 16:13, Philippe Mathieu-Daudé wrote: Since VirtIO devices can change endianness at runtime, we need to use the device endianness, not the target one. Hey Philippe, can you clarify what do you mean by they can change endianness at runtime? The target's one is used because

Re: [PATCH v3 22/49] i386/sev: Introduce 'sev-snp-guest' object

2024-04-22 Thread Markus Armbruster
Michael Roth writes: > From: Brijesh Singh > > SEV-SNP support relies on a different set of properties/state than the > existing 'sev-guest' object. This patch introduces the 'sev-snp-guest' > object, which can be used to configure an SEV-SNP guest. For example, > a default-configured SEV-SNP gu

[PATCH] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63

2024-04-22 Thread Clément Léger
The current semihost exception number (16) is a reserved number (range [16-17]). The upcoming double trap specification uses that number for the double trap exception. Since the privileged spec (Table 22) defines ranges for custom uses change the semihosting exception number to 63 which belongs to

Re: [PATCH v2 2/6] hw/ppc: SPI controller model - registers implementation

2024-04-22 Thread Cédric Le Goater
On 4/16/24 19:02, Chalapathi V wrote: On 15-04-2024 20:44, Cédric Le Goater wrote: Hello Chalapathi The subject could be rephrased to : "ppc/pnv: Add SPI controller model". On 4/9/24 19:56, Chalapathi V wrote: SPI controller device model supports a connection to a single SPI responder. This

Re: [PATCH] target/riscv/kvm: tolerate KVM disable ext errors

2024-04-22 Thread Daniel Henrique Barboza
On 4/22/24 10:43, Andrew Jones wrote: On Mon, Apr 22, 2024 at 10:12:53AM -0300, Daniel Henrique Barboza wrote: Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr enabled, will fail with a kernel oops SIGILL right at the start. The reason is that we can't expose zkr without

[PATCH v2 1/1] ebpf: Added traces back. Changed source set for eBPF to 'system'.

2024-04-22 Thread Andrew Melnychenko
There was an issue with Qemu build with "--disable-system". The traces could be generated and the build fails. The traces were 'cut out' for previous patches, and overall, the 'system' source set should be used like in pre-'eBPF blob' patches. Signed-off-by: Andrew Melnychenko --- ebpf/ebpf_rss.

Re: [PATCH v2 1/1] ebpf: Added traces back. Changed source set for eBPF to 'system'.

2024-04-22 Thread Andrew Melnichenko
Hello, everyone. Was added missed "trace.h" Best regards. On Mon, Apr 22, 2024 at 5:17 PM Andrew Melnychenko wrote: > > There was an issue with Qemu build with "--disable-system". > The traces could be generated and the build fails. > The traces were 'cut out' for previous patches, and overall,

Re: [PATCH 0/3] target/arm: Make the counter frequency default 1GHz for new CPUs, machines

2024-04-22 Thread Peter Maydell
On Mon, 22 Apr 2024 at 14:38, Marcin Juszkiewicz wrote: > > W dniu 22.04.2024 o 14:56, Peter Maydell pisze: > > On Fri, 19 Apr 2024 at 19:46, Peter Maydell > > wrote: > > >> The upshot is that the only CPU type that changes is 'max'; but any > >> new type we add in future (whether v8.6 or not) w

[PATCH v3] hw/audio/virtio-snd: Use device endianness instead of target one

2024-04-22 Thread Philippe Mathieu-Daudé
Since VirtIO devices can change endianness at runtime, we need to use the device endianness, not the target one. Cc: qemu-sta...@nongnu.org Fixes: eb9ad377bb ("virtio-sound: handle control messages and streams") Signed-off-by: Philippe Mathieu-Daudé --- v2: Use virtio_is_big_endian() v3: Remove "

Re: [PATCH v7 00/12] Enabling DCD emulation support in Qemu

2024-04-22 Thread Jonathan Cameron via
On Mon, 22 Apr 2024 13:04:48 +0100 Jonathan Cameron wrote: > On Sat, 20 Apr 2024 16:35:46 -0400 > Gregory Price wrote: > > > On Fri, Apr 19, 2024 at 11:43:14AM -0700, fan wrote: > > > On Fri, Apr 19, 2024 at 02:24:36PM -0400, Gregory Price wrote: > > > > > > > > added review to all patch

Re: [PATCH v2] hw/audio/virtio-snd: Use device endianness instead of target one

2024-04-22 Thread Philippe Mathieu-Daudé
On 22/4/24 15:45, Manos Pitsidianakis wrote: On Mon, 22 Apr 2024 16:13, Philippe Mathieu-Daudé wrote: Since VirtIO devices can change endianness at runtime, we need to use the device endianness, not the target one. Hey Philippe, can you clarify what do you mean by they can change endianness

Re: [PATCH] target/riscv/kvm: tolerate KVM disable ext errors

2024-04-22 Thread Andrew Jones
On Mon, Apr 22, 2024 at 11:08:31AM -0300, Daniel Henrique Barboza wrote: > > > On 4/22/24 10:43, Andrew Jones wrote: > > On Mon, Apr 22, 2024 at 10:12:53AM -0300, Daniel Henrique Barboza wrote: > > > Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr > > > enabled, will fail w

Re: [PATCH v2 4/6] hw/misc: Microchip's 25CSM04 SEEPROM model

2024-04-22 Thread Cédric Le Goater
Hello Chalapathi On 4/9/24 19:56, Chalapathi V wrote: This commit implements a Serial EEPROM utilizing the Serial Peripheral Interface (SPI) compatible bus. Currently implemented SEEPROM is Microchip's 25CSM04 which provides 4 Mbits of Serial EEPROM utilizing the Serial Peripheral Interface (SPI

[PATCH] hvf: arm: Remove PL1_WRITE_MASK

2024-04-22 Thread Zenghui Yu
As it had never been used since the first commit a1477da3ddeb ("hvf: Add Apple Silicon support"). Signed-off-by: Zenghui Yu --- target/arm/hvf/hvf.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 65a5601804..015e96a6d3 100644 --- a/target/arm

Re: [PATCH v3 31/49] i386/sev: Update query-sev QAPI format to handle SEV-SNP

2024-04-22 Thread Markus Armbruster
Michael Roth writes: > Most of the current 'query-sev' command is relevant to both legacy > SEV/SEV-ES guests and SEV-SNP guests, with 2 exceptions: > > - 'policy' is a 64-bit field for SEV-SNP, not 32-bit, and > the meaning of the bit positions has changed > - 'handle' is not relevant to

Re: [PATCH v3 36/49] i386/sev: Add KVM_EXIT_VMGEXIT handling for Extended Guest Requests

2024-04-22 Thread Markus Armbruster
Michael Roth writes: > The GHCB specification[1] defines a VMGEXIT-based Guest Request > hypercall to allow an SNP guest to issue encrypted requests directly to > SNP firmware to do things like query the attestation report for the > guest. These are generally handled purely in the kernel. > > In

Re: [PATCH v3 43/49] qapi, i386: Move kernel-hashes to SevCommonProperties

2024-04-22 Thread Markus Armbruster
Daniel P. Berrangé writes: > On Wed, Mar 20, 2024 at 03:39:39AM -0500, Michael Roth wrote: >> From: Dov Murik >> >> In order to enable kernel-hashes for SNP, pull it from >> SevGuestProperties to its parent SevCommonProperties so >> it will be available for both SEV and SNP. >> >> Signed-off-b

Re: [PATCH v2 5/6] hw/ppc: SPI controller wiring to P10 chip and create seeprom device

2024-04-22 Thread Cédric Le Goater
On 4/9/24 19:56, Chalapathi V wrote: In this commit Creates SPI controller on p10 chip. Create the keystore seeprom of type "seeprom-25csm04" Connect the cs of seeprom to PIB_SPIC[2] cs irq. The QOM tree of spi controller and seeprom are. /machine (powernv10-machine) /chip[0] (power10_v2.0-pn

Re: [PATCH v7 00/12] Enabling DCD emulation support in Qemu

2024-04-22 Thread Jonathan Cameron via
On Mon, 22 Apr 2024 15:23:16 +0100 Jonathan Cameron wrote: > On Mon, 22 Apr 2024 13:04:48 +0100 > Jonathan Cameron wrote: > > > On Sat, 20 Apr 2024 16:35:46 -0400 > > Gregory Price wrote: > > > > > On Fri, Apr 19, 2024 at 11:43:14AM -0700, fan wrote: > > > > On Fri, Apr 19, 2024 at 02:2

Re: [PATCH] target/arm: fix MPIDR value for ARM CPUs with SMT

2024-04-22 Thread Richard Henderson
On 4/22/24 04:26, Peter Maydell wrote: On Mon, 22 Apr 2024 at 11:46, Peter Maydell wrote: On Sun, 21 Apr 2024 at 06:40, Richard Henderson wrote: --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1314,8 +1314,18 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) }

Re: [PATCH] target/arm: fix MPIDR value for ARM CPUs with SMT

2024-04-22 Thread Richard Henderson
On 4/22/24 08:21, Richard Henderson wrote: For Arm's CPUs they fall into two categories:   * older ones don't set MT in their MPIDR, and the Aff0     field is effectively the CPU number   * newer ones do set MT in their MPIDR, but don't have     SMT, so their Aff0 is always 0 and their Aff1     i

Re: [PATCH v3 5/6] target/arm: Do memory type alignment check when translation disabled

2024-04-22 Thread Clément Chigot
Hi Richard, While testing the future V9, I've some regressions on a custom board using cortex-R5 CPUs. Unaligned data accesses are no longer allowed because of that patch. I've dug into the various documentation and it seems that R-profile CPUs don't have the same default memory type as A-profile

Re: [PATCH v2] tests/unit: Remove debug statements in test-nested-aio-poll.c

2024-04-22 Thread Stefan Hajnoczi
On Mon, Apr 22, 2024 at 01:22:46PM +0200, Philippe Mathieu-Daudé wrote: > We have been running this test for almost a year; it > is safe to remove its debug statements, which clutter > CI jobs output: > > ▶ 88/100 /nested-aio-poll OK > io_read 0x16bb26158 > io_poll_true

Re: [PATCH 0/3] target/arm: Make the counter frequency default 1GHz for new CPUs, machines

2024-04-22 Thread Marcin Juszkiewicz
W dniu 22.04.2024 o 16:18, Peter Maydell pisze: On Mon, 22 Apr 2024 at 14:38, Marcin Juszkiewicz From what I see in EDK2 code we read CNTFREQ_EL0: GetPlatformTimerFreq() checks for PcdArmArchTimerFreqInHz variable which sbsa-ref has set to 0. So it calls ArmGenericTimerGetTimerFreq() -> Arm

Re: [PATCH v7 00/12] Enabling DCD emulation support in Qemu

2024-04-22 Thread Gregory Price
On Mon, Apr 22, 2024 at 01:04:48PM +0100, Jonathan Cameron wrote: > On Sat, 20 Apr 2024 16:35:46 -0400 > Gregory Price wrote: > > > On Fri, Apr 19, 2024 at 11:43:14AM -0700, fan wrote: > > > On Fri, Apr 19, 2024 at 02:24:36PM -0400, Gregory Price wrote: > > > > > > > > added review to all patc

Re: [PATCH v3 5/6] target/arm: Do memory type alignment check when translation disabled

2024-04-22 Thread Richard Henderson
On 4/22/24 08:26, Clément Chigot wrote: Hi Richard, While testing the future V9, I've some regressions on a custom board using cortex-R5 CPUs. Unaligned data accesses are no longer allowed because of that patch. I've dug into the various documentation and it seems that R-profile CPUs don't have

[PATCH intel_iommu 1/7] intel_iommu: fix FRCD construction macro.

2024-04-22 Thread CLEMENT MATHIEU--DRIF
The constant must be unsigned, otherwise the two's complement overrides the other fields when a PASID is present Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu_internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/in

[PATCH intel_iommu 3/7] intel_iommu: make types match

2024-04-22 Thread CLEMENT MATHIEU--DRIF
The 'level' field in vtd_iotlb_key is an uint8_t. We don't need to store level as an int in vtd_lookup_iotlb Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 6f13

[PATCH intel_iommu 5/7] intel_iommu: extract device IOTLB invalidation logic

2024-04-22 Thread CLEMENT MATHIEU--DRIF
This piece of code can be shared by both IOTLB invalidation and PASID-based IOTLB invalidation Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 57 +-- 1 file changed, 33 insertions(+), 24 deletions(-) diff --git a/hw/i386/intel_iommu.c b/

[PATCH intel_iommu 6/7] intel_iommu: add PASID-based IOTLB invalidation

2024-04-22 Thread CLEMENT MATHIEU--DRIF
Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 130 ++--- hw/i386/intel_iommu_internal.h | 51 +++-- 2 files changed, 150 insertions(+), 31 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index aaac61bf6a..4b

[PATCH intel_iommu 0/7] FLTS for VT-d

2024-04-22 Thread CLEMENT MATHIEU--DRIF
This series is the first of a list that add support for SVM in the Intel IOMMU. Here, we implement support for first-stage translation in VT-d. The PASID-based IOTLB invalidation is also added in this series as it is a requirement of FLTS. The last patch introduces the 'flts' option to enable the

[PATCH intel_iommu 2/7] intel_iommu: rename slpte to pte before adding FLTS

2024-04-22 Thread CLEMENT MATHIEU--DRIF
Some variables struct fields and functions can be used for both slpte and flpte. We can modify certain identifiers to make them more generic. - slpte in IOMMUTLBEntry becomes pte and will be used for both FL and SL - VTD_SL_PT_LEVEL, VTD_SL_PT_PAGE_SIZE_MASK and VTD_SL_LEVEL_BITS can be renamed

[PATCH intel_iommu 7/7] intel_iommu: add a CLI option to enable FLTS

2024-04-22 Thread CLEMENT MATHIEU--DRIF
Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 6 ++ include/hw/i386/intel_iommu.h | 1 + 2 files changed, 7 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 4b54a45107..c35ccc3a98 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_

[PATCH intel_iommu 4/7] intel_iommu: add support for first-stage translation

2024-04-22 Thread CLEMENT MATHIEU--DRIF
This translation mode will only be made available in scalable mode Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 364 - hw/i386/intel_iommu_internal.h | 51 - 2 files changed, 362 insertions(+), 53 deletions(-) diff --git a/hw/i38

Re: [PATCH 0/3] target/arm: Make the counter frequency default 1GHz for new CPUs, machines

2024-04-22 Thread Peter Maydell
On Mon, 22 Apr 2024 at 15:18, Peter Maydell wrote: > I imagine that value gets written into CNTFRQ by TF-A somewhere > along the line (and then read by EDK2 later), though I haven't > quite found where. Plus I notice that the TF-A sbsa-watchdog-timer > assumes that the generic-timer frequency and

Re: [PATCH v3 5/6] target/arm: Do memory type alignment check when translation disabled

2024-04-22 Thread Peter Maydell
On Mon, 22 Apr 2024 at 16:48, Richard Henderson wrote: > > On 4/22/24 08:26, Clément Chigot wrote: > > Hi Richard, > > > > While testing the future V9, I've some regressions on a custom board > > using cortex-R5 CPUs. > > Unaligned data accesses are no longer allowed because of that patch. > > > >

Re: [PATCH 00/27] Add qapi-domain Sphinx extension

2024-04-22 Thread John Snow
On Mon, Apr 22, 2024 at 5:20 AM Markus Armbruster wrote: > > John Snow writes: > > > On Fri, Apr 19, 2024, 10:45 AM Markus Armbruster wrote: > > > >> John Snow writes: > >> > >> > This series adds a new qapi-domain extension for Sphinx, which adds a > >> > series of custom directives for docume

Re: [PATCH 0/6] Add ivshmem-flat device

2024-04-22 Thread Gustavo Romero
Hi Markus, Thanks for interesting in the ivshmem-flat device. Bill Mills (cc:ed) is the best person to answer your question, so please find his answer below. On 2/28/24 3:29 AM, Markus Armbruster wrote: Gustavo Romero writes: [...] This patchset introduces a new device, ivshmem-flat, which

Re: [PATCH 0/7] plugins: Use unwind info for special gdb registers

2024-04-22 Thread Alex Bennée
Richard Henderson writes: > Based-on: 20240404230611.21231-1-richard.hender...@linaro.org > ("[PATCH v2 00/21] Rewrite plugin code generation") I'm getting code conflicts w.r.t to the above (which is already merged?) so it would be helpful to get a re-base. > > This is an attempt to fix > https

Re: [PATCH intel_iommu 5/7] intel_iommu: extract device IOTLB invalidation logic

2024-04-22 Thread Philippe Mathieu-Daudé
On 22/4/24 17:52, CLEMENT MATHIEU--DRIF wrote: This piece of code can be shared by both IOTLB invalidation and PASID-based IOTLB invalidation Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 57 +-- 1 file changed, 33 insertions(+), 24

Re: [PATCH intel_iommu 3/7] intel_iommu: make types match

2024-04-22 Thread Philippe Mathieu-Daudé
On 22/4/24 17:52, CLEMENT MATHIEU--DRIF wrote: The 'level' field in vtd_iotlb_key is an uint8_t. We don't need to store level as an int in vtd_lookup_iotlb Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i3

[PATCH] target/arm: Restrict translation disabled alignment check to VMSA

2024-04-22 Thread Richard Henderson
For cpus using PMSA, when the MPU is disabled, the default memory type is Normal, Non-cachable. Fixes: 59754f85ed3 ("target/arm: Do memory type alignment check when translation disabled") Reported-by: Clément Chigot Signed-off-by: Richard Henderson --- Since v9 will likely be tagged tomorrow w

Re: [PATCH] target/arm: Restrict translation disabled alignment check to VMSA

2024-04-22 Thread Richard Henderson
On 4/22/24 10:07, Richard Henderson wrote: For cpus using PMSA, when the MPU is disabled, the default memory type is Normal, Non-cachable. Fixes: 59754f85ed3 ("target/arm: Do memory type alignment check when translation disabled") Reported-by: Clément Chigot Signed-off-by: Richard Henderson -

[PATCH v2 0/1] target/riscv/kvm: tolerate KVM disable ext errors

2024-04-22 Thread Daniel Henrique Barboza
Hi, In this new version we changed the commit message a bit and we're now only handling the case for EINVAL. Both were suggested by Drew in v1. Changes from v1: - added an extra paragraph explaining why we're throwing an warning - changed the warning string - warning is now being thrown only if E

[PATCH v2 1/1] target/riscv/kvm: tolerate KVM disable ext errors

2024-04-22 Thread Daniel Henrique Barboza
Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr enabled, will fail with a kernel oops SIGILL right at the start. The reason is that we can't expose zkr without implementing the SEED CSR. Disabling zkr in the guest would be a workaround, but if the KVM doesn't allow it we'll e

Re: [PATCH] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63

2024-04-22 Thread Daniel Henrique Barboza
Palmer, Anup, On 4/22/24 10:58, Clément Léger wrote: The current semihost exception number (16) is a reserved number (range [16-17]). The upcoming double trap specification uses that number for the double trap exception. Since the privileged spec (Table 22) defines ranges for custom uses change

Re: [PATCH] target/riscv/kvm: Fix exposure of Zkr

2024-04-22 Thread Daniel Henrique Barboza
On 4/22/24 10:46, Andrew Jones wrote: The Zkr extension may only be exposed to KVM guests if the VMM implements the SEED CSR. Use the same implementation as TCG. Without this patch, running with a KVM which does not forward the SEED CSR access to QEMU will result in an ILL exception being inj

RE: [PATCH v6 0/2] Implement SSH commands in QEMU GA for Windows

2024-04-22 Thread Aidan Leuck
Hi Konstantin, Thank you for taking the time to look over the patch and test it. I do expect this to work when installing OpenSSH by Windows features. I have been testing my implementation on Windows 11 which uses a newer version of OpenSSH server than the one shipped with Windows Server 2022.

[PATCH v7 0/2] Implement SSH commands in QEMU GA for Windows

2024-04-22 Thread aidan_leuck
From: aidaleuc Changes since v6 * Fixed issue with file permissions causing public keys to be rejected by the SSH server. credit (kkostiuk) Older versions of OpenSSH such as the one shipped with Windows Server 2022 are more stringent on file permissions. * Removed everyone group from create_ac

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