[PATCH v3 00/27] misc: Replace sprintf

Hi Phil, This incorporates my comments against 20240411104340.6617-1-phi...@linaro.org and 20240411101550.99392-1-phi...@linaro.org Especially cleanups to hexdup and disas. r~ Philippe Mathieu-Daudé (13): hw/mips/malta: Add re-usable rng_seed_hex_new() method system/qtest: Replace

[PATCH v3 11/27] backends/tpm: Use qemu_hexdump_line to avoid sprintf

From: Philippe Mathieu-Daudé sprintf() is deprecated on Darwin since macOS 13.0 / XCode 14.1. Using qemu_hexdump_line both fixes the deprecation warning and simplifies the code base. Reviewed-by: Stefan Berger Signed-off-by: Philippe Mathieu-Daudé [rth: Keep the linebreaks every 16 bytes] Sign

[PATCH v3 01/27] util/hexdump: Remove b parameter from qemu_hexdump_line

Require that the caller output the offset and increment bufptr. Use QEMU_HEXDUMP_LINE_BYTES in vhost_vdpa_dump_config instead of raw integer. Signed-off-by: Richard Henderson --- include/qemu/cutils.h | 2 +- hw/virtio/vhost-vdpa.c | 4 ++-- util/hexdump.c | 13 ++--- hw/virti

[PATCH v3 26/27] target/arm: Replace sprintf() by snprintf()

From: Philippe Mathieu-Daudé sprintf() is deprecated on Darwin since macOS 13.0 / XCode 14.1, resulting in painful developper experience. Use snprintf() instead. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20240411104340.6617-9-

[PATCH v3 08/27] hw/scsi/scsi-disk: Use qemu_hexdump_line to avoid sprintf

From: Philippe Mathieu-Daudé sprintf() is deprecated on Darwin since macOS 13.0 / XCode 14.1. Using qemu_hexdump_line both fixes the deprecation warning and simplifies the code base. Note that this drops the "0x" prefix to every byte, which should be of no consequence to tracing. Signed-off-by:

[PATCH v3 07/27] system/qtest: Replace sprintf by qemu_hexdump_line

From: Philippe Mathieu-Daudé sprintf() is deprecated on Darwin since macOS 13.0 / XCode 14.1. Using qemu_hexdump_line both fixes the deprecation warning and simplifies the code base. Signed-off-by: Philippe Mathieu-Daudé ` [rth: Use qemu_hexdump_line] Signed-off-by: Richard Henderson --- syste

[PATCH v3 12/27] disas/m68k: Replace sprintf() by snprintf()

From: Philippe Mathieu-Daudé sprintf() is deprecated on Darwin since macOS 13.0 / XCode 14.1, resulting in painful developper experience. Use snprintf() instead. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20240411104340.6617-2-

[PATCH v3 13/27] disas/microblaze: Replace sprintf() by snprintf()

From: Philippe Mathieu-Daudé sprintf() is deprecated on Darwin since macOS 13.0 / XCode 14.1, resulting in painful developper experience. Use snprintf() instead. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias Message-Id: <20240411104340.6617-3-phi...@linaro.org> Signed-of

[PATCH v3 03/27] util/hexdump: Use a GString for qemu_hexdump_line

Allocate a new, or append to an existing GString instead of using a fixed sized buffer. Require the caller to determine the length of the line -- do not bound len here. Signed-off-by: Richard Henderson --- include/qemu/cutils.h | 15 ++- hw/virtio/vhost-vdpa.c | 14 --

[PATCH v3 05/27] util/hexdump: Inline g_string_append_printf "%02x"

Trivial arithmetic can be used for emitting the nibbles, rather than full-blown printf formatting. Signed-off-by: Richard Henderson --- util/hexdump.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/util/hexdump.c b/util/hexdump.c index b29326b7f2..ae0d4992dc 100

[PATCH v3 24/27] hw/net/rocker: Replace sprintf() by snprintf()

From: Philippe Mathieu-Daudé sprintf() is deprecated on Darwin since macOS 13.0 / XCode 14.1, resulting in painful developper experience. Use snprintf() instead. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20240411104340.6617-7-phi...@linaro.org> Signed-off-by: Richard Henderson --- hw

[PATCH v3 23/27] hw/misc/imx: Replace sprintf() by snprintf()

From: Philippe Mathieu-Daudé sprintf() is deprecated on Darwin since macOS 13.0 / XCode 14.1, resulting in painful developper experience. Use snprintf() instead. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Message-Id: <20240411104340.6617-6-phi...@linaro.org> Signed-off-by

[PATCH v3 10/27] hw/dma/pl330: Use qemu_hexdump_line to avoid sprintf

From: Philippe Mathieu-Daudé sprintf() is deprecated on Darwin since macOS 13.0 / XCode 14.1. Using qemu_hexdump_line both fixes the deprecation warning and simplifies the code base. Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- hw/dma/pl330.c | 23 ---

[PATCH v3 27/27] target/i386/kvm: Improve KVM_EXIT_NOTIFY warnings

Signed-off-by: Richard Henderson --- target/i386/kvm/kvm.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index e68cbe9293..1fc809b2f9 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -5275,7 +5275,6

[PATCH v3 18/27] disas/microblaze: Print immediates directly with PRIimm

Use a printf format instead of sprintf into a buffer. Signed-off-by: Richard Henderson --- disas/microblaze.c | 61 +- 1 file changed, 11 insertions(+), 50 deletions(-) diff --git a/disas/microblaze.c b/disas/microblaze.c index c12968f3b9..390f98c0a3

[PATCH v3 17/27] disas/microblaze: Print registers directly with PRIreg

Use a printf format instead of sprintf into a buffer. Signed-off-by: Richard Henderson --- disas/microblaze.c | 54 -- 1 file changed, 23 insertions(+), 31 deletions(-) diff --git a/disas/microblaze.c b/disas/microblaze.c index a537ac65dd..c12968f3b9

[PATCH v3 22/27] linux-user/flatload: Replace sprintf() by snprintf()

From: Philippe Mathieu-Daudé sprintf() is deprecated on Darwin since macOS 13.0 / XCode 14.1, resulting in painful developper experience. Use snprintf() instead. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20240411104340.6617-5-phi...@linaro.org> Signed-off-by: Richard Henderson --- li

[PATCH v3 25/27] hw/riscv/virt: Replace sprintf by g_strdup_printf

From: Philippe Mathieu-Daudé sprintf() is deprecated on Darwin since macOS 13.0 / XCode 14.1. Use g_strdup_printf instead. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20240411104340.6617-8-phi...@linaro.org> [rth: Use g_strdup_printf] Signed-off-by: Richard Henderson --- hw/riscv/virt.

[PATCH v3 04/27] util/hexdump: Add unit_len and block_len to qemu_hexdump_line

Generalize the current 1 byte unit and 4 byte blocking within the output. Signed-off-by: Richard Henderson --- include/qemu/cutils.h | 6 +- hw/virtio/vhost-vdpa.c | 2 +- util/hexdump.c | 30 +- 3 files changed, 27 insertions(+), 11 deletions(-) diff

[PATCH v3 09/27] hw/ide/atapi: Use qemu_hexdump_line to avoid sprintf

From: Philippe Mathieu-Daudé sprintf() is deprecated on Darwin since macOS 13.0 / XCode 14.1. Using qemu_hexdump_line both fixes the deprecation warning and simplifies the code base. Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- hw/ide/atapi.c | 12 1

[PATCH v3 06/27] hw/mips/malta: Add re-usable rng_seed_hex_new() method

From: Philippe Mathieu-Daudé sprintf() is deprecated on Darwin since macOS 13.0 / XCode 14.1. Extract common code from reinitialize_rng_seed and load_kernel to rng_seed_hex_new. Using qemu_hexdump_line both fixes the deprecation warning and simplifies the code base. Signed-off-by: Philippe Mat

[PATCH v3 15/27] target/microblaze: Re-indent print_insn_microblaze

Signed-off-by: Richard Henderson --- disas/microblaze.c | 263 - 1 file changed, 141 insertions(+), 122 deletions(-) diff --git a/disas/microblaze.c b/disas/microblaze.c index 3473c94164..c729c76585 100644 --- a/disas/microblaze.c +++ b/disas/microblaz

[PATCH v3 20/27] disas/microblaze: Split get_field_special

Extract the raw special index and a function to lookup a name. Signed-off-by: Richard Henderson --- disas/microblaze.c | 142 +++-- 1 file changed, 61 insertions(+), 81 deletions(-) diff --git a/disas/microblaze.c b/disas/microblaze.c index 24febfdea9..19

[PATCH v3 02/27] util/hexdump: Remove ascii parameter from qemu_hexdump_line

Split out asciidump_line as a separate function, local to hexdump.c, for use by qemu_hexdump. Use "%-*s" to generate the alignment between the hex and the ascii, rather than explicit spaces. Signed-off-by: Richard Henderson --- include/qemu/cutils.h | 3 +-- hw/virtio/vhost-vdpa.c | 2 +- ut

[PATCH v3 19/27] disas/microblaze: Print registers directly with PRIrfsl

Use a printf format instead of sprintf into a buffer. Signed-off-by: Richard Henderson --- disas/microblaze.c | 22 +- 1 file changed, 5 insertions(+), 17 deletions(-) diff --git a/disas/microblaze.c b/disas/microblaze.c index 390f98c0a3..24febfdea9 100644 --- a/disas/microb

[PATCH v3 16/27] disas/microblaze: Merge op->name output into each fprintf

In the common case, issue one single fprintf. Signed-off-by: Richard Henderson --- disas/microblaze.c | 80 +++--- 1 file changed, 40 insertions(+), 40 deletions(-) diff --git a/disas/microblaze.c b/disas/microblaze.c index c729c76585..a537ac65dd 100644 -

[PATCH v3 14/27] disas/microblaze: Split out print_immval_addr

Unify the code blocks that try to print a symbolic address. Signed-off-by: Richard Henderson --- disas/microblaze.c | 89 +++--- 1 file changed, 29 insertions(+), 60 deletions(-) diff --git a/disas/microblaze.c b/disas/microblaze.c index 49a4c0fd40..3473c

[PATCH v3 21/27] disas/riscv: Use GString in format_inst

Allocate and fill a GString instead of snprintf and appending to a fixed sized buffer. Signed-off-by: Richard Henderson --- disas/riscv.c | 209 ++ 1 file changed, 92 insertions(+), 117 deletions(-) diff --git a/disas/riscv.c b/disas/riscv.c index

[PATCH 00/65]target/riscv: Support XTheadVector extension

This patchset implements the XTheadVector extension for RISC-V on QEMU. You can find the full description of the XTheadVector extension at: https://github.com/RISCV-SPEC/thead-extension-spec/blob/master/xtheadvector.adoc The XTheadvector extension is a non-standard extension for RISC-V. The encod

[PATCH 01/65] riscv: thead: Add th.sxstatus CSR emulation

From: Christoph Müllner The th.sxstatus CSR can be used to identify available custom extension on T-Head CPUs. The CSR is documented here: https://github.com/T-head-Semi/thead-extension-spec/pull/46 An important property of this patch is, that the th.sxstatus MAEE field is not set (indicating

Re: [PATCH 0/6 qemu] acpi: NUMA nodes for CXL HB as GP + complex NUMA test.

Hi, Jonathan, Jonathan Cameron writes: > ACPI 6.5 introduced Generic Port Affinity Structures to close a system > description gap that was a problem for CXL memory systems. > It defines an new SRAT Affinity structure (and hence allows creation of an > ACPI Proximity Node which can only be define

[PATCH 02/65] target/riscv: Reuse th_csr.c to add user-mode csrs

The former patch added th_csr.c to add th.sxstatus csr for XTheadMaee. However, it can only support system-mode vendor csrs. In this patch, I change the way of compiling th_csr.c and calling the function th_register_custom_csrs, using '#if !defined(CONFIG_USER_ONLY)' in th_csr.c to support both use

[PATCH 03/65] target/riscv: Add properties for XTheadVector extension

Add ext_xtheadvector properties. In this patch, we add ext_xtheadvector in RISCVCPUConfig for XTheadVector as a start. In rv64_thead_c906_cpu_init, we make ext_xtheadvector equals false to avoid affecting other extensions when it is not fully implemented. Signed-off-by: Huang Tao --- target/risc

[PATCH 04/65] target/riscv: Override some csr ops for XTheadVector

Some CSR operations have different behavior when XTheadVector is enabled. In this patch, we override the RISC-V standard implementation of these CSRs with a vendor implementation. Additionally, we attempt to use the decorator pattern to explicitly list the different behaviors between xtheadvector a

[PATCH 05/65] target/riscv: Add mlen in DisasContext

The mask register layout of XTheadVector is different from that of RVV1.0. For RVV1.0, the mask bits for element i are located in bit[i] of the mask register. While for XTheadVector, the mask bits for element i are located bit[MLEN*i] of the mask register. (MLEN = SEW/LMUL) So we add mlen in DisasC

[PATCH 06/65] target/riscv: Implement insns decode rules for XTheadVector

In this patch, we implement the XTheadVector instructions decode rules in xtheadvector.decode. In order to avoid compile failure, we add trans_ functions in trans_xtheadvector.c.inc as placeholders. Also, we add decode_xtheadvector in decoder_table to support dynamic building of deocders. There is

[PATCH 07/65] target/riscv: implement th.vsetvl{i} for XTheadVector

In this patch, we implement the th.vetvl{i} instructions. In the th_vsetvl function, some work has been done according to the difference between RVV1.0 and XTheadVector. th.vsetvl{i} differs from vsetvl{i} in the following points: 1. th.vsetvl{i} does not have the option to maintain the existing v

Re: [PATCH] linux-headers: change the annotation of VFIO_IOMMU_SPAPR_REGISTER_MEMORY in vfio.h

On Thu, Apr 11 2024, JianChunfu wrote: > The ioctl(VFIO_IOMMU_MAP_DMA/VFIO_IOMMU_UNMAP_DMA) won't be called > in SPAPR machine, which is replaced by VFIO_IOMMU_SPAPR_TCE_CREATE/ > VFIO_IOMMU_SPAPR_TCE_REMOVE, so change the description. > > Signed-off-by: JianChunfu > --- > linux-headers/linux/v

[PATCH 08/65] target/riscv: Add strided load instructions for XTheadVector

In this patch, we add one strided load instructions to show the way we implement XTheadVector load/store instructions. We use independent functions to achieve decoupling. XTheadVector strided load instructions diff from RVV1.0 in the following points: 1. Different mask reg layout. For mask bit of

Re: [RFC 0/2] Identify aliased maps in vdpa SVQ iova_tree

On Fri, Apr 12, 2024 at 8:47 AM Jason Wang wrote: > > On Wed, Apr 10, 2024 at 6:03 PM Eugenio Pérez wrote: > > > > The guest may have overlapped memory regions, where different GPA leads > > to the same HVA. This causes a problem when overlapped regions > > (different GPA but same translated HVA

[PATCH 09/65] target/riscv: Add strided store instructions for XTheadVector

XTheadVector strided store instructions diff from RVV1.0 in the following points: 1. Different mask reg layout. The difference is same as strided load instructions. 2. Different vector reg element width. XTheadVector has 4 instructions, th.vss{b,h,w,e}.v. They store SEW-bit reg data to 8/16/32/

[PATCH 10/65] target/riscv: Add unit-stride load instructions for XTheadVector

TheadVector unit-stride load instructions diff from RVV1.0 in the following points: 1. Different mask reg layout. 2. Different vector reg element width. 3. Different tail/masked elements process policy. 4. Different check function. The detials of the difference are the same as strided load instruc

[PATCH 11/65] target/riscv: Add unit-stride store instructions for XTheadVector

XTheadVector unit-stride store instructions diff from RVV1.0 in the following points: 1. Different mask reg layout. 2. Different vector reg element width. 3. Different tail/masked elements process policy. 4. Different check policy. The detials of the difference are the same as strided store instru

[PATCH v2] Makefile: fix use of -j without an argument

From: Matheus Tavares Bernardino Our Makefile massages the given make arguments to invoke ninja accordingly. One key difference is that ninja will parallelize by default, whereas make only does so with -j or -j. The make man page says that "if the -j option is given without an argument, make will

[PATCH 12/65] target/riscv: Add indexed load instructions for XTheadVector

XTheadVector indexed load instructions diff from RVV1.0 in the following points: 1. Different mask reg layout. 2. Different access width. XTheadVector has 7 instructions, th.vlx{b,h,w}.v, th.vlx{b,h,w}u.v and th.vlxe.v. Their index element width and reg data element width are all SEW-bit. The

Re: [PATCH] Makefile: fix use of -j without an argument

On Thu, Apr 11, 2024 at 5:46 PM Matheus Tavares Bernardino wrote: > +$(if $(filter -j, $(MAKEFLAGS)) \ > +,, \ > +$(or \ > + $(filter -l% -j%, $(MAKEFLAGS)), \ > + $(if $(filter --jobserver-auth=%, $(MAKEFLAGS)),, -j1)) \ > +)

[PATCH 13/65] target/riscv: Add indexed store instructions for XTheadVector

XTheadVector indexed store instructions diff from RVV1.0 in the following points: 1. Different mask reg layout. 2. Different access width. As same as XTheadVector indexed load instructions, except store does not need to distinguish between zero and sign extended. 3. Different masked elements pro

[PATCH 14/65] target/riscv: Add unit-stride fault-only-first instructions for XTheadVector

XTheadVector unit-stride fault-only-first instructions diff from RVV1.0 in the following points: 1. Different mask reg layout. 2. Different vector reg element width. 3. Different tail/masked elements process policy. 4. Different check policy. The detials of the difference are the same as unit-strid

[PATCH 15/65] target/riscv: Add vector amo operations for XTheadVector

In this patch, we add the vector amo instructions(Zvamo) for XTheadVector. Zvamo is unsupported by RVV1.0. The action of Zvamo is similar to Zaamo(atomic operations from the standard A extension). Signed-off-by: Huang Tao --- target/riscv/helper.h | 28 .../riscv/in

[PATCH 16/65] target/riscv: Add single-width integer add and subtract instructions for XTheadVector

In this patch, we add single-width integer add and subtract instructions, including th.vadd.vv/vx/vi, th.vsub.vv/vx and th.vrsub.vx/vi, also show the way we implement XTheadVector integer arithmetic instructions. These instructions diff from RVV1.0 in the following points: 1. Different mask reg lay

[PATCH 17/65] target/riscv: Add widening integer add/subtract instructions for XTheadVector

In this patch, we reuse lots of funtions of single-width operations, except do_opivv_th. The reason why do_opivv_widen_th does not call do_opivv_th is that widen operation is not applicable to using GVEC to accerlate the vector operations. The difference between XTheadVector and RVV1.0 is as same

[PATCH RFC] prevent overflow in xlnx_dpdma_desc_get_source_address()

Overflow can occur in a situation where desc->source_address has a maximum value (pow(2, 32) - 1), so add a cast to a larger type before the assignment. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: d3c6369a96 ("introduce xlnx-dpdma") Signed-off-by: Alexandra Diupina -

[PATCH 18/65] target/riscv: Add integer add-with-carry/sub-with-borrow instructions for XTheadVector

XTheadVector adc/sbc instructions diff from RVV1.0 in the following points: 1. Different mask reg layout. 2. Different tail elements process policy. 3. Different check policy. 4. When vm = 1, RVV1.0 vmadc and vmsbc perform the computation without carry-in/borrow-in. While XTheadVector does not h

[PATCH 19/65] target/riscv: Add bitwise logical instructions for XTheadVector

Add bitwise logical instructions by resuing macros define before, Therefore, the difference depending on the macros which commited in other patchs. Signed-off-by: Huang Tao --- target/riscv/helper.h | 25 + .../riscv/insn_trans/trans_xtheadvector.c.inc | 20 --

[PATCH 20/65] target/riscv: Add single-width bit shift instructions for XTheadVector

The difference between XTheadVector and RVV1.0 is same as the other patchs: 1. Different mask reg layout. 2. Different tail/masked elements process policy. 3. Simpler acceleration judgment logic. Signed-off-by: Huang Tao --- target/riscv/helper.h | 25 .../riscv/ins

[PATCH 21/65] target/riscv: Add narrowing integer right shift instructions for XTheadVector

The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h | 13 +++ .../riscv/insn_trans/trans_xtheadvector.c.inc | 99 +-- target/riscv

[PATCH 22/65] target/riscv: Add integer compare instructions for XTheadVector

The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h | 57 .../riscv/insn_trans/trans_xtheadvector.c.inc | 69 +++--- target/riscv/x

[PATCH 23/65] target/riscv: Add integer min/max instructions for XTheadVector

The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h | 33 + .../riscv/insn_trans/trans_xtheadvector.c.inc | 18 ++--- target/riscv/xtheadv

[PATCH 24/65] target/riscv: Add single-width integer multiply instructions for XTheadVector

The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h | 33 + .../riscv/insn_trans/trans_xtheadvector.c.inc | 18 ++--- target/riscv/vector_

[PATCH 25/65] target/riscv: Add integer divide instructions for XTheadVector

The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h | 33 + .../riscv/insn_trans/trans_xtheadvector.c.inc | 18 +++-- target/riscv/xtheadv

[PATCH 26/65] target/riscv: Add widening integer multiply instructions for XTheadVector

The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h | 19 + .../riscv/insn_trans/trans_xtheadvector.c.inc | 14 --- target/riscv/vecto

[PATCH 27/65] target/riscv: Add single-width integer multiply-add instructions for XTheadVector

The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h | 33 +++ .../riscv/insn_trans/trans_xtheadvector.c.inc | 18 ++-- target/riscv/xtheadvect

[PATCH 28/65] target/riscv: Add widening integer multiply-add instructions for XTheadVector

The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h | 22 + .../riscv/insn_trans/trans_xtheadvector.c.inc | 16 --- target/riscv/vecto

[PATCH 29/65] target/riscv: Add integer merge and move instructions for XTheadVector

The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Except of th.vmv.v.x, the difference is that XTheadVector has no limit of SEW of 8 to 64, Therefore, it is not suitable to use acceleration when xlen < SEW. Signed-off-by:

[PATCH 30/65] target/riscv: Add single-width saturating add and sub instructions for XTheadVector

In this patch, we add single-width saturating add and sub instructions to show the way we implement XTheadVector fixed-point arithmetic instructions. The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang

[PATCH 31/65] target/riscv: Add single-width average add and sub instructions for XTheadVector

The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h | 17 + .../riscv/insn_trans/trans_xtheadvector.c.inc | 12 --- target/riscv/vecto

[PATCH-for-9.0?] docs: i386: pc: Update maximum CPU numbers for PC Q35

From: Zhao Liu Commit e4e98c7eebfa ("pc: q35: Bump max_cpus to 4096 vcpus") increases the supported CPUs for PC Q35 machine. Update maximum CPU numbers for PC Q35 in the document. Signed-off-by: Zhao Liu --- docs/system/target-i386-desc.rst.inc | 2 +- 1 file changed, 1 insertion(+), 1 deleti

[PATCH 32/65] target/riscv: Add single-width fractional mul with rounding and saturation for XTheadVector

The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h | 9 + .../riscv/insn_trans/trans_xtheadvector.c.inc | 6 -- target/riscv/vector

[PATCH 33/65] target/riscv: Add widening saturating scaled multiply-add instructions for XTheadVector

There are no instructions similar to these instructions in RVV1.0. So we implement them by writing their own functions instead of copying code from RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h | 22 ++ .../riscv/insn_trans/trans_xtheadvector.c.inc | 16 +-

[PATCH 34/65] target/riscv: Add single-width scaling shift instructions for XTheadVector

The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h | 17 + .../riscv/insn_trans/trans_xtheadvector.c.inc | 14 --- target/riscv/vecto

[PATCH 35/65] target/riscv: Add narrowing fixed-point clip instructions for XTheadVector

The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h | 13 + .../riscv/insn_trans/trans_xtheadvector.c.inc | 14 + target/riscv/vec

[PATCH 36/65] target/riscv: Add single-width floating-point add/sub instructions for XTheadVector

In this patch, we add single-width floating-point add/sub instructions to show the way we implement XTheadVector floating-point arithmetic instructions. XTheadVector diff from RVV1.0 in the following points: 1. Different mask reg layout. 2. Different tail/masked elements process policy. 3. Differen

[PATCH 37/65] target/riscv: Add widening floating-point add/sub instructions for XTheadVector

The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h | 17 ++ .../riscv/insn_trans/trans_xtheadvector.c.inc | 162 +- target/riscv

[PATCH 38/65] target/riscv: Add single-width floating-point multiply/divide instructions for XTheadVector

The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h | 16 + .../riscv/insn_trans/trans_xtheadvector.c.inc | 12 --- target/riscv/vecto

[PATCH 39/65] target/riscv: Add widening floating-point multiply instructions for XTheadVector

The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h| 5 + target/riscv/insn_trans/trans_xtheadvector.c.inc | 6 -- target/riscv/vect

[PATCH 40/65] target/riscv: Add single-width floating-point fused multiply-add instructions for XTheadVector

The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h | 49 +++ .../riscv/insn_trans/trans_xtheadvector.c.inc | 34 ++--- target/riscv/vector_

Re: [PATCH 2/2] hw: Add a Kconfig switch for the TYPE_CPU_CLUSTER device

On 12/04/2024 08.20, Thomas Huth wrote: The cpu-cluster device is only needed for some few arm and riscv machines. Let's avoid compiling and linking it if it is not really necessary. Signed-off-by: Thomas Huth --- hw/arm/Kconfig | 3 +++ hw/cpu/Kconfig | 3 +++ hw/cpu/meson.build |

[PATCH 41/65] target/riscv: Add widening floating-point fused mul-add instructions for XTheadVector

The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h | 17 + .../riscv/insn_trans/trans_xtheadvector.c.inc | 18 + target/riscv/vec

[PATCH 42/65] target/riscv: Add floating-pointing square-root instructions for XTheadVector

The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h | 4 ++ .../riscv/insn_trans/trans_xtheadvector.c.inc | 46 ++- target/riscv/

[PATCH] dma-helpers: Fix iovec alignment

Commit 99868af3d0 changed the hardcoded constant BDRV_SECTOR_SIZE to a dynamic field 'align' but introduced a bug. qemu_iovec_discard_back() is now passed the wanted iov length instead of the actually required amount that should be removed from the end of the iov. The bug can likely only be hit in

[PATCH 43/65] target/riscv: Add floating-point MIN/MAX instructions for XTheadVector

The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h | 13 + .../riscv/insn_trans/trans_xtheadvector.c.inc | 10 --- target/riscv/xthea

[PATCH 44/65] target/riscv: Add floating-point sign-injection instructions for XTheadVector

The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h | 19 + .../riscv/insn_trans/trans_xtheadvector.c.inc | 14 --- target/riscv/vecto

[PATCH 45/65] target/riscv: Add floating-point compare instructions for XTheadVector

There is no similar instruction in RVV1.0 as th.vmford in XTheadVector. Signed-off-by: Huang Tao --- target/riscv/helper.h | 37 +++ .../riscv/insn_trans/trans_xtheadvector.c.inc | 49 +++--- target/riscv/vector_helper.c | 18 ++-- target/riscv/ve

[PATCH 46/65] target/riscv: Add floating-point classify and merge instructions for XTheadVector

The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h | 8 +++ .../riscv/insn_trans/trans_xtheadvector.c.inc | 51 +++- target/riscv/xt

[PATCH 47/65] target/riscv: Add single-width floating-point/integer type-convert instructions for XTheadVector

Compared to RVV1.0, XTheadVector lacks .rtz instructions, which specify the rounding mode of rounding to zero. Except of lack of similar instructions, the instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huan

[PATCH 48/65] target/riscv: Add widening floating-point/integer type-convert instructions for XTheadVector

Compared to RVV1.0, XTheadVector lacks .rtz instructions, which specify the rounding mode of rounding to zero. Except of lack of similar instructions, the instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huan

[PATCH 49/65] target/riscv: Add narrowing floating-point/integer type-convert instructions for XTheadVector

Compared to RVV1.0, XTheadVector lacks .rtz and .rod instructions, which specify the rounding mode. Except of lack of similar instructions, the instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao ---

[PATCH 50/65] target/riscv: Add single-width integer reduction instructions for XTheadVector

In this patch, we add single-width integer reduction instructions to show the way we implement XTheadVector reduction instructions. XTheadVector single-width integer reduction instructions diff from RVV1.0 in the following points: 1. Different mask reg layout. For mask bit of element i, XTheadVecto

[PATCH 51/65] target/riscv: Add widening integer reduction instructions for XTheadVector

The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h| 7 +++ target/riscv/insn_trans/trans_xtheadvector.c.inc | 6 -- target/riscv/xt

[PATCH 52/65] target/riscv: Add single-width floating-point reduction instructions for XTheadVector

The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h | 10 .../riscv/insn_trans/trans_xtheadvector.c.inc | 8 +-- target/riscv/xtheadvector_h

[PATCH 53/65] target/riscv: Add widening floating-point reduction instructions for XTheadVector

The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h| 3 +++ target/riscv/insn_trans/trans_xtheadvector.c.inc | 4 +++- target/riscv/xtheadve

[PATCH 54/65] target/riscv: Add mask-register logical instructions for XTheadVector

In this patch, we add mask-register logical instructions to show the way we implement XTheadVector mask instructions. XTheadVector mask-register logical instructions diff from RVV1.0 in the following points: 1. Different mask reg layout. For mask bit of element i, XTheadVector locates it in bit[

[PATCH 55/65] target/riscv: Add vector mask population count vmpopc for XTheadVector

The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h | 2 ++ .../riscv/insn_trans/trans_xtheadvector.c.inc | 31 ++- target/riscv/

Re: [PATCH v3 22/27] linux-user/flatload: Replace sprintf() by snprintf()

On Fri, 12 Apr 2024 at 08:36, Richard Henderson wrote: > > From: Philippe Mathieu-Daudé > > sprintf() is deprecated on Darwin since macOS 13.0 / XCode 14.1, > resulting in painful developper experience. Use snprintf() instead. > > Signed-off-by: Philippe Mathieu-Daudé > Message-Id: <202404111043

[PATCH 56/65] target/riscv: Add th.vmfirst.m for XTheadVector

The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h | 2 ++ .../riscv/insn_trans/trans_xtheadvector.c.inc | 31 ++- target/riscv/

[PATCH 57/65] target/riscv: Add set-X-first mask bit instructrions for XTheadVector

The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h | 4 ++ .../riscv/insn_trans/trans_xtheadvector.c.inc | 36 ++- target/riscv/xtheadve

Re: [PATCH] dma-helpers: Fix iovec alignment

On 12/4/24 10:06, Stefan Fritsch wrote: Commit 99868af3d0 changed the hardcoded constant BDRV_SECTOR_SIZE to a dynamic field 'align' but introduced a bug. qemu_iovec_discard_back() is now passed the wanted iov length instead of the actually required amount that should be removed from the end of t

[PATCH 58/65] target/riscv: Add vector iota instruction for XTheadVector

The instruction has the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h | 5 .../riscv/insn_trans/trans_xtheadvector.c.inc | 29 +- target/riscv/x

[PATCH 59/65] target/riscv: Add vector element index instruction for XTheadVector

The instruction has the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h | 5 .../riscv/insn_trans/trans_xtheadvector.c.inc | 27 ++- target/riscv/

[PATCH 60/65] target/riscv: Add integer extract and scalar move instructions for XTheadVector

In this patch, we add integer extract and scalar move instructions to show the way we implement XTheadVector permutation instructions. XTheadVector integer scalar move instructions diff from RVV1.0 in the following points: 1. th.vext.x.v can transfer any element in a vector register to a general

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