In this patch, we add mask-register logical instructions to show the way
we implement XTheadVector mask instructions.
XTheadVector mask-register logical instructions diff from RVV1.0 in the
following points:
1. Different mask reg layout. For mask bit of element i, XTheadVector locates it
in bit[mlen], while RVV1.0 locates it in bit[i].
Signed-off-by: Huang Tao <eric.hu...@linux.alibaba.com>
---
target/riscv/helper.h | 9 ++++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 44 +++++++++++++++----
target/riscv/xtheadvector_helper.c | 42 ++++++++++++++++++
3 files changed, 87 insertions(+), 8 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index c39ee9a8e8..7d992ac3b1 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -2289,3 +2289,12 @@ DEF_HELPER_6(th_vfredmin_vs_d, void, ptr, ptr, ptr, ptr,
env, i32)
DEF_HELPER_6(th_vfwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(th_vfwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_6(th_vmand_mm, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmnand_mm, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmandnot_mm, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmxor_mm, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmor_mm, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmornot_mm, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc
b/target/riscv/insn_trans/trans_xtheadvector.c.inc
index b71875700b..e9fa7f1ae2 100644
--- a/target/riscv/insn_trans/trans_xtheadvector.c.inc
+++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc
@@ -2405,20 +2405,48 @@ GEN_OPFVV_TRANS_TH(th_vfredmin_vs, reduction_check_th)
/* Vector Widening Floating-Point Reduction Instructions */
GEN_OPFVV_WIDEN_TRANS_TH(th_vfwredsum_vs, reduction_check_th)
+/*
+ * Vector Mask Operations
+ */
+
+/* Vector Mask-Register Logical Instructions */
+#define GEN_MM_TRANS_TH(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_r *a) \
+{ \
+ if (require_xtheadvector(s) && \
+ vext_check_isa_ill(s)) { \
+ uint32_t data = 0; \
+ gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \
+ \
+ data = FIELD_DP32(data, VDATA_TH, MLEN, s->mlen); \
+ data = FIELD_DP32(data, VDATA_TH, LMUL, s->lmul); \
+ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), \
+ vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs1), \
+ vreg_ofs(s, a->rs2), tcg_env, \
+ s->cfg_ptr->vlenb, \
+ s->cfg_ptr->vlenb, data, fn); \
+ finalize_rvv_inst(s); \
+ return true; \
+ } \
+ return false; \
+}
+
+GEN_MM_TRANS_TH(th_vmand_mm)
+GEN_MM_TRANS_TH(th_vmnand_mm)
+GEN_MM_TRANS_TH(th_vmandnot_mm)
+GEN_MM_TRANS_TH(th_vmxor_mm)
+GEN_MM_TRANS_TH(th_vmor_mm)
+GEN_MM_TRANS_TH(th_vmnor_mm)
+GEN_MM_TRANS_TH(th_vmornot_mm)
+GEN_MM_TRANS_TH(th_vmxnor_mm)
+
#define TH_TRANS_STUB(NAME) \
static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
{ \
return require_xtheadvector(s); \
}
-TH_TRANS_STUB(th_vmand_mm)
-TH_TRANS_STUB(th_vmnand_mm)
-TH_TRANS_STUB(th_vmandnot_mm)
-TH_TRANS_STUB(th_vmxor_mm)
-TH_TRANS_STUB(th_vmor_mm)
-TH_TRANS_STUB(th_vmnor_mm)
-TH_TRANS_STUB(th_vmornot_mm)
-TH_TRANS_STUB(th_vmxnor_mm)
TH_TRANS_STUB(th_vmpopc_m)
TH_TRANS_STUB(th_vmfirst_m)
TH_TRANS_STUB(th_vmsbf_m)
diff --git a/target/riscv/xtheadvector_helper.c
b/target/riscv/xtheadvector_helper.c
index 8953207630..b3f445eeb5 100644
--- a/target/riscv/xtheadvector_helper.c
+++ b/target/riscv/xtheadvector_helper.c
@@ -3475,3 +3475,45 @@ static uint64_t fwadd32(uint64_t a, uint32_t b,
float_status *s)
/* Unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */
GEN_TH_FRED(th_vfwredsum_vs_h, uint32_t, uint16_t, H4, H2, fwadd16, clearl_th)
GEN_TH_FRED(th_vfwredsum_vs_w, uint64_t, uint32_t, H8, H4, fwadd32, clearq_th)
+
+/*
+ * Vector Mask Operations
+ */
+/* Vector Mask-Register Logical Instructions */
+#define GEN_TH_MASK_VV(NAME, OP) \
+void HELPER(NAME)(void *vd, void *v0, void *vs1, \
+ void *vs2, CPURISCVState *env, \
+ uint32_t desc) \
+{ \
+ uint32_t mlen = th_mlen(desc); \
+ uint32_t vlmax = (env_archcpu(env)->cfg.vlenb << 3) / mlen; \
+ uint32_t vl = env->vl; \
+ uint32_t i; \
+ int a, b; \
+ \
+ VSTART_CHECK_EARLY_EXIT(env); \
+ for (i = env->vstart; i < vl; i++) { \
+ a = th_elem_mask(vs1, mlen, i); \
+ b = th_elem_mask(vs2, mlen, i); \
+ th_set_elem_mask(vd, mlen, i, OP(b, a)); \
+ } \
+ env->vstart = 0; \
+ for (; i < vlmax; i++) { \
+ th_set_elem_mask(vd, mlen, i, 0); \
+ } \
+}
+
+#define TH_NAND(N, M) (!(N & M))
+#define TH_ANDNOT(N, M) (N & !M)
+#define TH_NOR(N, M) (!(N | M))
+#define TH_ORNOT(N, M) (N | !M)
+#define TH_XNOR(N, M) (!(N ^ M))
+
+GEN_TH_MASK_VV(th_vmand_mm, TH_AND)
+GEN_TH_MASK_VV(th_vmnand_mm, TH_NAND)
+GEN_TH_MASK_VV(th_vmandnot_mm, TH_ANDNOT)
+GEN_TH_MASK_VV(th_vmxor_mm, TH_XOR)
+GEN_TH_MASK_VV(th_vmor_mm, TH_OR)
+GEN_TH_MASK_VV(th_vmnor_mm, TH_NOR)
+GEN_TH_MASK_VV(th_vmornot_mm, TH_ORNOT)
+GEN_TH_MASK_VV(th_vmxnor_mm, TH_XNOR)
--
2.44.0
