On Mon, 25 Mar 2024 at 08:52, Jinjie Ruan wrote:
>
> A SPI, PPI or SGI interrupt can have non-maskable property. So maintain
> non-maskable property in PendingIrq and GICR/GICD. Since add new device
> state, it also needs to be migrated, so also save NMI info in
> vmstate_gicv3_cpu and vmstate_gic
On Mon, 25 Mar 2024 at 08:52, Jinjie Ruan wrote:
>
> Augment the GICv3's QOM device interface by adding one
> new set of sysbus IRQ line, to signal NMI to each CPU.
>
> Signed-off-by: Jinjie Ruan
> Reviewed-by: Richard Henderson
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Mon, 25 Mar 2024 at 08:52, Jinjie Ruan wrote:
>
> Add GICR_INMIR0 register and support access GICR_INMIR0.
>
> Signed-off-by: Jinjie Ruan
> Reviewed-by: Richard Henderson
> ---
> v10:
> - gicr_isuperprio -> gicr_inmir0.
> v6:
> - Add Reviewed-by.
> v4:
> - Make the GICR_INMIR0 implementation
On Mon, 25 Mar 2024 at 08:52, Jinjie Ruan wrote:
>
> Add GICD_INMIR, GICD_INMIRnE register and support access GICD_INMIR0.
>
> Signed-off-by: Jinjie Ruan
> Reviewed-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
On Thu, Mar 28, 2024 at 09:54:49AM -0500, Eric Blake wrote:
> On Thu, Mar 28, 2024 at 03:06:03PM +0100, Thomas Huth wrote:
> > Since version 2.66, glib has useful URI parsing functions, too.
> > Use those instead of the QEMU-internal ones to be finally able
> > to get rid of the latter. The g_uri_g
On Thu, Mar 28, 2024 at 11:18:04AM -0300, Fabiano Rosas wrote:
> Philippe Mathieu-Daudé writes:
>
> > The whole RDMA subsystem was deprecated in commit e9a54265f5
> > ("hw/rdma: Deprecate the pvrdma device and the rdma subsystem")
> > released in v8.2.
> >
> > Remove:
> > - RDMA handling from mi
On 3/28/24 15:02, Avihai Horon wrote:
There are several places where postcopy_start() fails without setting
errp. This can cause a null pointer de-reference, as in case of error,
the caller of postcopy_start() copies/prints the error set in errp.
Fix it by setting errp in all of postcopy_start()
Adjusting cc list to add upstream NBD and drop developers unrelated to
this part of the qemu series...
On Thu, Mar 28, 2024 at 02:13:42PM +, Richard W.M. Jones wrote:
> On Thu, Mar 28, 2024 at 03:06:03PM +0100, Thomas Huth wrote:
> > Since version 2.66, glib has useful URI parsing functions, t
On Thu, Mar 28, 2024 at 04:02:51PM +0200, Avihai Horon wrote:
> After commit 9425ef3f990a ("migration: Use migrate_has_error() in
> close_return_path_on_source()"), close_return_path_on_source() assumes
> that migration error is set if an error occurs during migration.
>
> This may not be true if
On Thu, Mar 28, 2024 at 04:02:52PM +0200, Avihai Horon wrote:
> There are several places where postcopy_start() fails without setting
> errp. This can cause a null pointer de-reference, as in case of error,
> the caller of postcopy_start() copies/prints the error set in errp.
>
> Fix it by setting
On 27/03/2024 16:54, Philippe Mathieu-Daudé wrote:
Per Daniel suggestion [*]:
> isapc could arguably be restricted to just 32-bit CPU models,
> because we should not need it to support any feature that didn't
> exist prior to circa 1995. eg refuse to start with isapc, if 'lm'
> is prese
On Tue, Nov 14, 2023 at 03:38:15PM +0100, Philippe Mathieu-Daudé wrote:
> Previous commits re-organized the target-specific bits
> from Xen files. We can now build the common files once
> instead of per-target.
>
> Only 4 files call libxen API (thus its CPPFLAGS):
> - xen-hvm-common.c,
> - xen_pt.
On Wed, Mar 27, 2024 at 05:54:56PM +0100, Philippe Mathieu-Daudé wrote:
> Per Daniel suggestion [*]:
>
> > isapc could arguably be restricted to just 32-bit CPU models,
> > because we should not need it to support any feature that didn't
> > exist prior to circa 1995. eg refuse to start with is
On Thu, Mar 28, 2024 at 02:32:37AM +, Liu, Yuan1 wrote:
> > -Original Message-
> > From: Peter Xu
> > Sent: Thursday, March 28, 2024 3:26 AM
> > To: Liu, Yuan1
> > Cc: Daniel P. Berrangé ; faro...@suse.de; qemu-
> > de...@nongnu.org; hao.xi...@bytedance.com; bryan.zh...@bytedance.com;
Hello Avihai,
On 3/28/24 15:02, Avihai Horon wrote:
After commit 9425ef3f990a ("migration: Use migrate_has_error() in
close_return_path_on_source()"), close_return_path_on_source() assumes
that migration error is set if an error occurs during migration.
This may not be true if migration errors
On Thu, Mar 28, 2024 at 03:02:30AM +, Liu, Yuan1 wrote:
> Yes, I will support software fallback to ensure CI testing and users can
> still use qpl compression without IAA hardware.
>
> Although the qpl software solution will have better performance than zlib,
> I still don't think it has a g
On 28/03/2024 16.01, Peter Xu wrote:
On Thu, Mar 28, 2024 at 11:18:04AM -0300, Fabiano Rosas wrote:
Philippe Mathieu-Daudé writes:
The whole RDMA subsystem was deprecated in commit e9a54265f5
("hw/rdma: Deprecate the pvrdma device and the rdma subsystem")
released in v8.2.
Remove:
- RDMA h
On Wed, 27 Mar 2024 at 05:41, Harsh Prateek Bora wrote:
>
>
>
> On 3/26/24 21:32, Peter Maydell wrote:
> > On Tue, 12 Mar 2024 at 17:11, Nicholas Piggin wrote:
> >>
> >> From: Harsh Prateek Bora
> >>
> >> Introduce the nested PAPR hcalls:
> >> - H_GUEST_GET_STATE which is used to get state
If the group of the highest priority pending interrupt is disabled
via ICC_IGRPEN*, the ICC_HPPIR* registers should return
INTID_SPURIOUS, not the interrupt ID. (See the GIC architecture
specification pseudocode functions ICC_HPPIR1_EL1[] and
HighestPriorityPendingInterrupt().)
Make HPPIR reads h
On 28/03/2024 15.59, Daniel P. Berrangé wrote:
On Thu, Mar 28, 2024 at 09:54:49AM -0500, Eric Blake wrote:
On Thu, Mar 28, 2024 at 03:06:03PM +0100, Thomas Huth wrote:
Since version 2.66, glib has useful URI parsing functions, too.
Use those instead of the QEMU-internal ones to be finally able
On 28/03/2024 16.12, Mark Cave-Ayland wrote:
On 27/03/2024 16:54, Philippe Mathieu-Daudé wrote:
Per Daniel suggestion [*]:
> isapc could arguably be restricted to just 32-bit CPU models,
> because we should not need it to support any feature that didn't
> exist prior to circa 1995. eg re
From: aidaleuc
Signed-off-by: aidaleuc
---
qga/commands-common-ssh.c | 50 ++
qga/commands-common-ssh.h | 10
qga/commands-posix-ssh.c | 51 +++
qga/meson.build | 1 +
4 files changed, 64 insertions(+),
From: aidaleuc
This patch aims to implement guest-ssh-add-authorized-keys,
guest-ssh-remove-authorized-keys, and guest-ssh-get-authorized-keys
for Windows. This PR is based on Microsoft's OpenSSH implementation
https://github.com/PowerShell/Win32-OpenSSH. The guest agents
will support Kubevirt
From: aidaleuc
Signed-off-by: aidaleuc
---
qga/commands-windows-ssh.c | 789 +
qga/commands-windows-ssh.h | 26 ++
qga/meson.build| 5 +-
qga/qapi-schema.json | 17 +-
4 files changed, 826 insertions(+), 11 deletions(-)
create mode 1006
On Tue, 26 Mar 2024 at 09:58, Marcin Juszkiewicz
wrote:
>
> Hardware of sbsa-ref board is nowadays defined by both BSA and SBSA
> specifications. Then BBR defines firmware interface.
>
> Added note about DeviceTree data passed from QEMU to firmware. It is
> very minimal and provides only data we u
On 28/03/2024 17:21, Cédric Le Goater wrote:
External email: Use caution opening links or attachments
Hello Avihai,
On 3/28/24 15:02, Avihai Horon wrote:
After commit 9425ef3f990a ("migration: Use migrate_has_error() in
close_return_path_on_source()"), close_return_path_on_source() assumes
Hi Igor,
This is the first steps to decouple the isapc VS q35/i440fx
machines. A new TYPE_PC_PCI_MACHINE is introduced to help
differentiating. Fields unrelated to the legacy isapc are
moved to the new PcPciMachineState structure.
More work remain in hw/i386/pc_piix.c so we can build a
binary wit
On 28/03/2024 17:09, Peter Xu wrote:
External email: Use caution opening links or attachments
On Thu, Mar 28, 2024 at 04:02:51PM +0200, Avihai Horon wrote:
After commit 9425ef3f990a ("migration: Use migrate_has_error() in
close_return_path_on_source()"), close_return_path_on_source() assumes
When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. In
particular because type array declared with such macro
are easier to review.
In few commits we are going to add more types, so replace
the type_register_static() to ease further reviews.
Introduce TYPE_PC_PCI_MACHINE for machines where PCI
is expected (as opposition to the ISA-only PC machine).
This type inherits from the well known TYPE_PC_MACHINE.
Convert I440FX/PIIX and Q35 machines to use it.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 25 +
Currently PC machines are based on TYPE_PC_MACHINE.
In preparation of being based on different types,
pass the current type as argument.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 4 ++--
hw/i386/pc_piix.c| 9 +
hw/i386/pc_q35.c | 3 ++-
3 files changed, 9 i
The 'pci_root_uid' field is irrelevant for non-PCI
machines, restrict it to the PcPciMachineClass.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 4 +++-
hw/i386/acpi-build.c | 9 +++--
hw/i386/pc_piix.c| 7 +--
hw/i386/pc_q35.c | 7 +--
4 files changed, 20
Since only PCI-based machines use the 'acpi_build_enabled',
move it to PcPciMachineState.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/acpi-build.h | 2 +-
include/hw/i386/pc.h | 3 ++-
hw/i386/acpi-build.c | 8
hw/i386/pc.c | 5 ++---
hw/i386/xen/xen-hvm.c | 3 ++-
5 f
All TYPE_PC_PCI_MACHINE-based machines have pci_enabled
set to %true. By checking a TYPE_PC_MACHINE inherits the
TYPE_PC_PCI_MACHINE base class, we don't need this field
anymore.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 1 -
hw/i386/pc.c | 3 +--
hw/i386/pc_piix.c
PCMachineClass::has_acpi_build is always %true for PCI
based machines. Remove it, setting the 'acpi_build_enabled'
field once in pc_pci_machine_initfn().
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 3 ---
hw/i386/pc.c | 6 +++---
hw/i386/pc_piix.c| 1 -
3 files c
acpi_setup() caller knows about the machine state, so pass
it as argument to avoid a qdev_get_machine() call.
We already resolved X86_MACHINE(pcms) as 'x86ms' so use the
latter.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/acpi-build.h | 3 ++-
hw/i386/acpi-build.c | 5 ++---
hw/i386/pc.c
South bridge type is only relevant for the i440fx/piix
machine, which is PCI-based.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 8
hw/i386/pc.c | 3 ++-
hw/i386/pc_piix.c| 12 ++--
3 files changed, 12 insertions(+), 11 deletions(-)
diff --git
Introduce the pc_machine_is_pci_enabled() helper to be
able to alter PCMachineClass fields later.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 2 ++
hw/i386/pc.c | 11 +--
hw/i386/pc_piix.c| 11 ++-
hw/i386/pc_q35.c | 2 +-
hw/i386/pc_sysfw.c
pc_pci_hole64_start() is only used by PCI-based
machines. Pass it a PcPciMachineState argument,
removing a qdev_get_machine() call.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 2 +-
hw/i386/pc.c | 8
hw/pci-host/i440fx.c | 2 +-
hw/pci-host/q35.c| 2 +-
All PCI-based machines have the smbios_defaults field
set to %true. Simplify by using an inlined helper
checking whether the machine is PCI-based or not.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 1 -
hw/i386/fw_cfg.c | 7 ++-
hw/i386/pc.c | 1 -
hw/i386/pc
All PCI-based machines have the has_reserved_memory
field set to %true. Simplify by using an inlined helper
checking whether the machine is PCI-based or not.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 1 -
hw/i386/pc.c | 17 ++---
hw/i386/pc_piix.c|
All PCI-based machines have the gigabyte_align field
set to %true. Simplify by using an inlined helper
checking whether the machine is PCI-based or not.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 9 -
hw/i386/pc.c | 1 -
hw/i386/pc_piix.c| 16 +
Factor fw_cfg_build_smbios_legacy() out of
fw_cfg_build_smbios().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/fw_cfg.h | 1 +
hw/i386/fw_cfg-smbios-stub.c | 4
hw/i386/fw_cfg.c | 33 ++---
3 files changed, 27 insertions(+), 11 dele
"fw_cfg.h" declares fw_cfg_build_smbios() which use
SmbiosEntryPointType, itself declared in "qapi-types-machine.h".
void fw_cfg_build_smbios(PCMachineState *pcms, FWCfgState *fw_cfg,
SmbiosEntryPointType ep_type);
Signe
smbios_defaults() and smbios_legacy_mode() are logical
opposite. Simplify using the latter.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/fw_cfg.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/hw/i386/fw_cfg.c b/hw/i386/fw_cfg.c
index ffa60a4a33..df05fe060c 100644
acpi_setup() returns early if acpi_build_enabled is not set:
2752 void acpi_setup(PCMachineState *pcms)
2753 {
...
2768 if (!pcms->acpi_build_enabled) {
2769 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2770 return;
2771 }
acpi_build_enabled is
Extract the ISA-only PC machine code from pc_piix.c
to a new file, pc_isa.c.
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 1 +
hw/i386/pc_isa.c| 33 +
hw/i386/pc_piix.c | 23 ---
hw/i386/meson.build | 1 +
4 files cha
Keep fw_cfg_build_smbios() for PCI-based machines, call
fw_cfg_build_smbios_legacy() directly from pc_machine_done().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/fw_cfg.c | 10 --
hw/i386/pc.c | 12 +++-
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/h
Since CXL helpers expect a PCI-based machine, we
can directly pass them a PcPciMachineState argument.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index e36d76656b..d8e91d18b
We are going to refactor fw_cfg_build_smbios() in the
next patches. In order to avoid too much #ifdef'ry in
it, define a stub.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/fw_cfg-smbios-stub.c | 15 +++
hw/i386/fw_cfg.c | 4 ++--
hw/i386/meson.build | 1 +
pc_system_flash_create() is only useful for PCI-based machines.
Move the call to the PCI-based init() handler.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 2 +-
hw/i386/pc_sysfw.c | 10 --
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/hw/i386/pc.c b/h
All PCI-based machines have the smbios_legacy_mode
field set to %false. Simplify by using an inlined
helper checking whether the machine is PCI-based or
not.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 1 -
hw/i386/fw_cfg.c | 8 ++--
hw/i386/pc_piix.c| 2 --
3 fi
fw_cfg_add_extra_pci_roots() expects a PCI bus, which only
PCI-based machines have. No need to call it on the ISA-only
machine. Move it to the PCI-specific machine_done handler.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
Only PCI-based machines use the set of parallel flash devices.
Move the fields from PCMachineState to PcPciMachineState.
Directly pass a PcPciMachineState argument to the
pc_system_flash/fw methods.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 10
hw/i386/pc.c
pc_init1() is specific to the isapc and i440fx/piix machines,
rename it as pc_piix_init(). Expose it in "hw/i386/pc.h" to
be able to call it externally (see next patch).
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 1 +
hw/i386/pc_piix.c| 8
hw/isa/piix.c
On Sun, 24 Mar 2024 at 16:56, Arnaud Minier
wrote:
>
> Add the basic infrastructure (register read/write, type...)
> to implement the STM32L4x5 USART.
>
> Also create different types for the USART, UART and LPUART
> of the STM32L4x5 to deduplicate code and enable the
> implementation of different
CXL depends on PCIe, which isn't available on non-PCI
machines such the ISA-only PC one.
Move CXLState to PcPciMachineState, and move the CXL
specific calls to pc_pci_machine_initfn() and
pc_pci_machine_done().
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 3 ++-
hw/i386/acpi
On Sun, 24 Mar 2024 at 16:57, Arnaud Minier
wrote:
>
> Implement the ability to read and write characters to the
> usart using the serial port.
>
> The character transmission is based on the
> cmsdk-apb-uart implementation.
>
> Signed-off-by: Arnaud Minier
> Signed-off-by: Inès Varhol
> +/* Tr
x86_bios_rom_init() is the single non-PCI-machine call
from pc_system_firmware_init(). Extract it to the caller.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 6 +-
hw/i386/pc_sysfw.c | 5 +
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/hw/i386/pc.c b/hw
On Sun, 24 Mar 2024 at 16:57, Arnaud Minier
wrote:
>
> Add a function to change the settings of the
> serial connection.
>
> Signed-off-by: Arnaud Minier
> Signed-off-by: Inès Varhol
> ---
> hw/char/stm32l4x5_usart.c | 98 +++
> hw/char/trace-events | 1
On Sun, 24 Mar 2024 at 16:57, Arnaud Minier
wrote:
>
> Add the USART to the SoC and connect it to the other implemented devices.
>
> Signed-off-by: Arnaud Minier
> Signed-off-by: Inès Varhol
> ---
> docs/system/arm/b-l475e-iot01a.rst | 2 +-
> hw/arm/Kconfig | 1 +
> hw/ar
On Sun, 24 Mar 2024 at 16:56, Arnaud Minier
wrote:
>
> This patch adds the STM32L4x5 USART
> (Universal Synchronous/Asynchronous Receiver/Transmitter)
> device and is part of a series implementing the
> STM32L4x5 with a few peripherals.
>
> It implements the necessary functionalities to receive/se
On Mon, 25 Mar 2024 at 06:19, Thomas Huth wrote:
> We are now using timeouts from the meson test harneess in meson.build, too,
> see the slow_qtests[] at the beginning of that file.
> You seem to be using a 10 minutes timeout in your test below
> (usart_wait_for_flag() function), but you didn't ad
Extend the virtio device property definitions to include the
VIRTIO_F_IN_ORDER feature.
The default state of this feature is disabled, allowing it to be
explicitly enabled where it's supported.
Acked-by: Eugenio Pérez
Signed-off-by: Jonah Palmer
---
include/hw/virtio/virtio.h | 4 +++-
1 file
Initialize sequence variables for VirtQueue and VirtQueueElement
structures. A VirtQueue's sequence variables are initialized when a
VirtQueue is being created or reset. A VirtQueueElement's sequence
variable is initialized when a VirtQueueElement is being initialized.
These variables will be used
Add support for the VIRTIO_F_IN_ORDER feature across a variety of vhost
devices.
The inclusion of VIRTIO_F_IN_ORDER in the feature bits arrays for these
devices ensures that the backend is capable of offering and providing
support for this feature, and that it can be disabled if the backend
does n
Implements VIRTIO_F_IN_ORDER feature support for virtio devices using
the packed virtqueue layout.
For a virtio device that has negotiated the VIRTIO_F_IN_ORDER feature
whose virtqueues use a packed virtqueue layout, it's essential that used
VirtQueueElements are written to the descriptor ring in-
Implements VIRTIO_F_IN_ORDER feature support for virtio devices using
the split virtqueue layout.
For a virtio device that has negotiated the VIRTIO_F_IN_ORDER feature
whose virtqueues use a split virtqueue layout, it's essential that
used VirtQueueElements are written to the used ring in-order.
The goal of these patches is to add support to a variety of virtio and
vhost devices for the VIRTIO_F_IN_ORDER transport feature. This feature
indicates that all buffers are used by the device in the same order in
which they were made available by the driver.
These patches attempt to implement a g
On 3/28/24 16:50, Avihai Horon wrote:
On 28/03/2024 17:21, Cédric Le Goater wrote:
External email: Use caution opening links or attachments
Hello Avihai,
On 3/28/24 15:02, Avihai Horon wrote:
After commit 9425ef3f990a ("migration: Use migrate_has_error() in
close_return_path_on_source()"),
Hardware of sbsa-ref board is nowadays defined by both BSA and SBSA
specifications. Then BBR defines firmware interface.
Added note about DeviceTree data passed from QEMU to firmware. It is
very minimal and provides only data we use in firmware.
Added NUMA information to list of things reported b
On Thu, Mar 28, 2024 at 10:06:01AM -0500, Eric Blake wrote:
> Adjusting cc list to add upstream NBD and drop developers unrelated to
> this part of the qemu series...
>
> On Thu, Mar 28, 2024 at 02:13:42PM +, Richard W.M. Jones wrote:
> > On Thu, Mar 28, 2024 at 03:06:03PM +0100, Thomas Huth w
W dniu 28.03.2024 o 16:43, Peter Maydell pisze:
On Tue, 26 Mar 2024 at 09:58, Marcin Juszkiewicz
wrote:
Hardware of sbsa-ref board is nowadays defined by both BSA and SBSA
specifications. Then BBR defines firmware interface.
Added note about DeviceTree data passed from QEMU to firmware. It is
On Thu, Mar 28, 2024 at 17:38:51 +0100, Marcin Juszkiewicz wrote:
> Hardware of sbsa-ref board is nowadays defined by both BSA and SBSA
> specifications. Then BBR defines firmware interface.
>
> Added note about DeviceTree data passed from QEMU to firmware. It is
> very minimal and provides only d
On Thu, 28 Mar 2024 at 16:39, Marcin Juszkiewicz
wrote:
>
> Hardware of sbsa-ref board is nowadays defined by both BSA and SBSA
> specifications. Then BBR defines firmware interface.
>
> Added note about DeviceTree data passed from QEMU to firmware. It is
> very minimal and provides only data we u
On Thu, Mar 28, 2024 at 04:02:50PM +0200, Avihai Horon wrote:
> Hello,
>
> This small series fixes two migration bugs I stumbled upon recently.
> Comments are welcome, thanks for reviewing.
>
> Avihai Horon (2):
> migration: Set migration error in migration_completion()
> migration/postcopy:
On 28/3/24 16:40, aidan_le...@selinc.com wrote:
From: aidaleuc
Signed-off-by: aidaleuc
---
qga/commands-common-ssh.c | 50 ++
qga/commands-common-ssh.h | 10
qga/commands-posix-ssh.c | 51 +++
qga/meson.buil
On 28/03/2024 14.02, Philippe Mathieu-Daudé wrote:
The whole RDMA subsystem was deprecated in commit e9a54265f5
("hw/rdma: Deprecate the pvrdma device and the rdma subsystem")
released in v8.2.
Remove:
- PVRDMA device
- generated vmw_pvrdma/ directory from linux-headers
- rdmacm-mux tool f
On 28/03/2024 14.02, Philippe Mathieu-Daudé wrote:
GlusterFS+RDMA has been deprecated 8 years ago in commit
0552ff2465 ("block/gluster: deprecate rdma support"):
gluster volfile server fetch happens through unix and/or tcp,
it doesn't support volfile fetch over rdma. The rdma code may
a
Fixes: 83b4613ba83 ("disas: introduce show_opcodes")
Signed-off-by: Richard Henderson
---
disas/disas-mon.c | 1 +
disas/disas.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/disas/disas-mon.c b/disas/disas-mon.c
index 48ac492c6c..5d6d9aa02d 100644
--- a/disas/disas-mon.c
+++ b/disas/
On 3/28/24 05:33, Peter Maydell wrote:
If the group of the highest priority pending interrupt is disabled
via ICC_IGRPEN*, the ICC_HPPIR* registers should return
INTID_SPURIOUS, not the interrupt ID. (See the GIC architecture
specification pseudocode functions ICC_HPPIR1_EL1[] and
HighestPriorit
On Thu, 28 Mar 2024, Philippe Mathieu-Daudé wrote:
acpi_setup() caller knows about the machine state, so pass
it as argument to avoid a qdev_get_machine() call.
We already resolved X86_MACHINE(pcms) as 'x86ms' so use the
latter.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/acpi-build.h |
On Thu, 28 Mar 2024, Philippe Mathieu-Daudé wrote:
x86_bios_rom_init() is the single non-PCI-machine call
from pc_system_firmware_init(). Extract it to the caller.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 6 +-
hw/i386/pc_sysfw.c | 5 +
2 files changed, 6 insertions(
On Thu, 28 Mar 2024, Philippe Mathieu-Daudé wrote:
pc_system_flash_create() is only useful for PCI-based machines.
Move the call to the PCI-based init() handler.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 2 +-
hw/i386/pc_sysfw.c | 10 --
2 files changed, 5 insertions
On Thu, Mar 28, 2024 at 04:22:27PM +0100, Thomas Huth wrote:
> Since e9a54265f5 was not very clear about rdma migration code, should we
> maybe rather add a separate deprecation note for the migration part, and add
> a proper warning message to the migration code in case someone tries to use
> it t
This is a series of patches for adding support for the Branch History
Rolling Buffer (BHRB) facility. This was added to the Power ISA
starting with version 2.07. Changes were subsequently made in version
3.1 to limit BHRB recording to instructions run in problem state only
and to add a control bi
Add support for the clrbhrb and mfbhrbe instructions.
Since neither instruction is believed to be critical to
performance, both instructions were implemented using helper
functions.
Access to both instructions is controlled by bits in the
HFSCR (for privileged state) and MMCR0 (for problem state)
This commit is preparatory to the addition of Branch History
Rolling Buffer (BHRB) functionality, which is being provided
today starting with the P8 processor.
BHRB uses several SPR register fields to control whether or not
a branch instruction's address (and sometimes target address)
should be re
Adds migration support for Branch History Rolling
Buffer (BHRB) internal state.
Signed-off-by: Glenn Miles
Reviewed-by: Nicholas Piggin
---
Changes from v3:
- Rebased onto latest master branch
target/ppc/machine.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/ta
This commit continues adding support for the Branch History
Rolling Buffer (BHRB) as is provided starting with the P8
processor and continuing with its successors. This commit
is limited to the recording and filtering of taken branches.
The following changes were made:
- Enabled functionality
On Mon, 25 Mar 2024 at 08:52, Jinjie Ruan wrote:
>
> Implement icv_nmiar1_read() for icc_nmiar1_read(), so add definition for
> ICH_LR_EL2.NMI and ICH_AP1R_EL2.NMI bit.
>
> If FEAT_GICv3_NMI is supported, ich_ap_write() should consider
> ICV_AP1R_EL1.NMI
> bit. In icv_activate_irq() and icv_eoir_
On Thu, Mar 28, 2024 at 02:20:44PM +0400, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau
>
> ../migration/block.c:966:16: error: ‘ret’ may be used uninitialized
> [-Werror=maybe-uninitialized]
>
> Given that "cluster_size" must be <= BLK_MIG_BLOCK_SIZE, the previous
> loop is ente
On Thu, Mar 28, 2024 at 02:20:48PM +0400, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau
>
> ../migration/ram.c:1873:23: error: ‘dirty’ may be used uninitialized
> [-Werror=maybe-uninitialized]
>
> When 'block' != NULL, 'dirty' is initialized.
>
> Signed-off-by: Marc-André Lureau
On Thu, Mar 28, 2024 at 02:20:45PM +0400, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau
>
> ../migration/dirtyrate.c:186:5: error: ‘records’ may be used uninitialized
> [-Werror=maybe-uninitialized]
> ../migration/dirtyrate.c:168:12: error: ‘gen_id’ may be used uninitialized
> [-
It was noticed that my linux.vnet.ibm.com address does not
always work so dropping the vnet to see if that works better.
Signed-off-by: Glenn Miles
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index a07af6b9d4..575ac2e05d 100644
--
Richard Henderson writes:
> On 3/23/24 22:09, Sven Schnelle wrote:
>> The CPU seems to mask a few bits in the offset when running
>> under HP-UX. ISR/IOR register contents for an address in
>> the processor HPA (0xfffa) on my C8000 and J6750:
>> running on Linux: 3fff c000
On Thu, 28 Mar 2024, Rene Engel wrote:
I wanted to discuss this topic with you again, there was already a patch series
that worked well under Qemu with
Pegasos2/AmigaOneXe/Same460 and AmigaOs4.1. The option zoom-to-fit=on should be
used to adjust all resolutions provided by the guest
system to
* BALATON Zoltan (bala...@eik.bme.hu) wrote:
> On Sun, 24 Mar 2024, Dr. David Alan Gilbert wrote:
> > * Philippe Mathieu-Daudé (phi...@linaro.org) wrote:
> > > Replace qemu_printf() by monitor_printf() / monitor_puts() in monitor.
> > >
> > > Signed-off-by: Philippe Mathieu-Daudé
> > > ---
> > >
On Thu, 28 Mar 2024, Dr. David Alan Gilbert wrote:
* BALATON Zoltan (bala...@eik.bme.hu) wrote:
On Sun, 24 Mar 2024, Dr. David Alan Gilbert wrote:
* Philippe Mathieu-Daudé (phi...@linaro.org) wrote:
Replace qemu_printf() by monitor_printf() / monitor_puts() in monitor.
Signed-off-by: Philippe
When a memory device, such as CXL1.1 type3 memory, is emulated as
normal memory (E820_TYPE_RAM), the memory device is indistinguishable
from normal DRAM in terms of memory tiering with the current implementation.
The current memory tiering assigns all detected normal memory nodes
to the same DRAM t
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