[RFC QEMU PATCH v7 1/1] virtio-pci: implement No_Soft_Reset bit

In current code, when guest does S3, virtio devices are reset due to the bit No_Soft_Reset is not set. After resetting, the display resources of virtio-gpu are destroyed, then the display can't come back and only show blank after resuming. Implement No_Soft_Reset bit of PCI_PM_CTRL register, then

[RFC QEMU PATCH v7 0/1] S3 support

Hi all, This is the v7 patch to support S3. v7 makes below changes: * Tested this patch with Qemu on Xen hypervisor. Depending on kernel patch (virtio: Add support for no-reset virtio PCI PM: https://lore.kernel.org/lkml/20231208070754.3132339-1-steve...@chromium.org/) * Changed the default val

Re: [PATCH-for-9.1] target/ppc: Unify TYPE_POWERPC_CPU definition for 32/64-bit

On 22/03/2024 19.34, Philippe Mathieu-Daudé wrote: Apparently there is no wordsize special use with the QOM TYPE_POWERPC_CPU typename. Unify 32 and 64-bit with a single common definition. Signed-off-by: Philippe Mathieu-Daudé --- target/ppc/cpu-qom.h | 4 1 file changed, 4 deletions(-)

Re: [PATCH 03/26] confidential guest support: Add kvm_init() and kvm_reset() in class

Hi Xiaoyao, On 22/3/24 19:10, Paolo Bonzini wrote: From: Xiaoyao Li Different confidential VMs in different architectures all have the same needs to do their specific initialization (and maybe resetting) stuffs with KVM. Currently each of them exposes individual *_kvm_init() functions and let

[PATCH v2 0/5] target/riscv: Support Zve32x and Zve64x extensions

This patch series adds the support for Zve32x and Zvx64x and makes vector registers visible in GDB if any of the V/Zve*/Zvk* extensions is enabled. v2: Rebase onto riscv-to-apply.next (commit 385e575). Jason Chien (5): target/riscv: Add support for Zve32x extension target/riscv: Expose Zv

[PATCH v2 3/5] target/riscv: Add support for Zve64x extension

Add support for Zve64x extension. Enabling Zve64f enables Zve64x and enabling Zve64x enables Zve32x according to their dependency. Signed-off-by: Jason Chien Reviewed-by: Frank Chang Reviewed-by: Max Chou --- target/riscv/cpu.c | 1 + target/riscv/cpu_cfg.h | 1 + target/riscv/tc

[PATCH v2 5/5] target/riscv: Relax vector register check in RISCV gdbstub

In current implementation, the gdbstub allows reading vector registers only if V extension is supported. However, all vector extensions and vector crypto extensions have the vector registers and they all depend on Zve32x. The gdbstub should check for Zve32x instead. Signed-off-by: Jason Chien Rev

[PATCH v2 4/5] target/riscv: Expose Zve64x extension to users

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107 Signed-off-by: Jason Chien Reviewed-by: Frank Chang Reviewed-by: Max Chou --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f6287bf892..18e1ae66f4 100644 --- a/tar

[PATCH v2 2/5] target/riscv: Expose Zve32x extension to users

Signed-off-by: Jason Chien Reviewed-by: Frank Chang Reviewed-by: Max Chou --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 851ac7372c..6bd8798bb5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1473,6 +1473,7 @

[PATCH v2 1/5] target/riscv: Add support for Zve32x extension

Add support for Zve32x extension and replace some checks for Zve32f with Zve32x, since Zve32f depends on Zve32x. Signed-off-by: Jason Chien Reviewed-by: Frank Chang Reviewed-by: Max Chou --- target/riscv/cpu.c | 1 + target/riscv/cpu_cfg.h | 1 + target/

Re: [PATCH-for-9.0 1/2] hw/clock: Let clock_set_mul_div() return boolean value

On 16:58 Fri 22 Mar , Philippe Mathieu-Daudé wrote: > Let clock_set_mul_div() return a boolean value whether the > clock has been updated or not, similarly to clock_set(). > > Signed-off-by: Philippe Mathieu-Daudé Acked-by: Luc Michel > --- > include/hw/clock.h | 4 +++- > hw/core/clock.c

[PATCH v10 07/23] target/arm: Add support for NMI in arm_phys_excp_target_el()

According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt with superpriority is always IRQ, never FIQ, so handle NMI same as IRQ in arm_phys_excp_target_el(). Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson --- v4: - Add Reviewed-by. v3: - Remove nmi_is_irq flag in CPUA

[PATCH v10 05/23] target/arm: Support MSR access to ALLINT

Support ALLINT msr access as follow: mrs , ALLINT// read allint msr ALLINT, // write allint with imm Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson --- v9: - Move nmi_reginfo and related functions inside an existing ifdef TARGET_AARCH64 to solve the -

[PATCH v10 02/23] target/arm: Add PSTATE.ALLINT

When PSTATE.ALLINT is set, an IRQ or FIQ interrupt that is targeted to ELx, with or without superpriority is masked. As Richard suggested, place ALLINT bit in PSTATE in env->pstate. With the change to pstate_read/write, exception entry and return are automatically handled. Signed-off-by: Jinjie

[PATCH v10 20/23] hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update()

In CPU Interface, if the IRQ has the non-maskable property, report NMI to the corresponding PE. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson --- v10: - superprio -> nmi. - Update the commit message, superpriority -> non-maskable. v6: - Add Reviewed-by. v4: - Swap the ordering of the

[PATCH v10 06/23] target/arm: Add support for Non-maskable Interrupt

This only implements the external delivery method via the GICv3. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson --- v10: - In arm_cpu_exec_interrupt(), if SCTLR_ELx.NMI is 0, NMI -> IRQ, VINMI -> VIRQ, VFNMI -> VFIQ. - Make arm_cpu_update_virq() and arm_cpu_update_vfiq() check that

[PATCH v10 00/23] target/arm: Implement FEAT_NMI and FEAT_GICv3_NMI

This patch set implements FEAT_NMI and FEAT_GICv3_NMI for armv8. These introduce support for a new category of interrupts in the architecture which we can use to provide NMI like functionality. There are two modes for using this FEAT_NMI. When PSTATE.ALLINT or PSTATE.SP & SCTLR_ELx.SCTLR_SPINTMASK

[PATCH v10 03/23] target/arm: Add support for FEAT_NMI, Non-maskable Interrupt

Add support for FEAT_NMI. NMI (FEAT_NMI) is an mandatory feature in ARMv8.8-A and ARM v9.3-A. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson --- v3: - Add Reviewed-by. - Adjust to before the MSR patches. --- target/arm/internals.h | 3 +++ 1 file changed, 3 insertions(+) diff --git

[PATCH v10 13/23] hw/intc: Enable FEAT_GICv3_NMI Feature

Added properties to enable FEAT_GICv3_NMI feature, setup distributor and redistributor registers to indicate NMI support. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson --- v10: - Adjust to before add irq non-maskable property. v4: - Add Reviewed-by. --- hw/intc/arm_gicv3_common.c

[PATCH v10 12/23] target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64()

According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt with superpriority is always IRQ, never FIQ, so the NMI exception trap entry behave like IRQ. And VINMI(vIRQ with Superpriority) can be raised from the GIC or come from the hcrx_el2.HCRX_VINMI bit, VFNMI(vFIQ with Superpriori

[PATCH v10 22/23] target/arm: Add FEAT_NMI to max

Enable FEAT_NMI on the 'max' CPU. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson --- v3: - Add Reviewed-by. - Sorted to last. --- docs/system/arm/emulation.rst | 1 + target/arm/tcg/cpu64.c| 1 + 2 files changed, 2 insertions(+) diff --git a/docs/system/arm/emulation.rst b/d

[PATCH v10 18/23] hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read()

Implement icv_nmiar1_read() for icc_nmiar1_read(), so add definition for ICH_LR_EL2.NMI and ICH_AP1R_EL2.NMI bit. If FEAT_GICv3_NMI is supported, ich_ap_write() should consider ICV_AP1R_EL1.NMI bit. In icv_activate_irq() and icv_eoir_write(), the ICV_AP1R_EL1.NMI bit should be set or clear accordi

[PATCH v10 15/23] hw/intc/arm_gicv3_redist: Implement GICR_INMIR0

Add GICR_INMIR0 register and support access GICR_INMIR0. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson --- v10: - gicr_isuperprio -> gicr_inmir0. v6: - Add Reviewed-by. v4: - Make the GICR_INMIR0 implementation more clearer. --- hw/intc/arm_gicv3_redist.c | 19 +++ h

[PATCH v10 11/23] hw/intc/arm_gicv3: Add external IRQ lines for NMI

Augment the GICv3's QOM device interface by adding one new set of sysbus IRQ line, to signal NMI to each CPU. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson --- v4: - Add Reviewed-by. v3: - Add support for VNMI. --- hw/intc/arm_gicv3_common.c | 6 ++ include/hw/intc/arm_g

[PATCH v10 10/23] hw/arm/virt: Wire NMI and VINMI irq lines from GIC to CPU

Wire the new NMI and VINMI interrupt line from the GIC to each CPU. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson --- v9: - Rename ARM_CPU_VNMI to ARM_CPU_VINMI. - Update the commit message. v4: - Add Reviewed-by. v3: - Also add VNMI wire. --- hw/arm/virt.c | 7 ++- 1 file chang

[PATCH v10 23/23] hw/arm/virt: Add FEAT_GICv3_NMI feature support in virt GIC

A PE that implements FEAT_NMI and FEAT_GICv3 also implements FEAT_GICv3_NMI. A PE that does not implement FEAT_NMI, does not implement FEAT_GICv3_NMI So included support FEAT_GICv3_NMI feature as part of virt platform GIC initialization if FEAT_NMI and FEAT_GICv3 supported. Signed-off-by: Jinjie

[PATCH v10 04/23] target/arm: Implement ALLINT MSR (immediate)

Add ALLINT MSR (immediate) to decodetree, in which the CRm is 0b000x. The EL0 check is necessary to ALLINT, and the EL1 check is necessary when imm == 1. So implement it inline for EL2/3, or EL1 with imm==0. Avoid the unconditional write to pc and use raise_exception_ra to unwind. Signed-off-by: J

[PATCH v10 21/23] hw/intc/arm_gicv3: Report the VINMI interrupt

In vCPU Interface, if the vIRQ has the non-maskable property, report vINMI to the corresponding vPE. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson --- v10: - Update the commit message, superpriority -> non-maskable. v9: - Update the commit subject and message, vNMI -> vINMI. v6: - Ad

[PATCH v10 19/23] hw/intc/arm_gicv3: Implement NMI interrupt prioirty

If GICD_CTLR_DS bit is zero and the NMI is non-secure, the NMI prioirty is higher than 0x80, otherwise it is higher than 0x0. And save NMI super prioirty information in hppi.superprio to deliver NMI exception. Since both GICR and GICD can deliver NMI, it is both necessary to check whether the pendi

[PATCH v10 16/23] hw/intc/arm_gicv3: Implement GICD_INMIR

Add GICD_INMIR, GICD_INMIRnE register and support access GICD_INMIR0. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson --- v10: - superprio -> nmi. v4: - Make the GICD_INMIR implementation more clearer. - Udpate the commit message. v3: - Add Reviewed-by. --- hw/intc/arm_gicv3_dist.c |

[PATCH v10 09/23] target/arm: Handle PSTATE.ALLINT on taking an exception

Set or clear PSTATE.ALLINT on taking an exception to ELx according to the SCTLR_ELx.SPINTMASK bit. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson --- v9: - Not check SCTLR_NMI in arm_cpu_do_interrupt_aarch64(). v3: - Add Reviewed-by. --- target/arm/helper.c | 8 1 file chang

[PATCH v10 17/23] hw/intc/arm_gicv3: Add NMI handling CPU interface registers

Add the NMIAR CPU interface registers which deal with acknowledging NMI. When introduce NMI interrupt, there are some updates to the semantics for the register ICC_IAR1_EL1 and ICC_HPPIR1_EL1. For ICC_IAR1_EL1 register, it should return 1022 if the intid has non-maskable property. And for ICC_NMIA

[PATCH v10 01/23] target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NMI

FEAT_NMI defines another three new bits in HCRX_EL2: TALLINT, HCRX_VINMI and HCRX_VFNMI. When the feature is enabled, allow these bits to be written in HCRX_EL2. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson --- v9: - Declare cpu variable to reuse latter. v4: - Update the comment for

[PATCH v10 14/23] hw/intc/arm_gicv3: Add irq non-maskable property

A SPI, PPI or SGI interrupt can have non-maskable property. So maintain non-maskable property in PendingIrq and GICR/GICD. Since add new device state, it also needs to be migrated, so also save NMI info in vmstate_gicv3_cpu and vmstate_gicv3. Signed-off-by: Jinjie Ruan Acked-by: Richard Henderson

[PATCH v10 08/23] target/arm: Handle IS/FS in ISR_EL1 for NMI, VINMI and VFNMI

Add IS and FS bit in ISR_EL1 and handle the read. With CPU_INTERRUPT_NMI or CPU_INTERRUPT_VINMI, both CPSR_I and ISR_IS must be set. With CPU_INTERRUPT_VFNMI, both CPSR_F and ISR_FS must be set. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson --- v9: - CPU_INTERRUPT_VNMI -> CPU_INTERRU

Re: [PATCH v8] arm/kvm: Enable support for KVM_ARM_VCPU_PMU_V3_FILTER

On Mon, Mar 25, 2024 at 01:35:58PM +0800, Shaoqin Huang wrote: > Hi Daniel, > > Thanks for your reviewing. I see your comments in the v7. > > I have some doubts about what you said about the QAPI. Do you want me to > convert the current design into the QAPI parsing like the > IOThreadVirtQueueMap

Re: [PATCH-for-9.0 2/2] hw/misc/stm32l4x5_rcc: Propagate period when enabling a clock

On 16:39 Fri 22 Mar , Peter Maydell wrote: > On Fri, 22 Mar 2024 at 15:59, Philippe Mathieu-Daudé > wrote: > > > > From: Arnaud Minier > > > > The "clock_set_mul_div" function doesn't propagate the clock period > > to the children if it is changed (e.g. by enabling/disabling a clock > > mult

Re: [PATCH 11/26] runstate: skip initial CPU reset if reset is not actually possible

On Fri, Mar 22, 2024 at 07:11:01PM +0100, Paolo Bonzini wrote: > Right now, the system reset is concluded by a call to > cpu_synchronize_all_post_reset() in order to sync any changes > that the machine reset callback applied to the CPU state. > > However, for VMs with encrypted state such as SEV-E

Re: [PATCH-for-9.0 1/2] hw/clock: Let clock_set_mul_div() return boolean value

On 09:40 Mon 25 Mar , Luc Michel wrote: > On 16:58 Fri 22 Mar , Philippe Mathieu-Daudé wrote: > > Let clock_set_mul_div() return a boolean value whether the > > clock has been updated or not, similarly to clock_set(). > > > > Signed-off-by: Philippe Mathieu-Daudé > > Acked-by: Luc Michel

Re: [PULL 20/34] tests/libqos: add riscv/virt machine nodes

On 08/03/2024 12.11, Alistair Francis wrote: From: Daniel Henrique Barboza Add a RISC-V 'virt' machine to the graph. This implementation is a modified copy of the existing arm machine in arm-virt-machine.c It contains a virtio-mmio and a generic-pcihost controller. The generic-pcihost controll

Re: [PATCH 12/26] KVM: track whether guest state is encrypted

On 22/3/24 19:11, Paolo Bonzini wrote: So far, KVM has allowed KVM_GET/SET_* ioctls to execute even if the guest state is encrypted, in which case they do nothing. For the new API using VM types, instead, the ioctls will fail which is a safer and more robust approach. The new API will be the on

Re: [PATCH 13/26] KVM: remove kvm_arch_cpu_check_are_resettable

On 22/3/24 19:11, Paolo Bonzini wrote: Board reset requires writing a fresh CPU state. As far as KVM is concerned, the only thing that blocks reset is that CPU state is encrypted; therefore, kvm_cpus_are_resettable() can simply check if that is the case. Signed-off-by: Paolo Bonzini --- incl

Re: [PATCH 15/26] target/i386: Implement mc->kvm_type() to get VM type

On 22/3/24 19:11, Paolo Bonzini wrote: KVM is introducing a new API to create confidential guests, which will be used by TDX and SEV-SNP but is also available for SEV and SEV-ES. The API uses the VM type argument to KVM_CREATE_VM to identify which confidential computing technology to use. Since

Re: [PATCH RESEND v3 0/3] i386: Fix Hyper-V Gen1 guests stuck on boot with 'hv-passthrough'

Vitaly Kuznetsov writes: > Changes since 'RESEND v2': > - Included 'docs/system: Add recommendations to Hyper-V enlightenments doc' > in the set as it also requires a "RESEND") Ping) > > Hyper-V Gen1 guests are getting stuck on boot when 'hv-passthrough' is > used. While 'hv-passthrough' is a

Re: [PATCH 18/26] kvm: Introduce support for memory_attributes

On 22/3/24 19:11, Paolo Bonzini wrote: From: Xiaoyao Li Introduce the helper functions to set the attributes of a range of memory to private or shared. This is necessary to notify KVM the private/shared attribute of each gpa range. KVM needs the information to decide the GPA needs to be mapped

Re: [PATCH 11/26] runstate: skip initial CPU reset if reset is not actually possible

On 22/3/24 19:11, Paolo Bonzini wrote: Right now, the system reset is concluded by a call to cpu_synchronize_all_post_reset() in order to sync any changes that the machine reset callback applied to the CPU state. However, for VMs with encrypted state such as SEV-ES guests (currently the only cas

Let's close member documentation gaps

If you're cc'ed, I have a bit of doc work for you. Search for your name to find it. The QAPI generator forces you to document your stuff. Except for commands, events, enum and object types listed in pragma documentation-exceptions, the generator silently defaults missing documentation to "Not do

Re: [PATCH 01/10] qtest/phb4: Add testbench for PHB4

Hello Saif, On 3/21/24 11:04, Saif Abrar wrote: New qtest TB added for PHB4. TB reads PHB Version register and asserts that bits[24:31] have value 0xA5. Signed-off-by: Saif Abrar --- tests/qtest/meson.build | 1 + tests/qtest/pnv-phb4-test.c | 74 +

Re: [PATCH v2 0/2] ARM Sbsa-ref: Enable CPU cluster topology

> W dniu 22.03.2024 o 19:51, Peter Maydell pisze: > > On Tue, 12 Mar 2024 at 08:32, Xiong Yining > > >> xiongyining1480 (2): > >>hw/arm/sbsa-ref:Enable CPU cluster on ARM sbsa machine > >>hw/arm/sbsa-ref: Add cpu-map to device tree > > > > Thanks for these patches. I think we should squas

Re: [PATCH 1/3] targt/hppa: Fix DCOR reconstruction of carry bits

On 3/25/24 04:04, Richard Henderson wrote: The carry bits for each nibble N are located in bit (N+1)*4, so the shift by 3 was off by one. Furthermore, the carry bit for the most significant carry bit is indeed located in bit 64, which is located in a different storage word. Use a double-word sh

Re: [PATCH 2/3] target/hppa: Optimize UADDCM with no condition

On 3/25/24 04:04, Richard Henderson wrote: With r1 as zero is by far the only usage of UADDCM, as the easiest way to invert a register. The compiler does occasionally use the addition step as well, and we can simplify that to avoid a temp and write directly into the destination. Signed-off-by:

[PATCH] qapi: document InputMultiTouchType

From: Marc-André Lureau Signed-off-by: Marc-André Lureau --- qapi/ui.json | 12 1 file changed, 12 insertions(+) diff --git a/qapi/ui.json b/qapi/ui.json index 5744c24e3c..53d9143054 100644 --- a/qapi/ui.json +++ b/qapi/ui.json @@ -1080,6 +1080,16 @@ # # Type of a multi-touch ev

Re: [PATCH v2] contrib/plugins/execlog: Fix compiler warning

On Mon, 25 Mar 2024 at 06:41, Pierrick Bouvier wrote: > > On 3/25/24 10:06, Yao Xingtao wrote: > > diff --git a/contrib/plugins/execlog.c b/contrib/plugins/execlog.c > > index a1dfd59ab7..09654910ee 100644 > > --- a/contrib/plugins/execlog.c > > +++ b/contrib/plugins/execlog.c > > @@ -327,8 +327,1

Re: [PULL 1/1] target/loongarch: Fix qemu-system-loongarch64 assert failed with the option '-d int'

Cc: qemu-sta...@nongnu.org 在 2024/3/22 下午10:58, Michael Tokarev 写道: 22.03.2024 13:03, Song Gao : qemu-system-loongarch64 assert failed with the option '-d int', the helper_idle() raise an exception EXCP_HLT, but the exception name is undefined. Signed-off-by: Song Gao Reviewed-by: Philippe

Re: [PATCH] qapi: document InputMultiTouchType

marcandre.lur...@redhat.com writes: > From: Marc-André Lureau > > Signed-off-by: Marc-André Lureau Reviewed-by: Markus Armbruster Queued, thanks!

Re: [RFC v2 2/2] hw/riscv: Add server platform reference machine

On 3/23/2024 3:14 AM, Atish Kumar Patra wrote: > On Tue, Mar 12, 2024 at 6:53 AM Fei Wu wrote: >> >> The RISC-V Server Platform specification[1] defines a standardized set >> of hardware and software capabilities, that portable system software, >> such as OS and hypervisors can rely on being prese

[RFC PATCH 03/12] hw/arm/smmu: Add stage to TLB

TLBs for nesting will be extended to be combined, a new index is added "stage", with 2 valid values: - SMMU_STAGE_1: Meaning this translates VA to PADDR, this entry can be cached from fully nested configuration or from stage-1 only. We don't support separate cached entries (VA to IPA) - SM

[RFC PATCH 02/12] hw/arm/smmu: Split smmuv3_translate()

smmuv3_translate() does everything from STE/CD parsing to TLB lookup and PTW. Soon, when nesting is supported, stage-1 data (tt, CD) needs to be translated using stage-2. Split smmuv3_translate() to 3 functions: - smmu_translate(): in smmu-common.c, which does the TLB lookup, PTW, TLB insertio

[RFC PATCH 06/12] hw/arm/smmuv3: Translate CD and TT using stage-2 table

According to the user manual (ARM IHI 0070 F.b), In "5.2 Stream Table Entry": [51:6] S1ContextPtr If Config[1] == 1 (stage 2 enabled), this pointer is an IPA translated by stage 2 and the programmed value must be within the range of the IAS. In "5.4.1 CD notes": The translation table walks per

[RFC PATCH 00/12] SMMUv3 nested translation support

Currently, QEMU supports emulating either stage-1 or stage-2 SMMUs but not nested instances. This patch series adds support for nested translation in SMMUv3, this is controlled by property “arm-smmuv3.stage=nested”, and advertised to guests as (IDR0.S1P == 1 && IDR0.S2P == 2) Main changes(architec

[RFC PATCH 05/12] hw/arm/smmuv3: Support nested SMMUs in smmuv3_notify_iova()

IOMMUTLBEvent only understands IOVA, for stage-2 only SMMUs keep the implementation, while only notify for stage-1 invalidation in case of nesting. Signed-off-by: Mostafa Saleh --- hw/arm/smmuv3.c | 23 +++ hw/arm/trace-events | 2 +- 2 files changed, 16 insertions(+), 9

[RFC PATCH 09/12] hw/arm/smmuv3: Advertise S2FWB

QEMU doesn's support memory attributes, so FWB is NOP, this might change in the future if memory attributre would be supported. Signed-off-by: Mostafa Saleh --- hw/arm/smmuv3.c | 8 1 file changed, 8 insertions(+) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index e5373f4cfe..288e7cf

[RFC PATCH 01/12] hw/arm/smmu: Use enum for SMMU stage

Currently, translation stage is represented as an int, where 1 is stage-1 and 2 is stage-2, when nested is added, 3 would be confusing to represent nesting, so we use an enum instead. While keeping the same values, this is useful for: - Doing tricks with bit masks, where BIT(0) is stage-1 and BIT

[RFC PATCH 04/12] hw/arm/smmu: Support nesting in commands

Commands had assumptions about VMID and ASID being mutually exclusive and the same for stage-1 and stage-2. As we are going to support nesting, we need to implement them properly: - CMD_TLBI_NH_ASID: Used to ignore VMID as it was not used in stage-1 instances, now we read it from the command and

[RFC PATCH 10/12] hw/arm/smmu: Refactor SMMU OAS

SMMUv3 OAS is hardcoded to 44 bits, for nested configurations that can be a problem as stage-2 might be shared with the CPU which might have different PARANGE, and according to SMMU manual ARM IHI 0070F.b: 6.3.6 SMMU_IDR5, OAS must match the system physical address size. This patch doesn't cha

[RFC PATCH 08/12] hw/arm/smmuv3: Support and advertise nesting

Everything is in place, add the last missing bits: - Handle fault checking according to the actual PTW event and not the the translation stage. - Consolidate parsing of STE cfg and setting translation stage. Advertise nesting if stage requested is "nested". Signed-off-by: Mostafa Saleh --- hw

Re: [PATCH v2] contrib/plugins/execlog: Fix compiler warning

On 3/25/24 13:58, Peter Maydell wrote: On Mon, 25 Mar 2024 at 06:41, Pierrick Bouvier wrote: On 3/25/24 10:06, Yao Xingtao wrote: diff --git a/contrib/plugins/execlog.c b/contrib/plugins/execlog.c index a1dfd59ab7..09654910ee 100644 --- a/contrib/plugins/execlog.c +++ b/contrib/plugins/execlo

[RFC PATCH 11/12] hw/arm/smmuv3: Add property for OAS

Add property that sets the OAS of the SMMU, this in not used in this patch. Signed-off-by: Mostafa Saleh --- hw/arm/smmuv3-internal.h | 2 +- hw/arm/smmuv3.c | 27 ++- include/hw/arm/smmuv3.h | 1 + 3 files changed, 28 insertions(+), 2 deletions(-) diff --git

[RFC PATCH 07/12] hw/arm/smmu-common: Support nested translation

When nested translation is requested, we need to do: - Translate stage-1 IPA using stage-2 to a physical address. - Translate stage-1 PTW walks using stage-2. - Combine both to create a single TLB entry Signed-off-by: Mostafa Saleh --- hw/arm/smmu-common.c | 135 +++

[RFC PATCH 12/12] hw/arm/virt: Set SMMU OAS based on CPU PARANGE

Use the new SMMU property to make the SMMU OAS match the CPU PARANGE. That's according to SMMU manual ARM IHI 0070F.b: 6.3.6 SMMU_IDR5, OAS must match the system physical address size. Signed-off-by: Mostafa Saleh --- hw/arm/virt.c | 14 -- target/arm/cpu.h | 2 ++ target

Re: [PATCH v3 02/17] esp.c: replace esp_fifo_pop_buf() with esp_fifo8_pop_buf() in do_command_phase()

On 24/3/24 20:16, Mark Cave-Ayland wrote: The aim is to restrict the esp_fifo_*() functions so that they only operate on the hardware FIFO. When reading from cmdfifo in do_command_phase() use the underlying esp_fifo8_pop_buf() function directly. Signed-off-by: Mark Cave-Ayland --- hw/scsi/esp

Re: [PATCH v3 01/17] esp.c: move esp_fifo_pop_buf() internals to new esp_fifo8_pop_buf() function

On 24/3/24 20:16, Mark Cave-Ayland wrote: Update esp_fifo_pop_buf() to be a simple wrapper onto the new esp_fifo8_pop_buf() function. Signed-off-by: Mark Cave-Ayland --- hw/scsi/esp.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) +static uint32_t esp_fifo_pop_buf(Fifo8 *fi

Re: [PATCH v3 03/17] esp.c: replace esp_fifo_pop_buf() with esp_fifo8_pop_buf() in do_message_phase()

On 24/3/24 20:16, Mark Cave-Ayland wrote: The aim is to restrict the esp_fifo_*() functions so that they only operate on the hardware FIFO. When reading from cmdfifo in do_message_phase() use the underlying esp_fifo8_pop_buf() function directly. Signed-off-by: Mark Cave-Ayland --- hw/scsi/esp

Re: [PATCH v3 12/17] esp.c: prevent cmdfifo overflow in esp_cdb_ready()

On 24/3/24 20:17, Mark Cave-Ayland wrote: During normal use the cmdfifo will never wrap internally and cmdfifo_cdb_offset will always indicate the start of the SCSI CDB. However it is possible that a malicious guest could issue an invalid ESP command sequence such that cmdfifo wraps internally an

Re: [PATCH 3/3] target/hppa: Fix unit carry conditions

On 3/25/24 04:04, Richard Henderson wrote: Split do_unit_cond to do_unit_zero_cond to only handle conditions versus zero. These are the only ones that are legal for UXOR. Simplify trans_uxor accordingly. Rename do_unit to do_unit_addsub, since xor has been split. Properly compute carry-out bit

[PATCH] qapi: document leftover members in qapi/stats.json

Suggested-by: Markus Armbruster Signed-off-by: Paolo Bonzini --- qapi/stats.json | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/qapi/stats.json b/qapi/stats.json index ce9d8161ecb..578b52c7ef7 100644 --- a/qapi/stats.json +++ b/qapi/stats.json @@ -114,13 +114,

[PATCH] qapi: document leftover members in qapi/run-state.json

Suggested-by: Markus Armbruster Signed-off-by: Paolo Bonzini --- qapi/run-state.json | 26 +- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/qapi/run-state.json b/qapi/run-state.json index 789fc34559a..cb4a2b43293 100644 --- a/qapi/run-state.json +++ b/qapi

Re: [PATCH v3 10/17] esp.c: don't assert() if FIFO empty when executing non-DMA SELATNS

On 24/3/24 20:16, Mark Cave-Ayland wrote: The current logic assumes that at least 1 byte is present in the FIFO when executing a non-DMA SELATNS command, but this may not be the case if the guest executes an invalid ESP command sequence. What is real hardware behavior here? Reported-by: Chuh

Re: [PATCH 03/26] confidential guest support: Add kvm_init() and kvm_reset() in class

On Mon, Mar 25, 2024 at 9:33 AM Philippe Mathieu-Daudé wrote: > > Hi Xiaoyao, > > On 22/3/24 19:10, Paolo Bonzini wrote: > > From: Xiaoyao Li > > > > Different confidential VMs in different architectures all have the same > > needs to do their specific initialization (and maybe resetting) stuffs

Re: [PATCH 15/26] target/i386: Implement mc->kvm_type() to get VM type

On Mon, Mar 25, 2024 at 10:29 AM Philippe Mathieu-Daudé wrote: > > On 22/3/24 19:11, Paolo Bonzini wrote: > > KVM is introducing a new API to create confidential guests, which > > will be used by TDX and SEV-SNP but is also available for SEV and > > SEV-ES. The API uses the VM type argument to KV

vhost-user-blk reconnect issue

Hi experts, With latest QEMU (8.2.90), we find two vhost-user-blk backend reconnect failure scenarios: 1. Disconnect vhost-user-blk backend before guest driver probe vblk device, then reconnect backend after guest driver probe device. QEMU won't send out any vhost messages to restore backend. T

Re: [PATCH] hw/s390x: Include missing 'cpu.h' header

On 22/03/2024 17.28, Philippe Mathieu-Daudé wrote: "cpu.h" is implicitly included. Include it explicitly to avoid the following error when refactoring headers: hw/s390x/s390-stattrib.c:86:40: error: use of undeclared identifier 'TARGET_PAGE_SIZE' len = sac->peek_stattr(sas, addr / TAR

Re: [PATCH] virtio_net: Do not send RSS key if it is not supported

Hello Xuan, On Mon, Mar 25, 2024 at 01:57:53PM +0800, Xuan Zhuo wrote: > On Fri, 22 Mar 2024 03:21:21 -0700, Breno Leitao wrote: > > Hello Xuan, > > > > On Fri, Mar 22, 2024 at 10:00:22AM +0800, Xuan Zhuo wrote: > > > On Thu, 21 Mar 2024 09:54:30 -0700, Breno Leitao > > > wrote: > > > > > > 4)

Re: [PATCH] virtio_net: Do not send RSS key if it is not supported

On Mon, 25 Mar 2024 04:26:08 -0700, Breno Leitao wrote: > Hello Xuan, > > On Mon, Mar 25, 2024 at 01:57:53PM +0800, Xuan Zhuo wrote: > > On Fri, 22 Mar 2024 03:21:21 -0700, Breno Leitao wrote: > > > Hello Xuan, > > > > > > On Fri, Mar 22, 2024 at 10:00:22AM +0800, Xuan Zhuo wrote: > > > > On Thu,

Re: [PATCH] qapi: document leftover members in qapi/run-state.json

Paolo Bonzini writes: > Suggested-by: Markus Armbruster > Signed-off-by: Paolo Bonzini > --- > qapi/run-state.json | 26 +- > 1 file changed, 25 insertions(+), 1 deletion(-) > > diff --git a/qapi/run-state.json b/qapi/run-state.json > index 789fc34559a..cb4a2b43293 1006

Re: [PATCH] qapi: document leftover members in qapi/stats.json

Paolo Bonzini writes: > Suggested-by: Markus Armbruster > Signed-off-by: Paolo Bonzini > --- > qapi/stats.json | 14 +- > 1 file changed, 9 insertions(+), 5 deletions(-) > > diff --git a/qapi/stats.json b/qapi/stats.json > index ce9d8161ecb..578b52c7ef7 100644 > --- a/qapi/stats.js

Re: [PULL 08/47] tests/avocado: ppc add hypervisor tests

On Fri, 23 Feb 2024 at 16:00, Nicholas Piggin wrote: > > The powernv and pseries machines both provide hypervisor facilities > that are supported by KVM. This is a large and complicated set of > features that don't get much system-level testing in ppc tests. > > Add a new test case for these which

Re: [PATCH] target/riscv/kvm/kvm-cpu.c: kvm_riscv_handle_sbi() fail with vendor-specific SBI

CCing Anup as well On 3/25/24 07:14, Alexei Filippov wrote: kvm_riscv_handle_sbi() may return not supported return code to not trigger qemu abort with vendor-specific sbi. Added SBI related return code's defines. Please add: Fixes: 4eb47125 ("target/riscv: Handle KVM_EXIT_RISCV_SBI exit")

[PATCH] qapi/block-core: improve Qcow2OverlapCheckFlags documentation

Most of fields have no description at all. Let's fix that. Still, no reason to place here more detailed descriptions of what these structures are, as we have public Qcow2 format specification. Signed-off-by: Vladimir Sementsov-Ogievskiy --- qapi/block-core.json | 25 + 1

Re: [PATCH] qapi: document leftover members in qapi/run-state.json

Il lun 25 mar 2024, 12:36 Markus Armbruster ha scritto: > Paolo Bonzini writes: > > > Suggested-by: Markus Armbruster > > Signed-off-by: Paolo Bonzini > > --- > > qapi/run-state.json | 26 +- > > 1 file changed, 25 insertions(+), 1 deletion(-) > > > > diff --git a/qapi

[PULL 0/7] target-arm queue

024-03-22 10:59:57 +) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240325 for you to fetch changes up to 55c79639d553c1b7a82b4cde781ad5f316f45b0e: tests/qtest/libqtest.c: Check for g_setenv() failure (2024-03-25

[PULL 5/7] hw/nvram/mac_nvram: Report failure to write data

There's no way for the macio_nvram device to report failure to write data, but we can at least report it to the user with error_report() as we do in other devices like xlnx-efuse. Spotted by Coverity. Resolves: Coverity CID 1507628 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Rev

[PULL 1/7] tests/qtest/npcm7xx_emc_test: Don't leak cmd_line

In test_rx() and test_tx() we allocate a GString *cmd_line but never free it. This is pretty harmless in a test case, but Coverity spotted it. Resolves: Coverity CID 1507122 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth Message-id: 20240312183810.557768-2-

[PULL 3/7] net/af-xdp.c: Don't leak sock_fds array in net_init_af_xdp()

In net_init_af_xdp() we parse the arguments and allocate a buffer of ints into sock_fds. However, although we free this in the error exit path, we don't ever free it in the successful return path. Coverity spots this leak. Switch to g_autofree so we don't need to manually free the array. Resolves

[PULL 7/7] tests/qtest/libqtest.c: Check for g_setenv() failure

Coverity points out that g_setenv() can fail and we don't check for this in qtest_inproc_init(). In practice this will only fail if a memory allocation failed in setenv() or if the caller passed an invalid architecture name (e.g. one with an '=' in it), so rather than requiring the callsite to chec

[PULL 2/7] tests/unit/socket-helpers: Don't close(-1)

In socket_check_afunix_support() we call socket(PF_UNIX, SOCK_STREAM, 0) to see if it works, but we call close() on the result whether it worked or not. Only close the fd if the socket() call succeeded. Spotted by Coverity. Resolves: Coverity CID 1497481 Signed-off-by: Peter Maydell Reviewed-by:

[PULL 4/7] hw/misc/pca9554: Correct error check bounds in get/set pin functions

In pca9554_get_pin() and pca9554_set_pin(), we try to detect an incorrect pin value, but we get the condition wrong, using ">" when ">=" was intended. This has no actual effect, because in pca9554_initfn() we use the correct test when creating the properties and so we'll never be called with an ou

[PULL 6/7] tests/unit/test-throttle: Avoid unintended integer division

In test_compute_wait() we do double units = bkt.max / 10; which does an integer division and then assigns it to a double variable, and similarly later on in the expression for an assertion. Use 10.0 so that we do a floating point division and calculate the exact value, rather than doing an intege

Re: [PULL 20/34] tests/libqos: add riscv/virt machine nodes

On 3/25/24 06:20, Thomas Huth wrote: On 08/03/2024 12.11, Alistair Francis wrote: From: Daniel Henrique Barboza Add a RISC-V 'virt' machine to the graph. This implementation is a modified copy of the existing arm machine in arm-virt-machine.c It contains a virtio-mmio and a generic-pcihost

Re: [PATCH v3 12/17] esp.c: prevent cmdfifo overflow in esp_cdb_ready()

On 25/03/2024 10:26, Philippe Mathieu-Daudé wrote: On 24/3/24 20:17, Mark Cave-Ayland wrote: During normal use the cmdfifo will never wrap internally and cmdfifo_cdb_offset will always indicate the start of the SCSI CDB. However it is possible that a malicious guest could issue an invalid ESP c

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