On Thu, Mar 21, 2024 at 3:29 AM Irina Ryapolova
wrote:
>
> Need to convert mmu_idx to privilege mode for PMP function.
>
> Signed-off-by: Irina Ryapolova
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
On Thu, Mar 14, 2024 at 4:17 PM Yong-Xuan Wang wrote:
>
> The timebase-frequency of guest OS should be the same with host
> machine. The timebase-frequency value in DTS should be got from
> hypervisor when using KVM acceleration.
>
> Reviewed-by: Andrew Jones
> Signed-off-by: Yong-Xuan Wang
Rev
On Thu, Mar 14, 2024 at 4:17 PM Yong-Xuan Wang wrote:
>
> The timebase-frequency of guest OS should be the same with host
> machine. The timebase-frequency value in DTS should be got from
> hypervisor when using KVM acceleration.
>
> Reviewed-by: Andrew Jones
> Signed-off-by: Yong-Xuan Wang
Tha
21.03.2024 21:32, Helge Deller wrote:
On 3/21/24 19:25, Sven Schnelle wrote:
Michael Tokarev writes:
20.03.2024 03:32, Richard Henderson :
Richard Henderson (3):
target/hppa: Fix assemble_16 insns for wide mode
target/hppa: Fix assemble_11a insns for wide mode
target
On Tue, Mar 12, 2024 at 11:55 PM Fei Wu wrote:
>
> The RISC-V Server Platform specification[1] defines a standardized set
> of hardware and software capabilities, that portable system software,
> such as OS and hypervisors can rely on being present in a RISC-V server
> platform.
>
> A correspondin
On 2024/3/22 2:28, Peter Maydell wrote:
> On Thu, 21 Mar 2024 at 15:46, Peter Maydell wrote:
>> Something somewhere needs to implement "if SCTLR_ELx.NMI is 0 then
>> we don't take EXCP_VINMI etc but instead (maybe) EXCP_VIRQ etc".
>> At the moment nothing does that:
>> * arm_cpu_update_vinmi()
On Fri, Mar 22, 2024 at 5:43 AM Si-Wei Liu wrote:
>
>
>
> On 3/20/2024 8:56 PM, Jason Wang wrote:
> > On Thu, Mar 21, 2024 at 5:03 AM Si-Wei Liu wrote:
> >>
> >>
> >> On 3/19/2024 8:27 PM, Jason Wang wrote:
> >>> On Tue, Mar 19, 2024 at 6:16 AM Si-Wei Liu wrote:
>
> On 3/17/2024 8:22 P
On Thu, Mar 21, 2024 at 8:50 PM wrote:
>
> From: Frank Chang
>
> Currently, QEMU only sets the iforce register to 0 and returns early
> when claiming the iforce register. However, this may leave mip.meip
> remains at 1 if a spurious external interrupt triggered by iforce
> register is the only pe
On Fri, Feb 16, 2024 at 6:50 AM Igor Lesik wrote:
>
> Hi,
>
> I have a situation when I need to use third-party 32-bit RISC-V CPU when rest
> is all 64-bit RISC-V CPUs. I have seen that some steps were already made in
> the direction to enable such configuration
> (https://riscv.org/blog/2023/0
Justinien Bouron writes:
> Depending on your use-case, it might be inconvenient to have qemu grab
> the input device from the host immediately upon starting the guest.
>
> Added a new bool option to input-linux: grab-on-startup. If true, the
> device is grabbed as soon as the guest is started, ot
In case of migration, during restore operation, qemu checks config space of the
pci device with the config space in the migration stream captured during save
operation. In case of config space data mismatch, restore operation is failed.
config space check is done in function get_pci_config_device(
On 3/21/24 20:28, Richard Henderson wrote:
Do not clobber the high bits of the address by using a 32-bit deposit.
Signed-off-by: Richard Henderson
Reviewed-by: Helge Deller
Helge
---
target/hppa/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/hppa
201 - 212 of 212 matches
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