Hi Phlippe,
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: Wednesday, March 20, 2024 11:57 PM
> To: Kim, Dongwon ; qemu-devel@nongnu.org
> Cc: marcandre.lur...@redhat.com
> Subject: Re: [PATCH 0/3] ui/console: initialize QemuDmaBuf in ui/console
>
> Hi Dongwon,
>
> On 20/3/
On 21/3/24 08:01, Kim, Dongwon wrote:
Hi Phlippe,
-Original Message-
From: Philippe Mathieu-Daudé
Sent: Wednesday, March 20, 2024 11:57 PM
To: Kim, Dongwon ; qemu-devel@nongnu.org
Cc: marcandre.lur...@redhat.com
Subject: Re: [PATCH 0/3] ui/console: initialize QemuDmaBuf in ui/console
I will re-send shortly. Thanks.
Daniel Henrique Barboza 於 2024年3月20日 週三
上午5:19寫道：
> Hi Jason,
>
> Care to re-send please? The patches don't apply to neither
> riscv-to-apply.next
> nor master.
>
>
> Thanks,
>
> Daniel
>
> On 3/19/24 13:23, Jason Chien wrote:
> > Ping. Can anyone review the patch
On 3/20/24 17:58, Huang Tao wrote:
In RVV and vcrypto instructions, the masked and tail elements are set to 1s
using vext_set_elems_1s function if the vma/vta bit is set. It is the element
agnostic policy.
However, this function can't deal the big endian situation. This patch fixes
the problem b
On 2024/3/21 16:18, Richard Henderson wrote:
On 3/20/24 17:58, Huang Tao wrote:
In RVV and vcrypto instructions, the masked and tail elements are set
to 1s
using vext_set_elems_1s function if the vma/vta bit is set. It is the
element
agnostic policy.
However, this function can't deal the bi
PMC5 does not count instructions when single stepping (with gdb,
haven't tried single stepping inside the target), or when taking
exceptions. At least the single-steppig is a bit of a landmine for
replay.
I don't quite understand the logic of the approach taken for
counting now. AFAIKS instruction
On 2024/3/20 1:28, Peter Maydell wrote:
> On Mon, 18 Mar 2024 at 09:37, Jinjie Ruan wrote:
>>
>> This only implements the external delivery method via the GICv3.
>>
>> Signed-off-by: Jinjie Ruan
>> Reviewed-by: Richard Henderson
>> ---
>> v8:
>> - Fix the rcu stall after sending a VNMI in qem
Since commit v8.1.0-511-g399e5e7125 "target/arm: Implement FEAT_PACQARMA3",
pauth-qarma3 is the default pauth scheme. However this one is very slow.
When people run aarch64 code in qemu tcg, an immediate reaction is like,
"this seems to be a bug somewhere", since the code run insanely slower tha
On 20/3/24 21:50, dongwon@intel.com wrote:
From: Dongwon Kim
QemuDmaBuf struct is defined and primarily used by ui/console/gl so it is
better to handle its creation, initialization and access within ui/console
rather than within hw modules such as hw/display/virtio-gpu and
hw/vfio/display.
On 20/3/24 21:50, dongwon@intel.com wrote:
From: Dongwon Kim
This commit introduces new methods within ui/console to handle the allocation,
initialization, and field retrieval of QemuDmaBuf. By isolating these
operations within ui/console, it enhances safety and encapsulation of
the struct.
On Thu, 21 Mar 2024 at 09:27, Jinjie Ruan wrote:
>
>
>
> On 2024/3/20 1:28, Peter Maydell wrote:
> > On Mon, 18 Mar 2024 at 09:37, Jinjie Ruan wrote:
> >>
> >> This only implements the external delivery method via the GICv3.
> >>
> >> Signed-off-by: Jinjie Ruan
> >> Reviewed-by: Richard Henderso
IODA PCT table (#3) is implemented
without any functionality, being a debug table.
Signed-off-by: Saif Abrar
---
hw/pci-host/pnv_phb4.c | 6 ++
include/hw/pci-host/pnv_phb4.h | 2 ++
include/hw/pci-host/pnv_phb4_regs.h | 1 +
3 files changed, 9 insertions(+)
diff --git a/h
Get the current link-status from PCIE macro.
Extract link-speed and link-width from the link-status
and set in the DLP training control (PCIE_DLP_TCR) register.
Signed-off-by: Saif Abrar
---
hw/pci-host/pnv_phb4.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff
Add a method to be invoked on QEMU reset.
Also add CFG and PBL core-blocks reset logic using
appropriate bits of PHB_PCIE_CRESET register.
Tested by reading the reset value of a register.
Signed-off-by: Saif Abrar
---
hw/pci-host/pnv_phb4.c | 104 +++-
inclu
Hello,
This series updates the existing PHB4 model to the latest spec:
"Power Systems Host Bridge 5 (PHB5) Functional Specification Version 0.5_00".
Updates include the following:
- implemented sticky reset logic
- implemented read-only, write-only, W1C and WxC logic
- return all 1's on read to u
SW cannot write the read-only(RO) bits of a register
and write-only(WO) bits of a register return 0 when read.
Added ro_mask[] for each register that defines which
bits in that register are RO.
When writing to a register, the RO-bits are not updated.
When reading a register, clear the WO bits and
New qtest TB added for PHB4.
TB reads PHB Version register and asserts that
bits[24:31] have value 0xA5.
Signed-off-by: Saif Abrar
---
tests/qtest/meson.build | 1 +
tests/qtest/pnv-phb4-test.c | 74 +
2 files changed, 75 insertions(+)
create mode 100644
Implement write-1-to-clear and write-X-to-clear logic.
Update registers with silent simple read and write.
Return all 1's when an unimplemented/reserved register is read.
Test that reading address 0x0 returns all 1's (i.e. -1).
Signed-off-by: Saif Abrar
---
hw/pci-host/pnv_phb4.c |
PHB updates the register PCIE Link-Control-2.
Set the write-mask bits for TLS, ENTER_COMP, TX_MARGIN,
HASD, MOD_COMP, COMP_SOS and COMP_P_DE.
Signed-off-by: Saif Abrar
---
hw/pci/pcie.c | 6 ++
include/standard-headers/linux/pci_regs.h | 3 +++
2 files changed, 9
Sticky bits retain their values on reset and are not overwritten with the reset
value.
Added sticky reset logic for all required registers,
i.e. CFG core, PBL core, PHB error registers, PCIE stack registers and REGB
error registers.
Tested by writing all 1's to the reg PHB_PBL_ERR_INJECT.
This w
Add a method to reset the value of LSI Source-ID.
Mask off LSI source-id based on number of interrupts in the big/small PHB.
Signed-off-by: Saif Abrar
---
hw/pci-host/pnv_phb4.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pn
From: Dongwon Kim
Signed-off-by: Dongwon Kim
Message-Id: <20240320034229.3347130-1-dongwon@intel.com>
[PMD: Split patch in 3, part 1/3]
Signed-off-by: Philippe Mathieu-Daudé
---
include/ui/console.h| 2 ++
hw/display/virtio-gpu-udmabuf.c | 8 +---
hw/vfio/display.c
Config-read the link-status register in the PCI-E macro,
Depending on the link-active bit, set the link-active status
in the HOTPLUG_STATUS and LINK_MANAGEMENT registers
Also, clear the Presence-status active low bit in HOTPLUG_STATUS reg
after config-reading the slot-status in the PCI-E macro.
Si
From: Dongwon Kim
It is safer to create, initialize, and access all the parameters
in QemuDmaBuf from a central location, ui/console, instead of
hw/virtio-gpu or hw/vfio modules.
Signed-off-by: Dongwon Kim
Message-Id: <20240320034229.3347130-1-dongwon@intel.com>
[PMD: Split patch in 3, part
Respin of Dongwon v2 split as bisectable changes.
Unfortunately last patch breaks vhost_user_gpu_handle_display.
Should dbus_scanout_texture() use dpy_gl_create_dmabuf()?
Dongwon, you can use it as a base for a v4.
Regards,
Phil.
Dongwon Kim (3):
ui/console: Introduce dpy_gl_dmabuf_get_heigh
From: Dongwon Kim
Signed-off-by: Dongwon Kim
Message-Id: <20240320034229.3347130-1-dongwon@intel.com>
[PMD: Split patch in 3, part 2/3]
Signed-off-by: Philippe Mathieu-Daudé
---
include/ui/console.h | 1 +
hw/vfio/display.c| 8 +++-
ui/console.c | 9 +
3 files chang
On Wed, Mar 20, 2024 at 02:12:32PM -0400, Stefan Hajnoczi wrote:
> Daniel P. Berrangé pointed out that the coroutine
> pool size heuristic is very conservative. Instead of halving
> max_map_count, he suggested reserving 5,000 mappings for non-coroutine
> users based on observations of guests he ha
From: Frank Chang
Currently, QEMU only sets the iforce register to 0 and returns early
when claiming the iforce register. However, this may leave mip.meip
remains at 1 if a spurious external interrupt triggered by iforce
register is the only pending interrupt to be claimed, and the interrupt
cann
On Mon, Mar 18, 2024 at 04:12:15PM +0100, Anthony Harivel wrote:
> Introduce a privileged helper to access RAPL MSR.
>
> The privileged helper tool, qemu-vmsr-helper, is designed to provide
> virtual machines with the ability to read specific RAPL (Running Average
> Power Limit) MSRs without requi
On Mon, 18 Mar 2024 at 09:37, Jinjie Ruan wrote:
>
> This only implements the external delivery method via the GICv3.
>
> Signed-off-by: Jinjie Ruan
> Reviewed-by: Richard Henderson
> @@ -692,13 +719,13 @@ static inline bool arm_excp_unmasked(CPUState *cs,
> unsigned int excp_idx,
>
Il mer 20 mar 2024, 23:33 Michael Roth ha scritto:
> On Wed, Mar 20, 2024 at 10:58:30AM +0100, Paolo Bonzini wrote:
> > On 3/20/24 09:39, Michael Roth wrote:
> > > From: Brijesh Singh
> > >
> > > The SNP_LAUNCH_START is called first to create a cryptographic launch
> > > context within the firmw
On Wed, 20 Mar 2024 at 16:15, Alex Bennée wrote:
>
> The following changes since commit c62d54d0a8067ffb3d5b909276f7296d7df33fa7:
>
> Update version for v9.0.0-rc0 release (2024-03-19 19:13:52 +)
>
> are available in the Git repository at:
>
> https://gitlab.com/stsquad/qemu.git
> tags/pu
On 3/6/24 14:08, Jason Chien wrote:
Signed-off-by: Jason Chien
Reviewed-by: Frank Chang
Reviewed-by: Max Chou
---
Please add the following tag in this commit msg:
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
The link is a feature request named "target/riscv: zve32x/zve
On 21/3/24 07:31, Song Gao wrote:
qemu-system-loongarch64 assert failed with the option '-d int',
the helper_idle() raise an exception EXCP_HLT, but the exception name is
undefined.
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 76 +++---
1 file ch
Am 20.03.2024 um 15:09 hat Daniel P. Berrangé geschrieben:
> On Wed, Mar 20, 2024 at 09:35:39AM -0400, Stefan Hajnoczi wrote:
> > On Tue, Mar 19, 2024 at 08:10:49PM +, Daniel P. Berrangé wrote:
> > > On Tue, Mar 19, 2024 at 01:55:10PM -0400, Stefan Hajnoczi wrote:
> > > > On Tue, Mar 19, 2024 a
pet...@redhat.com writes:
> From: Peter Xu
>
> On current code base I can observe extremely high sync count during
> precopy, as long as one enables postcopy-ram=on before switchover to
> postcopy.
>
> To provide some context of when we decide to do a full sync: we check
> must_precopy (which imp
qemu-system-loongarch64 assert failed with the option '-d int',
the helper_idle() raise an exception EXCP_HLT, but the exception name is
undefined.
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 74 +++---
1 file changed, 40 insertions(+), 34 deletions(
A PE that implements FEAT_NMI and FEAT_GICv3 also implements
FEAT_GICv3_NMI. A PE that does not implement FEAT_NMI, does not implement
FEAT_GICv3_NMI
So included support FEAT_GICv3_NMI feature as part of virt platform
GIC initialization if FEAT_NMI and FEAT_GICv3 supported.
Signed-off-by: Jinjie
Wire the new NMI and VINMI interrupt line from the GIC to each CPU.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v9:
- Rename ARM_CPU_VNMI to ARM_CPU_VINMI.
- Update the commit message.
v4:
- Add Reviewed-by.
v3:
- Also add VNMI wire.
---
hw/arm/virt.c | 7 ++-
1 file chang
Enable FEAT_NMI on the 'max' CPU.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v3:
- Add Reviewed-by.
- Sorted to last.
---
docs/system/arm/emulation.rst | 1 +
target/arm/tcg/cpu64.c| 1 +
2 files changed, 2 insertions(+)
diff --git a/docs/system/arm/emulation.rst b/d
FEAT_NMI defines another three new bits in HCRX_EL2: TALLINT, HCRX_VINMI and
HCRX_VFNMI. When the feature is enabled, allow these bits to be written in
HCRX_EL2.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v9:
- Declare cpu variable to reuse latter.
v4:
- Update the comment for
Implement icv_nmiar1_read() for icc_nmiar1_read(), so add definition for
ICH_LR_EL2.NMI and ICH_AP1R_EL2.NMI bit.
If FEAT_GICv3_NMI is supported, ich_ap_write() should consider ICH_AP1R_EL2.NMI
bit. In icv_activate_irq() and icv_eoir_write(), the ICH_AP1R_EL2.NMI bit
should be set or clear accordi
In vCPU Interface, if the vIRQ has the superpriority property, report
vINMI to the corresponding vPE.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v9:
- Update the commit subject and message, vNMI -> vINMI.
v6:
- Add Reviewed-by.
---
hw/intc/arm_gicv3_cpuif.c | 14 -
In CPU Interface, if the IRQ has the superpriority property, report
NMI to the corresponding PE.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v6:
- Add Reviewed-by.
v4:
- Swap the ordering of the IFs.
v3:
- Remove handling nmi_is_irq flag.
---
hw/intc/arm_gicv3_cpuif.c | 4
Added properties to enable FEAT_GICv3_NMI feature, setup distributor
and redistributor registers to indicate NMI support.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v4:
- Add Reviewed-by.
---
hw/intc/arm_gicv3_common.c | 1 +
hw/intc/arm_gicv3_dist.c | 2 ++
Add GICR_INMIR0 register and support access GICR_INMIR0.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v6:
- Add Reviewed-by.
v4:
- Make the GICR_INMIR0 implementation more clearer.
---
hw/intc/arm_gicv3_redist.c | 19 +++
hw/intc/gicv3_internal.h | 1 +
2 fil
Add IS and FS bit in ISR_EL1 and handle the read. With CPU_INTERRUPT_NMI or
CPU_INTERRUPT_VINMI, both CPSR_I and ISR_IS must be set. With
CPU_INTERRUPT_VFNMI, both CPSR_F and ISR_FS must be set.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v9:
- CPU_INTERRUPT_VNMI -> CPU_INTERRU
According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt
with superpriority is always IRQ, never FIQ, so handle NMI same as IRQ in
arm_phys_excp_target_el().
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v4:
- Add Reviewed-by.
v3:
- Remove nmi_is_irq flag in CPUA
When PSTATE.ALLINT is set, an IRQ or FIQ interrupt that is targeted to
ELx, with or without superpriority is masked.
As Richard suggested, place ALLINT bit in PSTATE in env->pstate.
With the change to pstate_read/write, exception entry
and return are automatically handled.
Signed-off-by: Jinjie
This only implements the external delivery method via the GICv3.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v9:
- Update the GPIOs passed in the arm_cpu_kvm_set_irq, and update the comment.
- Definitely not merge VINMI and VFNMI into EXCP_VNMI.
- Update VINMI and VFNMI when wr
A SPI, PPI or SGI interrupt can have a superpriority property. So
maintain superpriority information in PendingIrq and GICR/GICD.
Signed-off-by: Jinjie Ruan
Acked-by: Richard Henderson
---
v3:
- Place this ahead of implement GICR_INMIR.
- Add Acked-by.
---
include/hw/intc/arm_gicv3_common.h | 4
If GICD_CTLR_DS bit is zero and the NMI is non-secure, the NMI prioirty
is higher than 0x80, otherwise it is higher than 0x0. And save NMI
super prioirty information in hppi.superprio to deliver NMI exception.
Since both GICR and GICD can deliver NMI, it is both necessary to check
whether the pendi
According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt
with superpriority is always IRQ, never FIQ, so the NMI exception trap entry
behave like IRQ. And VINMI(vIRQ with Superpriority) can be raised from the
GIC or come from the hcrx_el2.HCRX_VINMI bit, VFNMI(vFIQ with Superpriori
Augment the GICv3's QOM device interface by adding one
new set of sysbus IRQ line, to signal NMI to each CPU.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v4:
- Add Reviewed-by.
v3:
- Add support for VNMI.
---
hw/intc/arm_gicv3_common.c | 6 ++
include/hw/intc/arm_g
Add GICD_INMIR, GICD_INMIRnE register and support access GICD_INMIR0.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v4:
- Make the GICD_INMIR implementation more clearer.
- Udpate the commit message.
v3:
- Add Reviewed-by.
---
hw/intc/arm_gicv3_dist.c | 34 ++
Add ALLINT MSR (immediate) to decodetree, in which the CRm is 0b000x. The
EL0 check is necessary to ALLINT, and the EL1 check is necessary when
imm == 1. So implement it inline for EL2/3, or EL1 with imm==0. Avoid the
unconditional write to pc and use raise_exception_ra to unwind.
Signed-off-by: J
Set or clear PSTATE.ALLINT on taking an exception to ELx according to the
SCTLR_ELx.SPINTMASK bit.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v9:
- Not check SCTLR_NMI in arm_cpu_do_interrupt_aarch64().
v3:
- Add Reviewed-by.
---
target/arm/helper.c | 8
1 file chang
Add support for FEAT_NMI. NMI (FEAT_NMI) is an mandatory feature in
ARMv8.8-A and ARM v9.3-A.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v3:
- Add Reviewed-by.
- Adjust to before the MSR patches.
---
target/arm/internals.h | 3 +++
1 file changed, 3 insertions(+)
diff --git
Add the NMIAR CPU interface registers which deal with acknowledging NMI.
When introduce NMI interrupt, there are some updates to the semantics for the
register ICC_IAR1_EL1 and ICC_HPPIR1_EL1. For ICC_IAR1_EL1 register, it
should return 1022 if the intid has super priority. And for ICC_NMIAR1_EL1
Support ALLINT msr access as follow:
mrs , ALLINT// read allint
msr ALLINT, // write allint with imm
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v9:
- Move nmi_reginfo and related functions inside an existing ifdef
TARGET_AARCH64 to solve the -
On Mon, 18 Mar 2024 at 09:38, Jinjie Ruan wrote:
>
> A SPI, PPI or SGI interrupt can have a superpriority property. So
> maintain superpriority information in PendingIrq and GICR/GICD.
>
> Signed-off-by: Jinjie Ruan
> Acked-by: Richard Henderson
> ---
> v3:
> - Place this ahead of implement GICR
The old_bs variable in bdrv_next() is currently determined by looking
at the old block backend. However, if the block graph changes before
the next bdrv_next() call, it might be that the associated BDS is not
the same that was referenced previously. In that case, the wrong BDS
is unreferenced, lead
From: Stefan Reiter
Some operations, e.g. block-stream, perform reads while discarding the
results (only copy-on-read matters). In this case, they will pass NULL
as the target QEMUIOVector, which will however trip bdrv_pad_request,
since it wants to extend its passed vector. In particular, this i
Changes in v2:
* Ran into another issue while writing the IO test Stefan wanted
to have (good call :)), so include a fix for that and add the
test. I didn't notice during manual testing, because I hadn't
used a scripted QMP 'quit', so there was no race.
Fiona Ebner (2):
blo
Previously, bdrv_pad_request() could not deal with a NULL qiov when
a read needed to be aligned. During prefetch, a stream job will pass a
NULL qiov. Add a test case to cover this scenario.
By accident, also covers a previous race during shutdown, where block
graph changes during iteration in bdrv
On Mon, Mar 18, 2024 at 04:12:16PM +0100, Anthony Harivel wrote:
> Starting with the "Sandy Bridge" generation, Intel CPUs provide a RAPL
> interface (Running Average Power Limit) for advertising the accumulated
> energy consumption of various power domains (e.g. CPU packages, DRAM,
> etc.).
>
> T
On Wed, Mar 20, 2024 at 12:22:34PM +, Daniel P. Berrangé wrote:
> On Wed, Mar 20, 2024 at 03:39:43AM -0500, Michael Roth wrote:
> > TODO: Brijesh as author, me as co-author (vice-versa depending)
> > drop flash handling? we only support BIOS now
>
> A reminder that this commit message ne
On 21/3/24 13:36, Song Gao wrote:
qemu-system-loongarch64 assert failed with the option '-d int',
the helper_idle() raise an exception EXCP_HLT, but the exception name is
undefined.
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 74 +++---
1 file ch
From: Zhao Liu
Add "modules" parameter parsing support in -smp.
Suggested-by: Xiaoyao Li
Tested-by: Yongwei Ma
Signed-off-by: Zhao Liu
Tested-by: Babu Moger
Acked-by: Markus Armbruster
---
Changes since v9:
* Rebased on the SMP changes about unsupported "parameter=1"
configurations. (Ph
From: Zhao Liu
Hi,
This is the our v10 patch series, rebased on the master branch at the
commit 54294b23e16d ("Merge tag 'ui-pull-request' of
https://gitlab.com/marcandre.lureau/qemu into staging").
Compared with v9 [1], v10 mainly contains minor cleanups, without
significant code changes.
Int
From: Zhao Liu
The commit 8f4202fb1080 ("i386: Populate AMD Processor Cache Information
for cpuid 0x801D") adds the cache topology for AMD CPU by encoding
the number of sharing threads directly.
>From AMD's APM, NumSharingCache (CPUID[0x801D].EAX[bits 25:14])
means [1]:
The number of lo
From: Zhao Liu
For i-cache and d-cache, current QEMU hardcodes the maximum IDs for CPUs
sharing cache (CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits
25:14]) to 0, and this means i-cache and d-cache are shared in the SMT
level.
This is correct if there's single thread per core, but is
From: Zhao Liu
CPUID[0xB] defines SMT, Core and Invalid types, and this leaf is shared
by Intel and AMD CPUs.
But for extended topology levels, Intel CPU (in CPUID[0x1F]) and AMD CPU
(in CPUID[0x8026]) have the different definitions with different
enumeration values.
Though CPUID[0x8026
From: Zhao Liu
Module is a level above the core, thereby supporting numa
configuration on the module level can bring user more numa flexibility.
This is the natural further support for module level.
Add module level support in numa configuration.
Tested-by: Yongwei Ma
Signed-off-by: Zhao Liu
From: Zhao Liu
Linux kernel (from v6.4, with commit edc0a2b595765 ("x86/topology: Fix
erroneous smp_num_siblings on Intel Hybrid platforms") is able to
handle platforms with Module level enumerated via CPUID.1F.
Expose the module level in CPUID[0x1F] if the machine has more than 1
modules.
Test
From: Zhuocheng Ding
After i386 supports module level, it's time to add the test for module
level's parsing.
Signed-off-by: Zhuocheng Ding
Co-developed-by: Zhao Liu
Signed-off-by: Zhao Liu
Reviewed-by: Yanan Wang
Tested-by: Babu Moger
Tested-by: Yongwei Ma
Acked-by: Michael S. Tsirkin
---
From: Zhao Liu
Currently, QEMU checks the specify number of topology domains to detect
if there's extended topology levels (e.g., checking nr_dies).
With this bitmap, the extended CPU topology (the levels other than SMT,
core and package) could be easier to detect without touching the
topology d
From: Zhao Liu
In cpu_x86_cpuid(), there are many variables in representing the cpu
topology, e.g., topo_info, cs->nr_cores and cs->nr_threads.
Since the names of cs->nr_cores and cs->nr_threads do not accurately
represent its meaning, the use of cs->nr_cores or cs->nr_threads is
prone to confus
From: Zhao Liu
Introduce module-id to be consistent with the module-id field in
CpuInstanceProperties.
Following the legacy smp check rules, also add the module_id validity
into x86_cpu_pre_plug().
Tested-by: Yongwei Ma
Co-developed-by: Zhuocheng Ding
Signed-off-by: Zhuocheng Ding
Signed-off
From: Zhao Liu
Support module level in i386 cpu topology structure "X86CPUTopoInfo".
Since x86 does not yet support the "modules" parameter in "-smp",
X86CPUTopoInfo.modules_per_die is currently always 1.
Therefore, the module level width in APIC ID, which can be calculated by
"apicid_bitwidth_
From: Zhao Liu
Add module-id in CpuInstanceProperties, to locate the CPU with module
level.
Suggested-by: Xiaoyao Li
Tested-by: Yongwei Ma
Signed-off-by: Zhao Liu
Tested-by: Babu Moger
Acked-by: Markus Armbruster
---
Changes since v7:
* New commit to introduce module_id to locate the CPU w
From: Zhao Liu
In x86, module is the topology level above core, which contains a set
of cores that share certain resources (in current products, the resource
usually includes L2 cache, as well as module scoped features and MSRs).
Though smp.clusters could also share the L2 cache resource [1], th
From: Zhao Liu
CPUID[4].EAX[bits 25:14] is used to represent the cache topology for
Intel CPUs.
After cache models have topology information, we can use
CPUCacheInfo.share_level to decide which topology level to be encoded
into CPUID[4].EAX[bits 25:14].
And since with the helper max_processor_i
From: Zhao Liu
At present, the subleaf 0x02 of CPUID[0x1F] is bound to the "die" level.
In fact, the specific topology level exposed in 0x1F depends on the
platform's support for extension levels (module, tile and die).
To help expose "module" level in 0x1F, decouple CPUID[0x1F] subleaf
with sp
From: Zhao Liu
Intel CPUs implement module level on hybrid client products (e.g.,
ADL-N, MTL, etc) and E-core server products.
A module contains a set of cores that share certain resources (in
current products, the resource usually includes L2 cache, as well as
module scoped features and MSRs).
From: Zhao Liu
Refer to the fixes of cache_info_passthrough ([1], [2]) and SDM, the
CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] should use the
nearest power-of-2 integer.
The nearest power-of-2 integer can be calculated by pow2ceil() or by
using APIC ID offset/width (like L3 topology
From: Zhao Liu
CPUID[0x801D].EAX[bits 25:14] NumSharingCache: number of logical
processors sharing cache.
The number of logical processors sharing this cache is
NumSharingCache + 1.
After cache models have topology information, we can use
CPUCacheInfo.share_level to decide which topology le
From: Zhao Liu
As module-level topology support is added to X86CPU, now we can enable
the support for the modules parameter on PC machines. With this support,
we can define a 5-level x86 CPU topology with "-smp":
-smp cpus=*,maxcpus=*,sockets=*,dies=*,modules=*,cores=*,threads=*.
So, add the 5-
From: Zhao Liu
Currently, by default, the cache topology is encoded as:
1. i/d cache is shared in one core.
2. L2 cache is shared in one core.
3. L3 cache is shared in one die.
This default general setting has caused a misunderstanding, that is, the
cache topology is completely equated with a sp
From: Zhao Liu
Add module_id member in X86CPUTopoIDs.
module_id can be parsed from APIC ID, so also update APIC ID parsing
rule to support module level. With this support, the conversions with
module level between X86CPUTopoIDs, X86CPUTopoInfo and APIC ID are
completed.
module_id can be also ge
On 240320 0024, Vladimir Sementsov-Ogievskiy wrote:
> Hi all!
>
> From fuzzing I've got a fuzz-data, which produces the following crash:
>
> qemu-fuzz-x86_64: ../hw/net/virtio-net.c:134: void
> flush_or_purge_queued_packets(NetClientState *): Assertion
> `!virtio_net_get_subqueue(nc)->async_tx.
On Thu, Mar 21, 2024 at 01:37:36AM +, Liu, Yuan1 wrote:
> > -Original Message-
> > From: Peter Xu
> > Sent: Thursday, March 21, 2024 4:32 AM
> > To: Liu, Yuan1
> > Cc: Daniel P. Berrangé ; faro...@suse.de; qemu-
> > de...@nongnu.org; hao.xi...@bytedance.com; bryan.zh...@bytedance.com;
On Thu, 21 Mar 2024 at 13:10, Jinjie Ruan wrote:
>
> This only implements the external delivery method via the GICv3.
>
> Signed-off-by: Jinjie Ruan
> Reviewed-by: Richard Henderson
> ---
> v9:
> - Update the GPIOs passed in the arm_cpu_kvm_set_irq, and update the comment.
> - Definitely not mer
qatomic_cmpxchg__nocheck(), qatomic_read__nocheck(),
qatomic_set__nocheck() are defined in "qemu/atomic.h".
Include it in order to avoid:
In file included from include/exec/helper-proto.h:10:
In file included from include/exec/helper-proto-common.h:10:
In file included from include/qemu/atom
Hi,
In [*] I posted preliminary steps to unify hmp_info_tlb()
and hmp_info_mem() after making them per-CPU handler,
rather than target-specific method (which break single
binary). Since there is no rush and we need to figure
the usefulness of 'info tlb/mem' and what we want to do
with it, I droppe
Move APIC related code split in cpu-sysemu.c and
monitor.c to cpu-apic.c.
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/cpu-apic.c | 112 +++
target/i386/cpu-sysemu.c | 77 ---
target/i386/monitor.c| 25 -
target
Slightly simplify dump_mmu() by passing the description as
argument to dump_ttr().
Signed-off-by: Philippe Mathieu-Daudé
---
target/m68k/helper.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
index 310e26dfa1..cf9d
MicroBlaze MMU API is exposed in "mmu.h". In order to avoid
name clashing with other targets, prefix the API with 'mb_'.
Signed-off-by: Philippe Mathieu-Daudé
---
target/microblaze/mmu.h | 10 +-
target/microblaze/cpu.c | 2 +-
target/microblaze/helper.c| 4 ++--
target
hmp_info_tlb() is specific to tcg/system, move it to
target/i386/tcg/sysemu/hmp-cmds.c, along with the functions
it depend on (except addr_canonical() which is exposed in
"cpu.h").
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/cpu.h | 7 ++
target/i386/mmu.c | 231 +
MIPS MMU API declared in tcg-internal.h has public linkage.
In order to avoid name clashing with other targets, prefix
the API with 'mips_'.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/tcg-internal.h | 2 +-
target/mips/cpu.c | 2 +-
target/mips/tcg/sysemu/tl
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