On Thu, Feb 29, 2024 at 07:03:35AM +, Paz Offer wrote:
> Hi,
>
> I am trying to build my code with QEMU and getting compilation error
> according to the ISO C90 standard:
>
> const size_t buf_size = 31;
> char buffer[buf_size + 1];
>
> error: ISO C90 forbids array ‘buffer’
AST2700 interrupt controller(INTC) provides hardware interrupt interfaces
to interrupt of processors PSP, SSP and TSP. In INTC, each interrupt of
INT 128 to INT136 combines 32 interrupts.
Introduce a new aspeed_intc class with instance_init and realize handlers.
QEMU supports ARM Generic Interrup
AST2700 SLI engine is designed to accelerate the
throughput between cross-die connections.
It have CPU_SLI at CPU die and IO_SLI at IO die.
Introduce new ast2700_sli and ast2700_sliio class
with instance_init and realize handlers.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/misc/as
Changes from v1:
The patch series supports WDT, SDMC, SMC, SCU, SLI and INTC for AST2700 SoC.
Test steps:
1. Download openbmc image for AST2700 from
https://github.com/AspeedTech-BMC/openbmc/releases/tag/v09.00
https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.00/
ast2700-de
AST2700 have two SCU controllers which are SCU and SCUIO.
Both SCU and SCUIO registers are not compatible previous SOCs
, introduces new registers and adds ast2700 scu, sucio class init handler.
The pclk divider selection of SCUIO is defined in SCUIO280[20:18] and
the pclk divider selection of SCU
AST2700 CPU is ARM Cortex-A35 which is 64 bits.
Add TARGET_AARCH64 to build this machine.
According to the design of ast2700, it has a bootmcu(riscv-32) which
is used for executing SPL.
Then, CPUs(cortex-a35) execute u-boot, kernel and rofs.
Currently, qemu not support emulate two CPU architectur
Hello Jamin,
I tried to send the patch series to support AST2700 but I encountered some
patches
were rejected by server IP 211.20.114.70.
Error Log:
qemu-devel@nongnu.org
eggs.gnu.org
Remote Server returned '550-[SPF] 211.20.114.70 is not allowed to send mail
from aspeedtech.com. 550 Please s
Hi Sahil,
On Sun, Feb 25, 2024 at 10:38 PM Sahil wrote:
>
> Hi,
>
> My name is Sahil and I go by the pseudonym 'valdaarhun' on Github. I have
> never contributed to QEMU before but I have used it a few times as an end
> user. I developed an interest in virtualization during my internship at
> VMw
Hello Steve,
On 2/22/24 18:28, Steve Sistare wrote:
Define entry points to perform per-container cpr-specific initialization
and teardown.
Signed-off-by: Steve Sistare
---
hw/vfio/container.c | 11 ++-
hw/vfio/cpr.c | 19 +++
hw/vfio/iommuf
Xiaoyao Li writes:
> From: Isaku Yamahata
>
> Three sha384 hash values, mrconfigid, mrowner and mrownerconfig, of a TD
> can be provided for TDX attestation. Detailed meaning of them can be
> found:
> https://lore.kernel.org/qemu-devel/31d6dbc1-f453-4cef-ab08-4813f4e0f...@intel.com/
>
> Allow u
Xiaoyao Li writes:
> From: Isaku Yamahata
>
> Add property "quote-generation-socket" to tdx-guest, which is a property
> of type SocketAddress to specify Quote Generation Service(QGS).
>
> On request of GetQuote, it connects to the QGS socket, read request
> data from shared guest memory, send t
Hi,
> UEFI guests seem not to be affected in any way, no matter amount of RAM
> or CPU model (well, of course, since it's a SeaBIOS commit! :-D What I
> mean is that there seems to be nothing in edk2 that induces the same
> behavior).
That used to be a problem with UEFI too.
> A way of working
On 2/22/24 18:28, Steve Sistare wrote:
Allow cpr-reboot for vfio if the guest is in the suspended runstate. The
guest drivers' suspend methods flush outstanding requests and re-initialize
the devices, and thus there is no device state to save and restore. The
user is responsible for suspending
On Wed, Feb 28, 2024 at 01:01:55PM +0100, David Hildenbrand wrote:
On 28.02.24 12:47, Stefano Garzarella wrote:
Add a new `shm` bool option for `-object memory-backend-file`.
When this option is set to true, the POSIX shm_open(3) is used instead
of open(2).
So a file will not be created in the
On Wed, Feb 28, 2024 at 12:08:37PM +, Daniel P. Berrangé wrote:
On Wed, Feb 28, 2024 at 12:47:59PM +0100, Stefano Garzarella wrote:
Add a new `shm` bool option for `-object memory-backend-file`.
When this option is set to true, the POSIX shm_open(3) is used instead
of open(2).
So a file wi
Xiaoyao Li writes:
> Integrate TDX's TDX_REPORT_FATAL_ERROR into QEMU GuestPanic facility
>
> Originated-from: Isaku Yamahata
> Signed-off-by: Xiaoyao Li
> ---
> Changes in v5:
> - mention additional error information in gpa when it presents;
> - refine the documentation; (Markus)
>
> Changes i
Xiaoyao Li writes:
> Introduce tdx-guest object which inherits CONFIDENTIAL_GUEST_SUPPORT,
> and will be used to create TDX VMs (TDs) by
>
> qemu -machine ...,confidential-guest-support=tdx0 \
>-object tdx-guest,id=tdx0
>
> So far, it has no QAPI member/properety decleared and only on
On Wed, Feb 28, 2024 at 01:32:17PM +0100, Markus Armbruster wrote:
Stefano Garzarella writes:
Add a new `shm` bool option for `-object memory-backend-file`.
When this option is set to true, the POSIX shm_open(3) is used instead
of open(2).
So a file will not be created in the filesystem, but
On Sat, Feb 24, 2024 at 10:34:55PM +0800, Hyman Huang wrote:
> This patchset introduce GM/T 0018-2012 as a crypto backend driver,
> which is applied for block encryption. Currently, we support SM4
> cipher algorithm only.
>
> GM/T 0018-2012 is a cryptographic standard issued by the State
> Cryptog
Hi Jamin,
On 29/2/24 08:23, Jamin Lin via wrote:
The SDRAM memory controller(DRAMC) controls the access to external
DDR4 and DDR5 SDRAM and power up to DDR4 and DDR5 PHY.
The DRAM memory controller of AST2700 is not backward compatible
to previous chips such AST2600, AST2500 and AST2400.
Max m
Hi Jamin,
On 29/2/24 08:23, Jamin Lin via wrote:
AST2700 interrupt controller(INTC) provides hardware interrupt interfaces
to interrupt of processors PSP, SSP and TSP. In INTC, each interrupt of
INT 128 to INT136 combines 32 interrupts.
Introduce a new aspeed_intc class with instance_init and r
On Thu, 15 Feb 2024 09:42:13 +0100
Eric Auger wrote:
> Currently the default input range can extend to 64 bits. On x86,
> when the virtio-iommu protects vfio devices, the physical iommu
> may support only 39 bits. Let's set the default to 39, as done
> for the intel-iommu. On ARM we set 48b as a
-return gdb_read_register(current_cpu, buf, GPOINTER_TO_INT(reg));
+return gdb_read_register(current_cpu, buf, GPOINTER_TO_INT(reg) - 1);
}
---
base-commit: bfe8020c814a30479a4241aaa78b63960655962b
change-id: 20240229-null-841efa023c93
Best regards,
--
Akihiko Odaki
On 2/29/24 00:10, Richard Henderson wrote:
On 2/28/24 01:11, Paolo Bonzini wrote:
- /* TSTNE x,sign -> LT x,0 */
- if (arg_is_const_val(*p2, (ctx->type == TCG_TYPE_I32
- ? INT32_MIN : INT64_MIN))) {
+ /* TSTNE x,i -> LT x,0 if i only includes sign bit copie
On Wed, 28 Feb 2024 at 21:12, Sven Schnelle wrote:
>
> HP-UX 10.20 seems to make the lsi53c895a spinning on a memory location
> under certain circumstances. As the SCSI controller and CPU are not
> running at the same time this loop will never finish. After some
> time, the check loop interrupts w
Hi Jamin,
On 29/2/24 08:23, Jamin Lin via wrote:
Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35 CPU).
AST2700 SOC and its interrupt controller are too complex to handle
in the common Aspeed SoC framework. We introduce a new ast2700
class with instance_init and realize
On Wed, 28 Feb 2024 at 19:07, Heinrich Schuchardt
wrote:
>
> On 28.02.24 19:39, Peter Maydell wrote:
> > The limitation to a page dates back to commit 6d16c2f88f2a in 2009,
> > which was the first implementation of this function. I don't think
> > there's a particular reason for that value beyond
On 2/27/24 15:21, Nicholas Piggin wrote:
On Tue Feb 20, 2024 at 6:36 PM AEST, Harsh Prateek Bora wrote:
Introduce the nested PAPR hcall H_GUEST_CREATE_VCPU which is used to
create and initialize the specified VCPU resource for the previously
created guest. Each guest can have multiple VCPUs u
On 29/2/24 08:59, Daniel P. Berrangé wrote:
On Thu, Feb 29, 2024 at 07:03:35AM +, Paz Offer wrote:
Hi,
I am trying to build my code with QEMU and getting compilation error according
to the ISO C90 standard:
const size_t buf_size = 31;
char buffer[buf_size + 1];
error: I
On 2/27/24 15:29, Nicholas Piggin wrote:
On Tue Feb 20, 2024 at 6:36 PM AEST, Harsh Prateek Bora wrote:
Currently, nested_ppc_state stores a certain set of registers and works
with nested_[load|save]_state() for state transfer as reqd for nested-hv API.
Extending these with additional registe
On Thu, 29 Feb 2024 at 03:01, Kunkun Jiang wrote:
>
> Hi Peter,
>
> On 2024/2/27 23:28, Peter Maydell wrote:
> > On Tue, 27 Feb 2024 at 14:42, Kunkun Jiang via
> > wrote:
> >> Hi everybody,
> >>
> >> I want to start qemu-system-aarch64 with a vmlinux,
> >> which is an ELF format file. The arm_lo
On 28/2/24 21:25, Richard Henderson wrote:
This is the only case in which we expect to have no host memory backing
for a guest memory page, because in general linux user processes cannot
map any pages in the top half of the 64-bit address space.
Resolves: https://gitlab.com/qemu-project/qemu/-/i
On Thu, 29 Feb 2024 at 04:52, Joe Komlodi wrote:
> On Wed, Feb 28, 2024 at 6:21 AM Peter Maydell
> wrote:
> > So as far as I can see, this patchset defines a bunch of mechanism,
> > but no actual users: no device looks at these new memattrs, no board
> > code sets the properties. I don't really
Am 28.02.24 um 17:06 schrieb Vladimir Sementsov-Ogievskiy:
> On 28.02.24 19:00, Vladimir Sementsov-Ogievskiy wrote:
>> On 16.02.24 13:55, Fiona Ebner wrote:
>>> Now, the IO test added in patch 4/4 actually contains yet another use
>>> case, namely doing incremental mirrors to stand-alone qcow2 "dif
On Thu, Feb 29, 2024 at 5:04 PM Daniel P. Berrangé
wrote:
> On Sat, Feb 24, 2024 at 10:34:55PM +0800, Hyman Huang wrote:
> > This patchset introduce GM/T 0018-2012 as a crypto backend driver,
> > which is applied for block encryption. Currently, we support SM4
> > cipher algorithm only.
> >
> > G
On Wed, 28 Feb 2024 16:50:30 +
Ankit Agrawal wrote:
> >>> Jonathan, you pointed out interface design issues in your review of v2.>
> >> Are you fully satisfied with the interface in v3?
> >>
> >> Yes. I'm fine with the interface in this version (though it's v7, so I'm
> >> lost
> >> on v2
On 29.02.24 02:11, Peter Xu wrote:
On Wed, Feb 28, 2024 at 08:07:47PM +0100, Heinrich Schuchardt wrote:
On 28.02.24 19:39, Peter Maydell wrote:
On Wed, 28 Feb 2024 at 18:28, Heinrich Schuchardt
wrote:
On 28.02.24 16:06, Philippe Mathieu-Daudé wrote:
Hi Heinrich,
On 28/2/24 13:59, Heinrich
Stefano Garzarella writes:
> On Wed, Feb 28, 2024 at 01:32:17PM +0100, Markus Armbruster wrote:
>>Stefano Garzarella writes:
[...]
>>> +# @shm: if true, shm_open(3) is used to create/open POSIX shared memory
>>> +# object; if false, an open(2) is used. (default: false) (since 9.0)
>>> +#
On 2/27/24 15:32, Nicholas Piggin wrote:
On Tue Feb 20, 2024 at 6:36 PM AEST, Harsh Prateek Bora wrote:
Nested PAPR API provides a standard Guest State Buffer (GSB) format
with unique IDs for each guest state element for which get/set state is
supported by the API. Some of the elements are re
On 12.02.24 09:06, Mattias Nissler wrote:
When DMA memory can't be directly accessed, as is the case when
running the device model in a separate process without shareable DMA
file descriptors, bounce buffering is used.
It is not uncommon for device models to request mapping of several DMA
region
On 29/02/2024 08.20, Vladimir Sementsov-Ogievskiy wrote:
On 29.02.24 09:32, Markus Armbruster wrote:
Cédric Le Goater writes:
The purpose is to record a potential error in the migration stream if
qemu_savevm_state_setup() fails. Most of the current .save_setup()
handlers can be modified to us
On Thu, Feb 29, 2024 at 11:22 AM Heinrich Schuchardt
wrote:
>
> On 29.02.24 02:11, Peter Xu wrote:
> > On Wed, Feb 28, 2024 at 08:07:47PM +0100, Heinrich Schuchardt wrote:
> >> On 28.02.24 19:39, Peter Maydell wrote:
> >>> On Wed, 28 Feb 2024 at 18:28, Heinrich Schuchardt
> >>> wrote:
>
> >>
Am 28.02.24 um 17:24 schrieb Vladimir Sementsov-Ogievskiy:
> On 16.02.24 13:55, Fiona Ebner wrote:
>> Previous discussion from when this was sent upstream [0] (it's been a
>> while). I rebased the patches and re-ordered and squashed like
>> suggested back then [1].
>>
>> This implements two new mir
Commit ffda5db65a ("io/channel-tls: fix handling of bigger read buffers")
changed the behavior of the TLS io channels to schedule a second reading
attempt if there is still incoming data pending. This caused a regression
with backends like the sclpconsole that check in their read function that
the
On Thu, 29 Feb 2024 11:22:24 +0100
Heinrich Schuchardt wrote:
> On 29.02.24 02:11, Peter Xu wrote:
> > On Wed, Feb 28, 2024 at 08:07:47PM +0100, Heinrich Schuchardt wrote:
> >> On 28.02.24 19:39, Peter Maydell wrote:
> >>> On Wed, 28 Feb 2024 at 18:28, Heinrich Schuchardt
> >>> wrote:
> >>
On Thu, 15 Feb 2024 14:28:14 +
Jonathan Cameron via wrote:
Any comments? Almost all the other fixes I need for CXL memory to
work as normal ram are queued up so I'd love it if we can solve this one as
well.
This looks like a big series, but it's really just a refactor + trivial
addition - s
Hi,
I actually failed to carry forward the Reviewed-by tags from Jag,
Phillipe and Stefan as well when reposting even though I didn't make
any non-trivial changes to the respective patches. I intend to post
another version with the respective tags restored, but I'll give you a
day or two to speak
On 2/29/2024 4:37 PM, Markus Armbruster wrote:
Xiaoyao Li writes:
From: Isaku Yamahata
Three sha384 hash values, mrconfigid, mrowner and mrownerconfig, of a TD
can be provided for TDX attestation. Detailed meaning of them can be
found:
https://lore.kernel.org/qemu-devel/31d6dbc1-f453-4cef-a
On Thu, Feb 29, 2024 at 2:43 PM Thomas Huth wrote:
>
> Commit ffda5db65a ("io/channel-tls: fix handling of bigger read buffers")
> changed the behavior of the TLS io channels to schedule a second reading
> attempt if there is still incoming data pending. This caused a regression
> with backends li
> On 27-Feb-2024, at 21:17, Igor Mammedov wrote:
>
> clean up smbios_set_defaults() which is reused by legacy
> and non legacy machines from being aware of 'legacy' notion
> and need to turn it off. And push legacy handling up to
> PC machine code where it's relevant.
>
> Signed-off-by: Igor
On 2/29/2024 4:40 PM, Markus Armbruster wrote:
Xiaoyao Li writes:
From: Isaku Yamahata
Add property "quote-generation-socket" to tdx-guest, which is a property
of type SocketAddress to specify Quote Generation Service(QGS).
On request of GetQuote, it connects to the QGS socket, read request
Reflow paragraph following commit a937b6aa73 ("qapi: Reformat doc
comments to conform to current conventions"): use 4 spaces indentation,
70 columns width, and two spaces to separate sentences.
Suggested-by: Markus Armbruster
Signed-off-by: Stefano Garzarella
---
qapi/qom.json | 27
On Thu, 29 Feb 2024 09:38:29 +
Peter Maydell wrote:
> On Wed, 28 Feb 2024 at 19:07, Heinrich Schuchardt
> wrote:
> >
> > On 28.02.24 19:39, Peter Maydell wrote:
> > > The limitation to a page dates back to commit 6d16c2f88f2a in 2009,
> > > which was the first implementation of this functi
On Thu, 29 Feb 2024 at 02:32, Shaoqin Huang wrote:
>
> Hi Peter,
>
> On 2/22/24 22:28, Peter Maydell wrote:
> > On Wed, 21 Feb 2024 at 06:34, Shaoqin Huang wrote:
> >>
> >> The KVM_ARM_VCPU_PMU_V3_FILTER provides the ability to let the VMM decide
> >> which PMU events are provided to the guest. A
On Thu, Feb 29, 2024 at 11:28:37AM +0100, Markus Armbruster wrote:
Stefano Garzarella writes:
On Wed, Feb 28, 2024 at 01:32:17PM +0100, Markus Armbruster wrote:
Stefano Garzarella writes:
[...]
+# @shm: if true, shm_open(3) is used to create/open POSIX shared memory
+# object; if f
On 26/2/24 21:17, Taylor Simpson wrote:
Signed-off-by: Taylor Simpson
---
target/hexagon/hex_common.py | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 195620c7ec..4bacef223f 100755
--- a/targe
On Thu, 29 Feb 2024 at 10:59, Jonathan Cameron
wrote:
>
> On Thu, 29 Feb 2024 09:38:29 +
> Peter Maydell wrote:
>
> > On Wed, 28 Feb 2024 at 19:07, Heinrich Schuchardt
> > wrote:
> > >
> > > On 28.02.24 19:39, Peter Maydell wrote:
> > > > The limitation to a page dates back to commit 6d16c2f
On 29.02.24 11:58, Stefano Garzarella wrote:
Reflow paragraph following commit a937b6aa73 ("qapi: Reformat doc
comments to conform to current conventions"): use 4 spaces indentation,
70 columns width, and two spaces to separate sentences.
Suggested-by: Markus Armbruster
Signed-off-by: Stefano G
On 29.02.24 12:11, Peter Maydell wrote:
On Thu, 29 Feb 2024 at 10:59, Jonathan Cameron
wrote:
On Thu, 29 Feb 2024 09:38:29 +
Peter Maydell wrote:
On Wed, 28 Feb 2024 at 19:07, Heinrich Schuchardt
wrote:
On 28.02.24 19:39, Peter Maydell wrote:
The limitation to a page dates back to c
On Thu, Feb 29, 2024 at 12:12 PM Peter Maydell wrote:
>
> On Thu, 29 Feb 2024 at 10:59, Jonathan Cameron
> wrote:
> >
> > On Thu, 29 Feb 2024 09:38:29 +
> > Peter Maydell wrote:
> >
> > > On Wed, 28 Feb 2024 at 19:07, Heinrich Schuchardt
> > > wrote:
> > > >
> > > > On 28.02.24 19:39, Peter
The following changes since commit bfe8020c814a30479a4241aaa78b63960655962b:
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
(2024-02-28 14:23:21 +)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-202
From: Xianglai Li
The UEFI loading mode in loongarch is very different
from that in other architectures:loongarch's UEFI code
is in rom, while other architectures' UEFI code is in flash.
loongarch UEFI can be loaded as follows:
-machine virt,pflash=pflash0-format
-bios ./QEMU_EFI.fd
Other archi
> One thing I forgot.
>
> Please add a test. tests/qtest/bios-tables-test.c
IIUC, we need to add a test for aarch64 to test the interface with the
acpi-generic-initiator object.
> + relevant table dumps.
Sorry it isn't clear where do you want me to add this. In the git commit
message?
>> ---
>> hw/acpi/acpi-generic-initiator.c | 84
>> hw/arm/virt-acpi-build.c | 3 +
>> include/hw/acpi/acpi-generic-initiator.h | 26
> A few more comments.
>
> Maybe _ rather than - as more common for acpi include naming.
Ack. will change
On 29.02.24 13:11, Fiona Ebner wrote:
Am 28.02.24 um 17:06 schrieb Vladimir Sementsov-Ogievskiy:
On 28.02.24 19:00, Vladimir Sementsov-Ogievskiy wrote:
On 16.02.24 13:55, Fiona Ebner wrote:
Now, the IO test added in patch 4/4 actually contains yet another use
case, namely doing incremental mir
On 1/18/24 14:37, Denis V. Lunev wrote:
On 12/28/23 11:12, Alexander Ivanov wrote:
If all the bits in a dirty bitmap cluster are ones, the cluster
shouldn't
be written. Instead the corresponding L1 entry should be set to 1.
Check if all bits in a memory region are ones and set 1 to L1 entri
On Wed, 21 Feb 2024, BALATON Zoltan wrote:
Documentation on how to run Linux on the amigaone, pegasos2 and
sam460ex machines is currently buried in the depths of the qemu-devel
mailing list and in the source code. Let's collect the information in
the QEMU handbook for a one stop solution.
Ping?
On 29.02.24 13:41, Fiona Ebner wrote:
Am 28.02.24 um 17:24 schrieb Vladimir Sementsov-Ogievskiy:
On 16.02.24 13:55, Fiona Ebner wrote:
Previous discussion from when this was sent upstream [0] (it's been a
while). I rebased the patches and re-ordered and squashed like
suggested back then [1].
T
On Thu, 29 Feb 2024 11:43:44 +
Ankit Agrawal wrote:
> > One thing I forgot.
> >
> > Please add a test. tests/qtest/bios-tables-test.c
>
> IIUC, we need to add a test for aarch64 to test the interface with the
> acpi-generic-initiator object.
>
> > + relevant table dumps.
>
> Sorry it
On Thu, Feb 29, 2024 at 11:43:37AM +0100, Thomas Huth wrote:
> Commit ffda5db65a ("io/channel-tls: fix handling of bigger read buffers")
> changed the behavior of the TLS io channels to schedule a second reading
> attempt if there is still incoming data pending. This caused a regression
> with back
On Thu, 29 Feb 2024 11:46:27 +
Ankit Agrawal wrote:
> >> ---
> >> hw/acpi/acpi-generic-initiator.c | 84
> >> hw/arm/virt-acpi-build.c | 3 +
> >> include/hw/acpi/acpi-generic-initiator.h | 26
> > A few more comments.
> >
> > Maybe
>> > One thing I forgot.
>> >
>> > Please add a test. tests/qtest/bios-tables-test.c
>>
>> IIUC, we need to add a test for aarch64 to test the interface with the
>> acpi-generic-initiator object.
>>
>> > + relevant table dumps.
>>
>> Sorry it isn't clear where do you want me to add this. In the gi
On Wed, 2024-02-28 at 10:25 -1000, Richard Henderson wrote:
> There are multiple issues with the implementation of shmat().
>
> (1) With reserved_va, which is the default for 32-on-64-bit, we mmap
> the
> entire guest address space. Unlike mmap, shmat refuses to
> replace an
> existing ma
On Thu, 29 Feb 2024 at 11:17, Heinrich Schuchardt
wrote:
> > But yes, I'm not surprised that CXL runs into this. Heinrich,
> > are you doing CXL testing, or is this some other workload?
>
> I am running the UEFI Self-Certification Tests (SCT) on EDK 2 using:
>
> qemu-system-riscv64 \
>-M v
Am 29.02.24 um 12:48 schrieb Vladimir Sementsov-Ogievskiy:
> On 29.02.24 13:11, Fiona Ebner wrote:
>>
>> The iotest creates a new target image for each incremental sync which
>> only records the diff relative to the previous mirror and those diff
>> images are later rebased onto each other to get t
On Thu, Feb 29, 2024 at 1:35 PM Peter Maydell wrote:
>
> On Thu, 29 Feb 2024 at 11:17, Heinrich Schuchardt
> wrote:
> > > But yes, I'm not surprised that CXL runs into this. Heinrich,
> > > are you doing CXL testing, or is this some other workload?
> >
> > I am running the UEFI Self-Certification
>> >>> Jonathan, you pointed out interface design issues in your review of v2.>
>> >> Are you fully satisfied with the interface in v3?
>> >>
>> >> Yes. I'm fine with the interface in this version (though it's v7, so I'm
>> >> lost
>> >> on v2 vs v3!)
>> >
>> > Looks like I can't count to 7!
>> >
When PSTATE.ALLINT is set, an IRQ or FIQ interrupt that is targeted to
ELx, with or without superpriority is masked.
As Richard suggested, place ALLINT bit in PSTATE in env->pstate.
With the change to pstate_read/write, exception entry
and return are automatically handled.
Signed-off-by: Jinjie
Add support for FEAT_NMI. NMI (FEAT_NMI) is an mandatory feature in
ARMv8.8-A and ARM v9.3-A.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v3:
- Add Reviewed-by.
- Adjust to before the MSR patches.
---
target/arm/internals.h | 3 +++
1 file changed, 3 insertions(+)
diff --git
Add GICD_INMIR, GICD_INMIRnE register and support access GICD_INMIR0.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v4:
- Make the GICD_INMIR implementation more clearer.
- Udpate the commit message.
v3:
- Add Reviewed-by.
---
hw/intc/arm_gicv3_dist.c | 34 ++
Augment the GICv3's QOM device interface by adding one
new set of sysbus IRQ line, to signal NMI to each CPU.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v4:
- Add Reviewed-by.
v3:
- Add support for VNMI.
---
hw/intc/arm_gicv3_common.c | 6 ++
include/hw/intc/arm_g
According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt
with superpriority is always IRQ, never FIQ, so handle NMI same as IRQ in
arm_phys_excp_target_el().
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v4:
- Add Reviewed-by.
v3:
- Remove nmi_is_irq flag in CPUA
If GICD_CTLR_DS bit is zero and the NMI is non-secure, the NMI prioirty
is higher than 0x80, otherwise it is higher than 0x0. And save NMI
super prioirty information in hppi.superprio to deliver NMI exception.
Since both GICR and GICD can deliver NMI, it is both necessary to check
whether the pendi
FEAT_NMI defines another three new bits in HCRX_EL2: TALLINT, HCRX_VINMI and
HCRX_VFNMI. When the feature is enabled, allow these bits to be written in
HCRX_EL2.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v4:
- Update the comment for FEAT_NMI in hcrx_write().
- Update the comm
Set or clear PSTATE.ALLINT on taking an exception to ELx according to the
SCTLR_ELx.SPINTMASK bit.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v3:
- Add Reviewed-by.
---
target/arm/helper.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/arm/helper.c b/targ
Added properties to enable FEAT_GICv3_NMI feature, setup distributor
and redistributor registers to indicate NMI support.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v4:
- Add Reviewed-by.
---
hw/intc/arm_gicv3_common.c | 1 +
hw/intc/arm_gicv3_dist.c | 2 ++
Add ALLINT MSR (immediate) to decodetree, in which the CRm is 0b000x. The
EL0 check is necessary to ALLINT, and the EL1 check is necessary when
imm == 1. So implement it inline for EL2/3, or EL1 with imm==0. Avoid the
unconditional write to pc and use raise_exception_ra to unwind.
Signed-off-by: J
Wire the new NMI and VNMI interrupt line from the GIC to each CPU.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v4:
- Add Reviewed-by.
v3:
- Also add VNMI wire.
---
hw/arm/virt.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt.c b/hw/arm/vi
Add GICR_INMIR0 register and support access GICR_INMIR0.
Signed-off-by: Jinjie Ruan
---
v4:
- Make the GICR_INMIR0 implementation more clearer.
---
hw/intc/arm_gicv3_redist.c | 19 +++
hw/intc/gicv3_internal.h | 1 +
2 files changed, 20 insertions(+)
diff --git a/hw/intc/arm_
Add the NMIAR CPU interface registers which deal with acknowledging NMI.
When introduce NMI interrupt, there are some updates to the semantics for the
register ICC_IAR1_EL1 and ICC_HPPIR1_EL1. For ICC_IAR1_EL1 register, it
should return 1022 if the intid has super priority. And for ICC_NMIAR1_EL1
Enable FEAT_NMI on the 'max' CPU.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v3:
- Add Reviewed-by.
- Sorted to last.
---
docs/system/arm/emulation.rst | 1 +
target/arm/tcg/cpu64.c| 1 +
2 files changed, 2 insertions(+)
diff --git a/docs/system/arm/emulation.rst b/d
Support ALLINT msr access as follow:
mrs , ALLINT// read allint
msr ALLINT, // write allint with imm
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v5:
- Add Reviewed-by.
v4:
- Remove arm_is_el2_enabled() check in allint_check().
- Change to env->ps
In CPU Interface, if the IRQ has the superpriority property, report
NMI to the corresponding PE.
Signed-off-by: Jinjie Ruan
---
v4:
- Swap the ordering of the IFs.
v3:
- Remove handling nmi_is_irq flag.
---
hw/intc/arm_gicv3_cpuif.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/intc
According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt
with superpriority is always IRQ, never FIQ, so the NMI exception trap entry
behave like IRQ. However, VNMI can be IRQ or FIQ, FIQ can only come from
hcrx_el2.HCRX_VFNMI bit, IRQ can be raised from the GIC or come from the
hc
A SPI, PPI or SGI interrupt can have a superpriority property. So
maintain superpriority information in PendingIrq and GICR/GICD.
Signed-off-by: Jinjie Ruan
Acked-by: Richard Henderson
---
v3:
- Place this ahead of implement GICR_INMIR.
- Add Acked-by.
---
include/hw/intc/arm_gicv3_common.h | 4
Add IS and FS bit in ISR_EL1 and handle the read. With CPU_INTERRUPT_NMI or
CPU_INTERRUPT_VNMI, both CPSR_I and ISR_IS must be set. With
CPU_INTERRUPT_VFIQ and HCRX_EL2.VFNMI set, both CPSR_F and ISR_FS must be set.
Signed-off-by: Jinjie Ruan
---
v4；
- Also handle VNMI.
v3:
- CPU_INTERRUPT_NMI do
This only implements the external delivery method via the GICv3.
Signed-off-by: Jinjie Ruan
---
v4:
- Accept NMI unconditionally for arm_cpu_has_work() but add comment.
- Change from & to && for EXCP_IRQ or EXCP_FIQ.
- Refator nmi mask in arm_excp_unmasked().
- Also handle VNMI in arm_cpu_exec_in
A PE that implements FEAT_NMI and FEAT_GICv3 also implements
FEAT_GICv3_NMI. A PE that does not implement FEAT_NMI, does not implement
FEAT_GICv3_NMI
So included support FEAT_GICv3_NMI feature as part of virt platform
GIC initialization if FEAT_NMI and FEAT_GICv3 supported.
Signed-off-by: Jinjie
In vCPU Interface, if the vIRQ has the superpriority property, report
vNMI to the corresponding vPE.
Signed-off-by: Jinjie Ruan
---
hw/intc/arm_gicv3_cpuif.c | 14 --
hw/intc/gicv3_internal.h | 1 +
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/hw/intc/arm_gicv3_c
Am 27.02.24 um 16:47 schrieb Igor Mammedov:
> Windows (10) bootloader when running on top of SeaBIOS, fails to find
>
> SMBIOSv3 entry point. Tracing it shows that it looks for v2 anchor markers
>
> only and not v3. Tricking it into believing that entry point is found
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