Changes from v1: The patch series supports WDT, SDMC, SMC, SCU, SLI and INTC for AST2700 SoC.
Test steps: 1. Download openbmc image for AST2700 from https://github.com/AspeedTech-BMC/openbmc/releases/tag/v09.00 https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.00/ ast2700-default-obmc.tar.gz 2. untar ast2700-default-obmc.tar.gz ``` tar -xf ast2700-default-obmc.tar.gz ``` 3. Run and the contents of scripts as following IMGDIR=ast2700-default UBOOT_SIZE=$(stat --format=%s -L ${IMGDIR}/u-boot-nodtb.bin) UBOOT_DTB_ADDR=$((0x400000000 + ${UBOOT_SIZE})) qemu-system-aarch64 -M ast2700-evb -nographic -m 8G\ -device loader,addr=0x400000000,file=${IMGDIR}/u-boot-nodtb.bin,force-raw=on\ -device loader,addr=${UBOOT_DTB_ADDR},file=${IMGDIR}/u-boot.dtb,force-raw=on\ -device loader,addr=0x430000000,file=${IMGDIR}/bl31.bin,force-raw=on\ -device loader,addr=0x430080000,file=${IMGDIR}/optee/tee-raw.bin,force-raw=on\ -device loader,addr=0x430000000,cpu-num=0\ -device loader,addr=0x430000000,cpu-num=1\ -device loader,addr=0x430000000,cpu-num=2\ -device loader,addr=0x430000000,cpu-num=3\ -smp 4\ -drive file=${IMGDIR}/image-bmc,format=raw,if=mtd\ -serial mon:stdio\ -snapshot Known Issue: 1. QEMU supports ARM Generic Interrupt Controller, version 3(GICv3) but not support Shared Peripheral Interrupt (SPI), yet. Added work around in INTC patch to set GICINT132[18] which was BMC UART interrupt if it received GICINT132, so users are able to type any key from keyboard to trigger GICINT132 interrupt until AST2700 boot into login prompt. It is a temporary solution. If users encounter boot stck and no booting log, please type any key from keyboard. 2. It is required to add "-m 8G" to set the dram size 8G. AST2700 dram size calculation is not compatible AST2600. According to the DDR hardware capacity behavior, if users write the data at address which is over than the supported size, it would set the data at address 0. For example: a. sdram base address "0x4 00000000" b. sdram size is 1GiB The available address range is from "0x4 00000000" to "0x4 40000000". If users write 0xdeadbeef at address "0x6 00000000", the value of DRAM address 0 (base address 0x4 00000000) should be 0xdeadbeef. Please see ast2700_sdrammc_calc_size in https://github.com/AspeedTech-BMC/u-boot/blob/v00.05.00/drivers/ram/aspeed/ sdram_ast2700.c It seems we should create a new function instead of aspeed_soc_dram_init to support AST2700. https://github.com/qemu/qemu/blob/master/hw/arm/aspeed_soc_common.c Jamin Lin (8): aspeed/wdt: Add AST2700 support aspeed/sli: Add AST2700 support aspeed/sdmc: Add AST2700 support aspeed/smc: Add AST2700 support aspeed/scu: Add AST2700 support aspeed/intc: Add AST2700 support aspeed/soc: Add AST2700 support aspeed: Add an AST2700 eval board hw/arm/aspeed.c | 32 +++ hw/arm/aspeed_ast27x0.c | 462 +++++++++++++++++++++++++++++++ hw/arm/meson.build | 1 + hw/intc/aspeed_intc.c | 135 +++++++++ hw/intc/meson.build | 1 + hw/misc/aspeed_scu.c | 306 +++++++++++++++++++- hw/misc/aspeed_sdmc.c | 215 ++++++++++++-- hw/misc/aspeed_sli.c | 179 ++++++++++++ hw/misc/meson.build | 3 +- hw/misc/trace-events | 11 + hw/ssi/aspeed_smc.c | 326 ++++++++++++++++++++-- hw/ssi/trace-events | 2 +- hw/watchdog/wdt_aspeed.c | 24 ++ include/hw/arm/aspeed_soc.h | 26 +- include/hw/intc/aspeed_vic.h | 29 ++ include/hw/misc/aspeed_scu.h | 47 +++- include/hw/misc/aspeed_sdmc.h | 4 +- include/hw/misc/aspeed_sli.h | 32 +++ include/hw/ssi/aspeed_smc.h | 1 + include/hw/watchdog/wdt_aspeed.h | 3 +- 20 files changed, 1787 insertions(+), 52 deletions(-) create mode 100644 hw/arm/aspeed_ast27x0.c create mode 100644 hw/intc/aspeed_intc.c create mode 100644 hw/misc/aspeed_sli.c create mode 100644 include/hw/misc/aspeed_sli.h -- 2.25.1
