On Wed, 21 Feb 2024 at 06:56, Ho, Tong wrote:
>
> On Thu, Feb 8, 2024 at 3:36 AM, Peter Maydell
> wrote:
>
> > This implementation will send the transmitted characters
> > to the QEMU chardev and also loop them back into the UART
> > when loopback is enabled. Similarly if we receive a character
On 8/2/24 23:03, Bernhard Beschow wrote:
Rather than distributing PC system flash handling across three files, let's
confine it to one. Now, pc_system_firmware_init() creates, configures and cleans
up the system flash which makes the code easier to understand. It also avoids
the extra call to pc_
On Wed, 21 Feb 2024 at 15:34, Philippe Mathieu-Daudé wrote:
>
> On 20/2/24 17:06, Peter Maydell wrote:
> > Implement a ResetContainer. This is a subclass of Object, and it
> > implements the Resettable interface. The container holds a list of
> > arbitrary other objects which implement Resettabl
On 8/2/24 23:03, Bernhard Beschow wrote:
pc_system_flash_create() checked for pcmc->pci_enabled which is redundant since
its caller already checked it. The method can be turned into just two lines, so
inline and remove it.
Signed-off-by: Bernhard Beschow
---
hw/i386/pc_sysfw.c | 15 ++
On Fri, Feb 16, 2024 at 2:42 PM Hao Xiang wrote:
> This change adds a dedicated handler for
> MigrationOps::ram_save_target_page in
> multifd live migration. Now zero page checking can be done in the multifd
> threads
> and this becomes the default configuration. We still provide backward
> compa
To be able to compile QEMU with -Wvla (to prevent potential security
issues), we need to get rid of the variable length array in the
kvmppc_save_htab() function. Replace it with a heap allocation instead.
Signed-off-by: Thomas Huth
---
target/ppc/kvm.c | 2 +-
1 file changed, 1 insertion(+), 1 d
It would be good to enable -Wvla as an additional security feature
when compiling QEMU (see also Peter's explanation here:
https://lore.kernel.org/qemu-devel/20240125173211.1786196-1-peter.mayd...@linaro.org/
).
There are currently only two spots with variable lengths arrays left,
so if we fix tho
From: Peter Maydell
QEMU has historically used variable length arrays only very rarely.
Variable length arrays are a potential security issue where an
on-stack dynamic allocation isn't correctly size-checked, especially
when the size comes from the guest. (An example problem of this kind
from th
HPTES_PER_GROUP is 8 and HASH_PTE_SIZE_64 is 16, so we don't waste
too many bytes by always allocating the maximum amount of bytes on
the stack here to get rid of the variable length array.
Suggested-by: Peter Maydell
Signed-off-by: Thomas Huth
---
target/ppc/kvm.c | 4 ++--
1 file changed, 2 i
The processor tracing features in cpu_x86_cpuid() are hardcoded to a set
that should be safe on all processor that support PT virtualization.
But as an additional check, x86_cpu_filter_features() also checks
that the accelerator supports that safe subset, and if not it marks
CPUID_7_0_EBX_INTEL_PT
On Wed, 21 Feb 2024 at 16:26, Thomas Huth wrote:
>
> To be able to compile QEMU with -Wvla (to prevent potential security
> issues), we need to get rid of the variable length array in the
> kvmppc_save_htab() function. Replace it with a heap allocation instead.
>
> Signed-off-by: Thomas Huth
> --
On Wed, 21 Feb 2024 at 16:26, Thomas Huth wrote:
>
> HPTES_PER_GROUP is 8 and HASH_PTE_SIZE_64 is 16, so we don't waste
> too many bytes by always allocating the maximum amount of bytes on
> the stack here to get rid of the variable length array.
>
> Suggested-by: Peter Maydell
> Signed-off-by: T
20.02.2024 21:48, Daniel P. Berrangé:
This ends up looking a bit muddled together. I don't think we
need repeat 'qemu-img ' twice, and could add a little
more whitespace
eg instead of:
$ ./build/qemu-img check --help
qemu-img check: Check basic image integrity. Usage:
qemu-img check [-f FMT |
On Wed, Feb 21, 2024 at 07:31:42PM +0300, Michael Tokarev wrote:
> 20.02.2024 21:48, Daniel P. Berrangé:
>
> > This ends up looking a bit muddled together. I don't think we
> > need repeat 'qemu-img ' twice, and could add a little
> > more whitespace
> >
> > eg instead of:
> >
> > $ ./build/qemu
On 21/02/2024 17.29, Peter Maydell wrote:
On Wed, 21 Feb 2024 at 16:26, Thomas Huth wrote:
To be able to compile QEMU with -Wvla (to prevent potential security
issues), we need to get rid of the variable length array in the
kvmppc_save_htab() function. Replace it with a heap allocation instead
On 21/02/2024 17.26, Thomas Huth wrote:
From: Peter Maydell
QEMU has historically used variable length arrays only very rarely.
Variable length arrays are a potential security issue where an
on-stack dynamic allocation isn't correctly size-checked, especially
when the size comes from the guest.
From: Felix Wu
Signed-off-by: Felix Wu
Signed-off-by: Nabih Estefan
---
hw/smbios/smbios.c | 49 +---
include/hw/firmware/smbios.h | 4 +++
qemu-options.hx | 2 +-
3 files changed, 51 insertions(+), 4 deletions(-)
diff --git a/hw/smbios
On 2/21/2024 10:54 AM, Fabiano Rosas wrote:
> Fabiano Rosas writes:
>
>> Steve Sistare writes:
>>
>>> Simplify the exec migration code by using list utility functions.
>>>
>>> As a side effect, this also fixes a minor memory leak. On function return,
>>> "g_auto(GStrv) argv" frees argv and each
From: Felix Wu
Version 2.1+.
Signed-off-by: Felix Wu
Signed-off-by: Nabih Estefan
---
hw/smbios/smbios.c | 99
include/hw/firmware/smbios.h | 13 +
qemu-options.hx | 3 ++
3 files changed, 115 insertions(+)
diff --git a/hw/smbi
This patch series implements SMBIOS type 9 descriptor, system slots.
For each system slot, we can assign one descriptor for it if needed.
In versions later than 2.6, a new PCI device field was added to make sure the
descriptor is associated with a certain device, if provided.
For ease of usage, qem
On 2/21/2024 8:29 AM, Markus Armbruster wrote:
> I apologize for the lateness of my review.
No problem. Thanks for the review.
> Steve Sistare writes:
>
>> Generalize hmp_split_at_comma() to take any delimiter string, rename
>> as strList_from_string(), and move it to util/strList.c.
>>
>> No
On 2/21/2024 8:19 AM, Markus Armbruster wrote:
> Steve Sistare writes:
>
>> Signed-off-by: Steve Sistare
>> Reviewed-by: Marc-André Lureau
>> ---
>> tests/unit/meson.build| 1 +
>> tests/unit/test-strList.c | 80
>> +++
>> 2 files changed, 81 i
On 2/21/2024 8:14 AM, Markus Armbruster wrote:
> Steve Sistare writes:
>
>> Signed-off-by: Steve Sistare
>> Reviewed-by: Marc-André Lureau
>> ---
>> include/qemu/strList.h | 6 ++
>> util/strList.c | 14 ++
>> 2 files changed, 20 insertions(+)
>>
>> diff --git a/includ
On 2/21/2024 8:29 AM, Markus Armbruster wrote:
> Steve Sistare writes:
>
>> Signed-off-by: Steve Sistare
>> Reviewed-by: Marc-André Lureau
>> ---
>> include/qapi/util.h | 13 +
>> 1 file changed, 13 insertions(+)
>>
>> diff --git a/include/qapi/util.h b/include/qapi/util.h
>> index
On Wed, Feb 21, 2024 at 6:58 AM Daniel Henrique Barboza <
dbarb...@ventanamicro.com> wrote:
> Hi Atish,
>
> This series and its dependency, which I assume it's
>
> "[PATCH v4 0/5] Add ISA extension smcntrpmf support"
>
> Doesn't apply in neither master nor riscv-to-apply.next because of this
> pat
On 21/2/24 17:09, Peter Maydell wrote:
On Wed, 21 Feb 2024 at 15:34, Philippe Mathieu-Daudé wrote:
On 20/2/24 17:06, Peter Maydell wrote:
Implement a ResetContainer. This is a subclass of Object, and it
implements the Resettable interface. The container holds a list of
arbitrary other objec
On 2/19/24 00:25, Alvin Chang wrote:
According to RISC-V Debug specification, there are several common
matching conditions before firing a trigger, including the enabled
privilege levels of the trigger.
This commit adds trigger_common_match() to prepare the common matching
conditions for the
From: Roque Arcudia Hernandez
Current implementation checks the StreamIDs against STRTAB_BASE_CFG.LOG2SIZE
register field value and a constant SMMU_IDR1_SIDSIZE which is also used as
initial value for field SMMU_IDR1.SIDSIZE.
This limits the possibility of extending the SMMUv3 by inheritance and
From: Roque Arcudia Hernandez
According to the SMMU specification the StreamID construction and size is
IMPLEMENTATION DEFINED, the size being between 0 and 32 bits.
This patch creates virtual functions get_sid and get_iommu_mr to allow different
implementations of how the StreamID is constructe
This patch series modifies the ARM SMMUv3 to be able to work with an
implementation specific StreamID that does not match exactly the PCIe BDF.
The way to achieve this is by converting the smmu_get_sid and smmu_iommu_mr
functions to virtual functions that can be overridden by inheritance, making
su
On 2/19/24 00:25, Alvin Chang wrote:
We have implemented trigger_common_match(), which checks if the enabled
privilege levels of the trigger match CPU's current privilege level.
Remove the related code in riscv_cpu_debug_check_breakpoint() and invoke
trigger_common_match() to check the privile
On 21/2/24 17:59, Thomas Huth wrote:
On 21/02/2024 17.26, Thomas Huth wrote:
From: Peter Maydell
QEMU has historically used variable length arrays only very rarely.
Variable length arrays are a potential security issue where an
on-stack dynamic allocation isn't correctly size-checked, especial
On 21/2/24 18:27, Philippe Mathieu-Daudé wrote:
Clément, ResetData::entry isn't used, so we can simplify removing
the whole ResetData structure, but I'm not sure this is intended:
-- >8 --
diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c
index 4873b59b6c..1ff6b5d63d 100644
--- a/hw/sparc/leon3.
On 2/19/24 00:25, Alvin Chang wrote:
We have implemented trigger_common_match(), which checks if the enabled
privilege levels of the trigger match CPU's current privilege level.
Remove the related code in riscv_cpu_debug_check_watchpoint() and invoke
trigger_common_match() to check the privile
This patch series modifies the ARM GICv3 ITS to use the already existing
send_msi virtual function when writing the GITS_TRANSLATER in order to be able
to modify the final DeviceID to an implementation specific version that requires
extra information besides the BDF that comes in the requester_id.
From: Roque Arcudia Hernandez
According to the “GICv3 and GICv4 Software Overview” the DeviceID is
IMPLEMENTATION DEFINED. This patch increases the DeviceID in send_msi virtual
function to 32 bits to allow the possibility of a redefinition of it with a
bigger DeviceID.
Signed-off-by: Roque Arcud
From: Roque Arcudia Hernandez
This is trying to achieve 2 things: To be able to redefine the send_msi in a
derived class of arm_gicv3_its and/or to expose a method call interface to
inject interrupts from another device.
Signed-off-by: Roque Arcudia Hernandez
Signed-off-by: Nabih Estefan
---
On 21/2/24 10:47, Bernhard Beschow wrote:
Great! I'll rebase my PC initialization series on top of Peter's reset cleanup
series which probably results in folding cmos initialization into pc.c.
Don't, already done.
On 18/2/24 14:17, Bernhard Beschow wrote:
This function is used once in the pc machines. Remove it since it contains one
line only.
Now reminds me of
https://lore.kernel.org/qemu-devel/20211218130437.1516929-6-f4...@amsat.org/
Signed-off-by: Bernhard Beschow
---
include/hw/input/i8042.h
From: Roque Arcudia Hernandez
This patch adds a way to specify an NGUID for a given NVMe Namespace using a
string of hexadecimal digits with an optional '-' separator to group bytes. For
instance:
-device nvme-ns,nguid="e9accd3b83904e13167cf0593437f57d"
If provided, the NGUID will be part of th
Tianlan Zhou writes:
> Key for input grab should be Ctrl-Alt-g, not just Ctrl-Alt.
>
> Signed-off-by: Tianlan Zhou
> ---
>
> v1:
> - Initial patch
>
> ---
> docs/system/keys.rst.inc | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/docs/system/keys.rst.inc b/docs/system/k
On 21/02/2024 17.59, Thomas Huth wrote:
On 21/02/2024 17.26, Thomas Huth wrote:
From: Peter Maydell
QEMU has historically used variable length arrays only very rarely.
Variable length arrays are a potential security issue where an
on-stack dynamic allocation isn't correctly size-checked, espec
Richard Henderson writes:
> On 2/16/24 01:35, Alex Bennée wrote:
>> Richard Henderson writes:
>>
>>> Use TARGET_PAGE_SIZE and MAP_FIXED_NOREPLACE.
>>>
>>> We really should be attending to this earlier during
>>> probe_guest_base, as well as better detection and
>>> emulation of various Linux pe
Android Virtualization Framework (AVF) supports "KVM(pKVM)" also
Qualcomm's "Gunyah" and MediaTek's "GenieZone" as the hypervisor. Please
Add these hypervisors to QEMU.
Dear QEMU and KVM community,
Unfortunately QEMU was not accepted into Google Summer of Code this
year and we will not be able to run the projects we had proposed.
This will come as a disappointment to both applicants and mentors, but
please read on. For applicants we encourage you to look at the o
On 2/19/24 00:25, Alvin Chang wrote:
We have implemented trigger_common_match(), which checks if the enabled
privilege levels of the trigger match CPU's current privilege level. We
can invoke trigger_common_match() to check the privilege levels of the
type 3 triggers.
Signed-off-by: Alvin Cha
leon3.c currently fails to compile with some compilers when the -Wvla
option has been enabled:
../hw/sparc/leon3.c: In function ‘leon3_cpu_reset’:
../hw/sparc/leon3.c:153:5: error: ISO C90 forbids variable length array
‘offset_must_be_zero’ [-Werror=vla]
153 | ResetData *s = (ResetData
> This is also useful information. I would suggest you look
> at what the difference is between the image that boots and
> the one that doesn't: is it the same format (and what format
> is that)? is the way it is loaded on the real hardware the
> same, or different?
I am not able to distinguish b
From: Fan Ni
Add dynamic capacity extent list representative to the definition of
CXLType3Dev and add get DC extent list mailbox command per
CXL.spec.3.1:.8.2.9.9.9.2.
Signed-off-by: Fan Ni
---
hw/cxl/cxl-mailbox-utils.c | 71 +
hw/mem/cxl_type3.c
From: Fan Ni
With the change, when setting up memory for type3 memory device, we can
create DC regions.
A property 'num-dc-regions' is added to ct3_props to allow users to pass the
number of DC regions to create. To make it easier, other region parameters
like region base, length, and block size
From: Fan Ni
Per CXL spec 3.1, two mailbox commands are implemented:
Add Dynamic Capacity Response (Opcode 4802h) 8.2.9.9.9.3, and
Release Dynamic Capacity (Opcode 4803h) 8.2.9.9.9.4.
Signed-off-by: Fan Ni
---
hw/cxl/cxl-mailbox-utils.c | 288
include/hw/c
From: Fan Ni
The function ct3_build_cdat_entries_for_mr only uses size of the passed
memory region argument, refactor the function definition to make the passed
arguments more specific.
Signed-off-by: Fan Ni
---
hw/mem/cxl_type3.c | 15 +--
1 file changed, 9 insertions(+), 6 deleti
From: Fan Ni
Add (file/memory backed) host backend, all the dynamic capacity regions
will share a single, large enough host backend. Set up address space for
DC regions to support read/write operations to dynamic capacity for DCD.
With the change, following supports are added:
1. Add a new prope
From: Fan Ni
Since fabric manager emulation is not supported yet, the change implements
the functions to add/release dynamic capacity extents as QMP interfaces.
Note: we skips any FM issued extent release request if the exact extent
does not exist in the extent list of the device. We will loose
From: Fan Ni
Not all dpa range in the DC regions is valid to access until an extent
covering the range has been added. Add a bitmap for each region to
record whether a DC block in the region has been backed by DC extent.
For the bitmap, a bit in the bitmap represents a DC block. When a DC
extent
From: Fan Ni
Rename mem_size as static_mem_size for type3 memdev to cover static RAM and
pmem capacity, preparing for the introduction of dynamic capacity to support
dynamic capacity devices.
Signed-off-by: Fan Ni
---
hw/cxl/cxl-mailbox-utils.c | 4 ++--
hw/mem/cxl_type3.c | 8 --
From: Fan Ni
v3[1]->v4:
The code is rebased on mainstream QEMU with the following patch series:
hw/cxl/mailbox: change CCI cmd set structure to be a member, not a reference
hw/cxl/mailbox: interface to add CCI commands to an existing CCI
Main changes include:
1. Updated the specification ref
From: Fan Ni
Per cxl spec r3.1, add dynamic capacity region representative based on
Table 8-165 and extend the cxl type3 device definition to include dc region
information. Also, based on info in 8.2.9.9.9.1, add 'Get Dynamic Capacity
Configuration' mailbox support.
Note: decode_len of a dc regi
From: Fan Ni
Based on CXL spec r3.1 Table 8-127 (Identify Memory Device Output
Payload), dynamic capacity event log size should be part of
output of the Identify command.
Add dc_event_log_size to the output payload for the host to get the info.
Signed-off-by: Fan Ni
---
hw/cxl/cxl-mailbox-util
On 2/21/24 14:06, Atish Kumar Patra wrote:
On Wed, Feb 21, 2024 at 6:58 AM Daniel Henrique Barboza mailto:dbarb...@ventanamicro.com>> wrote:
Hi Atish,
This series and its dependency, which I assume it's
"[PATCH v4 0/5] Add ISA extension smcntrpmf support"
Doesn't apply in
On 2/21/24 03:08, Jinjie Ruan via wrote:
FEAT_NMI defines another new bit in HCRX_EL2: TALLINT. When the
feature is enabled, allow this bit to be written in HCRX_EL2.
Signed-off-by: Jinjie Ruan
---
target/arm/cpu-features.h | 5 +
target/arm/helper.c | 5 +
2 files changed, 10
On 20/2/24 22:11, Joe Komlodi wrote:
The current logging doesn't tell us which specific smbus device is an
error state.
Signed-off-by: Joe Komlodi
Reviewed-by: Peter Maydell
---
hw/i2c/smbus_slave.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/i2c/smbus_sla
Hi Alex, any comments or RB on this or patch 11? The last few changes I am
making for Peter will not change this patch.
- Steve
On 2/8/2024 1:54 PM, Steve Sistare wrote:
> Allow cpr-reboot for vfio if the guest is in the suspended runstate. The
> guest drivers' suspend methods flush outstandin
On 20/2/24 09:55, Thomas Huth wrote:
These definitions are required outside of the hw/ide/ code, too,
so lets's move them from internal.h to a new header called ide-dma.h.
Signed-off-by: Thomas Huth
---
include/hw/ide/ide-dma.h | 37 +
include/hw/ide/inte
On 20/2/24 09:55, Thomas Huth wrote:
Unentangle internal.h by moving public IDE device related
Disentangle ... from? Untangle? TIL Unentangle.
Anyway I'm not a native English speaker, so:
Reviewed-by: Philippe Mathieu-Daudé
definitions to ide-dev.h.
Signed-off-by: Thomas Huth
---
includ
On 20/2/24 09:55, Thomas Huth wrote:
Let's consolidate the public IDE bus related functions in a separate
header.
Signed-off-by: Thomas Huth
---
include/hw/ide/ide-bus.h | 42 +++
include/hw/ide/internal.h | 40 +
2 fi
On 21/2/24 19:07, Thomas Huth wrote:
leon3.c currently fails to compile with some compilers when the -Wvla
option has been enabled:
../hw/sparc/leon3.c: In function ‘leon3_cpu_reset’:
../hw/sparc/leon3.c:153:5: error: ISO C90 forbids variable length array
‘offset_must_be_zero’ [-Werror=vl
On 21/2/24 19:47, Philippe Mathieu-Daudé wrote:
On 21/2/24 19:07, Thomas Huth wrote:
leon3.c currently fails to compile with some compilers when the -Wvla
option has been enabled:
../hw/sparc/leon3.c: In function ‘leon3_cpu_reset’:
../hw/sparc/leon3.c:153:5: error: ISO C90 forbids variable
On 2/21/24 03:08, Jinjie Ruan via wrote:
The ALLINT bit in PSTATE is used to mask all IRQ or FIQ interrupts.
Place this in its own field within ENV, as that will
make it easier to reset from within TCG generated code.
With the change to pstate_read/write, exception entry
and return are automati
From: Fan Ni
The whole mailbox output payload space is already zeroed after copying
out the input payload, which happens before processing the specific mailbox
command:
https://elixir.bootlin.com/qemu/latest/source/hw/cxl/cxl-device-utils.c#L204
Signed-off-by: Fan Ni
---
hw/cxl/cxl-mailbox-uti
On 2/21/24 03:08, Jinjie Ruan via wrote:
Add ALLINT MSR (immediate) to decodetree. And the EL0 check is necessary
to ALLINT. Avoid the unconditional write to pc and use raise_exception_ra
to unwind.
Signed-off-by: Jinjie Ruan
---
target/arm/tcg/a64.decode | 1 +
target/arm/tcg/helper-a
On 21/02/2024 19.43, Philippe Mathieu-Daudé wrote:
On 20/2/24 09:55, Thomas Huth wrote:
Unentangle internal.h by moving public IDE device related
Disentangle ... from? Untangle? TIL Unentangle.
You're right, "disentangle" seems to be the more appropriate word.
I'll fix it up.
Anyway I'm no
On 2/21/24 09:09, Richard Henderson wrote:
+static bool trans_MSR_i_ALLINT(DisasContext *s, arg_i *a)
+{
+ if (!dc_isar_feature(aa64_nmi, s) || s->current_el == 0) {
+ return false;
+ }
+ gen_helper_msr_i_allint(tcg_env, tcg_constant_i32(a->imm));
You're passing all of #imm4, no
On 2/21/24 03:08, Jinjie Ruan via wrote:
Support ALLINT msr access as follow:
mrs , ALLINT // read allint
msr ALLINT, // write allint with imm
Signed-off-by: Jinjie Ruan
---
target/arm/helper.c | 32
1 file changed, 32 insertions(+)
diff -
Input grab key should be Ctrl-Alt-g, not just Ctrl-Alt.
Signed-off-by: Tianlan Zhou
---
system/vl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/system/vl.c b/system/vl.c
index a82555ae15..b8469d9965 100644
--- a/system/vl.c
+++ b/system/vl.c
@@ -891,7 +891,7 @@ static voi
Input grab key should be Ctrl-Alt-g, not just Ctrl-Alt.
v2:
- Update help message in system/vl.c
v1:
- Initial patch
Tianlan Zhou (2):
docs/system: Update description for input grab key
system/vl: Update description for input grab key
docs/system/keys.rst.inc | 2 +-
system/vl.c
Input grab key should be Ctrl-Alt-g, not just Ctrl-Alt.
Signed-off-by: Tianlan Zhou
---
docs/system/keys.rst.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/system/keys.rst.inc b/docs/system/keys.rst.inc
index 2e2c97aa23..59966a3fe7 100644
--- a/docs/system/keys.rst.
On 2/21/24 03:08, Jinjie Ruan via wrote:
This only implements the external delivery method via the GICv3.
Signed-off-by: Jinjie Ruan
---
target/arm/cpu-qom.h | 3 ++-
target/arm/cpu.c | 39 ++-
target/arm/cpu.h | 2 ++
target/arm/helper.c | 1
On 2/21/24 03:08, Jinjie Ruan via wrote:
The NMI exception state include whether the interrupt with super priority
is IRQ or FIQ, so add a nmi_is_irq flag in CPUARMState to distinguish it.
Signed-off-by: Jinjie Ruan
---
target/arm/cpu.h| 2 ++
target/arm/helper.c | 9 +
2 files
On 2/21/24 03:08, Jinjie Ruan via wrote:
Add support for FEAT_NMI. NMI (FEAT_NMI) is an mandatory feature in
ARMv8.8-A and ARM v9.3-A.
Signed-off-by: Jinjie Ruan
---
target/arm/internals.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/arm/internals.h b/target/arm/internals.h
On 2/21/24 10:26, Daniel Henrique Barboza wrote:
On 2/21/24 14:06, Atish Kumar Patra wrote:
On Wed, Feb 21, 2024 at 6:58 AM Daniel Henrique Barboza
mailto:dbarb...@ventanamicro.com>> wrote:
Hi Atish,
This series and its dependency, which I assume it's
"[PATCH v4 0/5] Add I
On 2/21/24 03:08, Jinjie Ruan via wrote:
Set or clear PSTATE.ALLINT on taking an exception to ELx according to the
SCTLR_ELx.SPINTMASK bit.
Signed-off-by: Jinjie Ruan
---
target/arm/helper.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.
On 2/21/24 09:09, Richard Henderson wrote:
On 2/21/24 03:08, Jinjie Ruan via wrote:
Add ALLINT MSR (immediate) to decodetree. And the EL0 check is necessary
to ALLINT. Avoid the unconditional write to pc and use raise_exception_ra
to unwind.
Signed-off-by: Jinjie Ruan
---
target/arm/tcg/a64.
On 2/21/24 03:08, Jinjie Ruan via wrote:
Set pstate.ALLINT in arm_cpu_reset_hold as daif do it.
Signed-off-by: Jinjie Ruan
---
target/arm/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 055670343e..e850763158 100644
--- a/target/arm/cpu
On 2/21/24 03:08, Jinjie Ruan via wrote:
+gicr_write_bitmap_reg(cs, attrs, &cs->gicr_isuperprio, value);
Where is gicr_isuperprio defined?
Ah, incorrect patch splitting and ordering -- introduced in patch 19.
r~
On 21/2/24 20:13, Thomas Huth wrote:
On 21/02/2024 19.43, Philippe Mathieu-Daudé wrote:
On 20/2/24 09:55, Thomas Huth wrote:
Unentangle internal.h by moving public IDE device related
Disentangle ... from? Untangle? TIL Unentangle.
You're right, "disentangle" seems to be the more appropriate
Hao Xiang writes:
> Now that zero page checking is done on the multifd sender threads by
> default, we still provide an option for backward compatibility. This
> change adds a qtest migration test case to set the zero-page-detection
> option to "legacy" and run multifd migration with zero page ch
We used to set the default granule to 4KB but with VFIO assignment
it makes more sense to use the actual host page size.
Indeed when hotplugging a VFIO device protected by a virtio-iommu
on a 64kB/64kB host/guest config, we current get a qemu crash:
"vfio: DMA mapping failed, unable to continue"
This allows to choose which granule will be used by
default by the virtio-iommu. Current default is 4K.
Signed-off-by: Eric Auger
---
hw/virtio/virtio-iommu.c | 24 +---
qemu-options.hx | 3 +++
2 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/hw/virt
Hi,
On 21/2/24 19:53, nifan@gmail.com wrote:
From: Fan Ni
The whole mailbox output payload space is already zeroed after copying
out the input payload, which happens before processing the specific mailbox
command:
https://elixir.bootlin.com/qemu/latest/source/hw/cxl/cxl-device-utils.c#L204
Introduce a new enum type property allowing to set an
IOMMU granule. Values are 4K, 16K, 64K and host. This
latter indicates the vIOMMU granule will matches the
host page size.
A subsequent patch will add such a property to the
virtio-iommu device.
Signed-off-by: Eric Auger
---
include/hw/qdev-
We used to set the default granule to 4KB but with VFIO assignment
it makes more sense to use the actual host page size.
Indeed when hotplugging a VFIO device protected by a virtio-iommu
on a 64kB/64kB host/guest config, we current get a qemu crash:
"vfio: DMA mapping failed, unable to continue"
Hao Xiang writes:
> 1. Implements the zero page detection and handling on the multifd
> threads for non-compression, zlib and zstd compression backends.
> 2. Added a new value 'multifd' in ZeroPageDetection enumeration.
> 3. Add proper asserts to ensure pages->normal are used for normal pages
> i
Hao Xiang writes:
> This change adds a dedicated handler for MigrationOps::ram_save_target_page in
nit: Add a dedicated handler...
Usually "this patch/change" is used only when necessary to avoid
ambiguity.
> multifd live migration. Now zero page checking can be done in the multifd
> threads
On 2/21/24 17:17, Atish Patra wrote:
On 2/21/24 10:26, Daniel Henrique Barboza wrote:
On 2/21/24 14:06, Atish Kumar Patra wrote:
On Wed, Feb 21, 2024 at 6:58 AM Daniel Henrique Barboza mailto:dbarb...@ventanamicro.com>> wrote:
Hi Atish,
This series and its dependency, which I
Thomas Huth writes:
> When using "--without-default-devices", the ARM_GICV3_TCG and ARM_GIC_KVM
> settings currently get disabled, though the arm virt machine is only of
> very limited use in that case. This also causes the migration-test to
> fail in such builds. Let's make sure that we always k
On 15/2/24 11:50, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (4):
hw/ppc/ppc4xx_pci: Remove unused "hw/ppc/ppc.h" header
hw/ppc/ppc4xx_pci: Extract PCI host definitions to
hw/pci-host/ppc4xx.h
hw/ppc/ppc4xx_pci: Move ppc4xx_pci.c to hw/pci-host/
hw/ppc/ppc440_pcix: Mov
Add missing long options and --help output.
While at it, remove unused option_index variable.
Signed-off-by: Michael Tokarev
---
qemu-img.c | 34 --
1 file changed, 24 insertions(+), 10 deletions(-)
diff --git a/qemu-img.c b/qemu-img.c
index cc51da31cf..3f719bbe
From: Philippe Mathieu-Daudé
Since the named GPIO lines are a "public" interface to the device,
we can directly call qdev_connect_gpio_out_named(), making it
consistent with how the other A20 input source (port92) is wired.
Suggested-by: Peter Maydell
Signed-off-by: Philippe Mathieu-Daudé
Revi
'qemu-img resize --help' does not work, since it wants more
arguments. Also it -size is only recognized as a very last
argument, but it is common for tools to handle other options
after positional arguments too.
Tell getopt_long() to return non-options together with options,
and process filename
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