v1:
1. support uart controller both 0 and 1 base
2. fix hardcode boot address 0
v2:
1. introduce a new UART0 device name
2. remove ASPEED_SOC_SPI_BOOT_ADDR marco
v3:
1. add uart helper functions to get the index, start and last.
2. add more description in commit log
Jamin Lin (2):
aspeed: intr
In the previous design of ASPEED SOCs QEMU model, it set the boot
address at "0" which was the hardcode setting for ast10x0, ast2600,
ast2500 and ast2400.
According to the design of ast2700, it has a bootmcu(riscv-32) which
is used for executing SPL and initialize DRAM and copy u-boot image
from S
The SAARP field added in commit 5fb2dcd179 ("target/mips: Provide
R/W access to SAARI and SAAR CP0 registers") has never been used,
remove it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/internal.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/mips/internal.h b/target/mips/
On 2/14/24 22:06, Philippe Mathieu-Daudé wrote:
The SAARP field added in commit 5fb2dcd179 ("target/mips: Provide
R/W access to SAARI and SAAR CP0 registers") has never been used,
remove it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/internal.h | 1 -
1 file changed, 1 deletion(-)
Because the three alternatives are monotonic, we don't
need to keep a couple of bitmasks, just identify the
strongest alternative at startup.
Signed-off-by: Richard Henderson
---
util/bufferiszero.c | 56 ++---
1 file changed, 22 insertions(+), 34 deletion
Because non-embedded aarch64 is expected to have AdvSIMD enabled, merely
double-check with the compiler flags for __ARM_NEON and don't bother with
a runtime check. Otherwise, model the loop after the x86 SSE2 function,
and use VADDV to reduce the four vector comparisons.
Signed-off-by: Richard He
Signed-off-by: Richard Henderson
---
RFC because I've not benchmarked this on real hw, only run it
through qemu for validation.
---
host/include/aarch64/host/cpuinfo.h | 1 +
util/bufferiszero.c | 49 +
util/cpuinfo-aarch64.c | 1 +
mes
From: Alexander Monakov
Thanks to early checks in the inline buffer_is_zero wrapper, the SIMD
routines are invoked much more rarely in normal use when most buffers
are non-zero. This makes use of AVX512 unprofitable, as it incurs extra
frequency and voltage transition periods during which the CPU
Signed-off-by: Richard Henderson
---
util/bufferiszero.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/util/bufferiszero.c b/util/bufferiszero.c
index ce04642c67..ce80713071 100644
--- a/util/bufferiszero.c
+++ b/util/bufferiszero.c
@@ -26,7 +26,8 @@
#include "qemu
From: Alexander Monakov
The SSE4.1 variant is virtually identical to the SSE2 variant, except
for using 'PTEST+JNZ' in place of 'PCMPEQB+PMOVMSKB+CMP+JNE' for testing
if an SSE register is all zeroes. The PTEST instruction decodes to two
uops, so it can be handled only by the complex decoder, and
From: Alexander Monakov
Test for length >= 256 inline, where is is often a constant.
Before calling into the accelerated routine, sample three bytes
from the buffer, which handles most non-zero buffers.
Signed-off-by: Alexander Monakov
Signed-off-by: Mikhail Romanov
Message-Id: <20240206204809
v3: https://patchew.org/QEMU/20240206204809.9859-1-amona...@ispras.ru/
Changes for v4:
- Keep separate >= 256 entry point, but only keep constant length
check inline. This allows the indirect function call to be hidden
and optimized away when the pointer is constant.
- Split out a >=
Split less-than and greater-than 256 cases.
Use unaligned accesses for head and tail.
Avoid using out-of-bounds pointers in loop boundary conditions.
Signed-off-by: Richard Henderson
---
util/bufferiszero.c | 86 +++--
1 file changed, 52 insertions(+), 34
From: Alexander Monakov
Use of prefetching in bufferiszero.c is quite questionable:
- prefetches are issued just a few CPU cycles before the corresponding
line would be hit by demand loads;
- they are done for simple access patterns, i.e. where hardware
prefetchers can perform better;
- th
From: Alexander Monakov
Increase unroll factor in SIMD loops from 4x to 8x in order to move
their bottlenecks from ALU port contention to load issue rate (two loads
per cycle on popular x86 implementations).
Avoid using out-of-bounds pointers in loop boundary conditions.
Follow SSE2 implementat
Sometimes, when migration fails, it is hard to find out
the cause of the problems: you have to grep qemu logs.
At the same time, there is MIGRATION event, which looks like
suitable place to hold such error descriptions.
To handle situation like this (maybe one day it will be useful
for other MIGRA
This commit adds the optional field reason for the events, which
contains the string, describing reason of status changing.
For example: reason of migration fail.
Function migrate_set_state now accepts 4th argument: the reason to
pass to event. Every call of this function appended with NULL argume
This patch adds error description as reason for event MIGRATION in every
place that generates MIGRATION_STATE_FAILED
Signed-off-by: Roman Khapov
---
migration/migration.c | 62 ++-
migration/multifd.c | 8 +++---
migration/savevm.c| 12 -
3
On 15/2/24 09:14, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
util/bufferiszero.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 15/2/24 09:14, Richard Henderson wrote:
Because the three alternatives are monotonic, we don't
need to keep a couple of bitmasks, just identify the
strongest alternative at startup.
Signed-off-by: Richard Henderson
---
util/bufferiszero.c | 56 ++---
We are missing an entry for the virtio-iommu-pci device. Add the
information on which machine it is currently supported and document
the new aw-bits option.
Signed-off-by: Eric Auger
---
v4 -> v5
- tweek the aw-bits option description according to Cédric's
suggestion
---
qemu-options.hx | 8
This patch adds error description as reason for event MIGRATION in every
place that generates MIGRATION_STATE_FAILED
Signed-off-by: Roman Khapov
---
migration/migration.c | 62 ++-
migration/multifd.c | 8 +++---
migration/savevm.c| 12 -
3
Currently the default input range can extend to 64 bits. On x86,
when the virtio-iommu protects vfio devices, the physical iommu
may support only 39 bits. Let's set the default to 39, as done
for the intel-iommu. On ARM we set 48b as a default (matching
SMMUv3 SMMU_IDR5.VAX == 0).
We use hw_compat
In [1] and [2] we attempted to fix a case where a VFIO-PCI device
protected with a virtio-iommu is assigned to an x86 guest. On x86
the physical IOMMU may have an address width (gaw) of 39 or 48 bits
whereas the virtio-iommu exposes a 64b input address space by default.
Hence the guest may try to u
aw-bits is a new option that allows to set the bit width of
the input address range. This value will be used as a default for
the device config input_range.end. By default it is set to 64 bits
which is the current value.
Signed-off-by: Eric Auger
Reviewed-by: Zhenzhong Duan
Reviewed-by: Cédric L
Use %u format to trace domain_range limits.
Signed-off-by: Eric Auger
Reviewed-by: Zhenzhong Duan
Reviewed-by: Cédric Le Goater
---
hw/virtio/trace-events | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events
index 77905d1994..23508
On Thu, Feb 15, 2024, at 09:31, Andreas Kemnade wrote:
> On Wed, 14 Feb 2024 23:42:58 +0100
> "Arnd Bergmann" wrote:
>> On Wed, Feb 14, 2024, at 13:26, Dmitry Baryshkov wrote:
>> > On Tue, 13 Feb 2024 at 23:22, Linus Walleij
>> > wrote:
>> >> On Tue, Feb 13, 2024 at 9:12 PM Arnd Bergmann wrot
From: Philippe Mathieu-Daudé
Add the 'any'-architecture target.
- Only consider 64-bit targets
- Do not use any hardware accelerator (except qtest)
- For architecture constants, use:
. max of supported targets phys/virt address space
. max of supported targets MMU modes
. min of supported
Since v2:
- Run check-qtest instead of check-unit in CI (Alex)
Almost 2 years later we got hundreds of cleanups patches
merged, so we can get this patch in. Building the 'any'
target has to be explictly requested in ./configure
target-list argument.
This binary will be use to rework QEMU startup
On Wed, 14 Feb 2024, Richard Henderson wrote:
> Because non-embedded aarch64 is expected to have AdvSIMD enabled, merely
> double-check with the compiler flags for __ARM_NEON and don't bother with
> a runtime check. Otherwise, model the loop after the x86 SSE2 function,
> and use VADDV to reduc
On Thu, 15 Feb 2024 at 10:45, Arnd Bergmann wrote:
>
> On Thu, Feb 15, 2024, at 09:31, Andreas Kemnade wrote:
> > On Wed, 14 Feb 2024 23:42:58 +0100
> > "Arnd Bergmann" wrote:
> >> On Wed, Feb 14, 2024, at 13:26, Dmitry Baryshkov wrote:
> >> > On Tue, 13 Feb 2024 at 23:22, Linus Walleij
> >> >
On Wed, 14 Feb 2024, Richard Henderson wrote:
> v3: https://patchew.org/QEMU/20240206204809.9859-1-amona...@ispras.ru/
>
> Changes for v4:
> - Keep separate >= 256 entry point, but only keep constant length
> check inline. This allows the indirect function call to be hidden
> and opt
On 30/1/24 12:11, Philippe Mathieu-Daudé wrote:
Missed during commit d537cf6c86 ("Unify IRQ handling")
when qemu_irq typedef was introduced for IRQState.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Patch queued.
Hi Clément,
On 31/1/24 09:50, Clément Chigot wrote:
This series allows leon3 emulations to record up 4 CPUs.
Clément Chigot (9):
sparc/grlib: split out the headers for each peripherals
intc/grlib_irqmp: add ncpus property
intc/grlib_irqmp: implements the multiprocessor status regist
Hi Shaoqin,
On 2/1/24 09:51, Shaoqin Huang wrote:
> The KVM_ARM_VCPU_PMU_V3_FILTER provides the ability to let the VMM decide
> which PMU events are provided to the guest. Add a new option
> `kvm-pmu-filter` as -cpu sub-option to set the PMU Event Filtering.
> Without the filter, all PMU events ar
Arguments `ram_block` are reassigned to local declarations `block`
without further use. Remove re-assignment to reduce noise.
Signed-off-by: Manos Pitsidianakis
---
system/physmem.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/system/physmem.c b/system/physmem.c
ind
Hi Philippe
On Thu, Feb 15, 2024 at 10:02 AM Philippe Mathieu-Daudé
wrote:
>
> Hi Clément,
>
> On 31/1/24 09:50, Clément Chigot wrote:
>
> > This series allows leon3 emulations to record up 4 CPUs.
>
> > Clément Chigot (9):
> >sparc/grlib: split out the headers for each peripherals
> >int
14.02.2024 14:13, Michael S. Tsirkin:
virtio,pc,pci: features, cleanups, fixes
vhost-user-snd support
x2APIC mode with TCG support
CXL update to r3.1
fixes, cleanups all over the place.
Signed-off-by: Michael S. Tsirkin
Akihik
13.02.2024 10:16, Philippe Mathieu-Daudé:
Prefer the QDev API over the low level QOM one.
No logical change intended.
Reviewed-by: Michael Tokarev
Picked up for trivial-patches.
/mjt
13.02.2024 10:16, Philippe Mathieu-Daudé :
Prefer the QDev API over the low level QOM one.
No logical change intended.
...
/* set the numa node property for sgx epc object */
-object_property_set_uint(obj, SGX_EPC_NUMA_NODE_PROP,
list->value->node,
-
On 2/15/24 09:42, Eric Auger wrote:
> We are missing an entry for the virtio-iommu-pci device. Add the
> information on which machine it is currently supported and document
> the new aw-bits option.
>
> Signed-off-by: Eric Auger
argh forgot to add Cédric R-b collected on v4
Reviewed-by: Cédric
On 15.02.24 10:15, Manos Pitsidianakis wrote:
Arguments `ram_block` are reassigned to local declarations `block`
without further use. Remove re-assignment to reduce noise.
Signed-off-by: Manos Pitsidianakis
---
system/physmem.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
di
On Mon, Feb 5, 2024 at 1:57 PM Alex Bennée wrote:
> Albert Esteve writes:
>
> > Shared objects lack spoofing protection.
> > For VHOST_USER_BACKEND_SHARED_OBJECT_REMOVE messages
> > received by the vhost-user interface, any backend was
> > allowed to remove entries from the shared table just
> >
15.02.2024 12:15, Manos Pitsidianakis :
Arguments `ram_block` are reassigned to local declarations `block`
without further use. Remove re-assignment to reduce noise.
Reviewed-by: Michael Tokarev
And applied to trivial-patches, thanks!
/mjt
On Tue, Feb 13, 2024 at 3:13 AM Irina Ryapolova
wrote:
>
> CSR hvictl (Hypervisor Virtual Interrupt Control) provides further flexibility
> for injecting interrupts into VS level in situations not fully supported by
> the
> facilities described thus far, but only with more active involvement of t
On Tue, Feb 6, 2024 at 12:11 AM Alex Bennée wrote:
> Albert Esteve writes:
>
> > Ensure that we cleanup all virtio shared
> > resources when the vhost devices is cleaned
> > up (after a hot unplug, or a crash).
> >
> > To do so, we add a new function to the virtio_dmabuf
> > API called `virtio_d
On Tue, Feb 13, 2024 at 3:13 AM Irina Ryapolova
wrote:
>
> From: Vadim Shakirov
>
> In the AIA specification in the paragraph "Virtual interrupts for VS level"
> it is indicated for interrupts 13-63: if the bit in hideleg is enabled,
> then the corresponding vsip and vsie bits are aliases to sip
target/i386: As specified by Intel Manual Vol2 3-180, cmp instructions
are not allowed to have lock prefix and a `UD` should be raised. Without
this patch, s1->T0 will be uninitialized and used in the case OP_CMPL.
Signed-off-by: Ziqiao Kong
---
target/i386/tcg/translate.c | 11 ++-
1 fi
(Resending again because I found I accidentally unsubscribed the list. And
sorry for disturbance for Richard.)
Hello QEMU Developers! I'm from the downstream project Unicorn
Engine (https://github.com/unicorn-engine/unicorn). I identified a simple
bug that triggers a tcg assertion in QEMU. Althoug
On Sat, Feb 3, 2024 at 1:23 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> In this new version we changed patch 3 as suggested by Alistair in v1
> [1]. Instead of creating individual always-true bool for each named
> feature, create a bool flag will be always 'true' to be used as config
> offset fo
On Wed, Feb 14, 2024 at 5:25 PM Andrew Jones wrote:
>
> On Wed, Feb 14, 2024 at 02:38:34PM +0100, Christoph Müllner wrote:
> > On Wed, Feb 14, 2024 at 2:35 PM Daniel Henrique Barboza
> > wrote:
> > >
> > >
> > >
> > > On 2/7/24 09:22, Christoph Müllner wrote:
> > > > The first patch of this serie
On Wed, Feb 7, 2024 at 6:18 PM Jason Chien wrote:
>
> The original implementation sets $pc to the address read from the jump
> vector table first and links $ra with the address of the next instruction
> after the updated $pc. After jumping to the updated $pc and executing the
> next ret instructio
On Tue, Jan 16, 2024 at 11:11 AM Sia Jee Heng
wrote:
>
> This series focuses on enabling the Serial Port Console Redirection (SPCR)
> table for the RISC-V virt platform. Considering that ARM utilizes the same
> function, the initial patch involves migrating the build_spcr function to
> common code
On Wed, Feb 7, 2024 at 10:00 PM Christoph Müllner
wrote:
>
> This series syncs the hwprobe keys with those available in the upstream
> kernel repository with the exception of Ztso, which is not supported in
> QEMU as of now.
>
> The first patch is a resend (sent on Nov 27), as it should have been
On Wed, Feb 7, 2024 at 1:42 AM Alexandre Ghiti wrote:
>
> Currently, the initrd is placed at 128MB, which overlaps with the kernel
> when it is large (for example syzbot kernels are). From the kernel side,
> there is no reason we could not push the initrd further away in memory
> to accommodate la
W dniu 15.02.2024 o 9:52 AM, Dmitry Baryshkov pisze:
If we want to actually go there, I think the best option for PCMCIA
support is likely to replace the entire "soc_common" pcmcia driver
with a simple drivers/pata/ storage driver and no support for
other cards.
hmm, main usage for PCMCIA/CF i
Am 17.01.24 um 08:23 schrieb M_O_Bz:
> Basic Info:
> 1. Issue: I got a " double free or corruption (out)", head for
> attachment debug.log for details, the debug.log print the backtrace of
> one virtual machine
> 2. Reproduce: currently I cann't destribe how to reproduce this bug,
> because it's in
Some memory regions are not being skipped in vhost_vdpa_listener_region_del,
but they are skipped in vhost_vdpa_listener_region_add, or vice versa. The
vhost-vdpa code expects all parts to maintain their properties, so we're adding
a trace to help with debugging when any part is skipped.
Eugenio
Next changes uses this variables, so avoid call repeatedly to memory
region functions. No functional change intended.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-vdpa.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio/vhos
Sometimes, certain parts are not being skipped in
vhost_vdpa_listener_region_del, but they are skipped in
vhost_vdpa_listener_region_add, or vice versa. The vhost-vdpa code
expects all parts to maintain their properties, so we're adding a trace
to help with debugging when any part is skipped.
Sig
On Fri, 17 Nov 2023 at 07:35, 方 <1584389...@qq.com> wrote:
>
> Hello everyone! I am working on implementing a tool to assess the complexity
> of CPU architecture porting. It primarily focuses on RISC-V architecture
> porting. In fact, the tool may have an average estimate of various
> architect
v3:
- PPC440_PCI -> PPC440_PCIX (Zoltan)
- MIT -> GPLv2 (Zoltan)
v2:
- Squashed 2 patches (Zoltan)
v1:
- Move ppc4xx_pci.c/ppc440_pcix.c from hw/ppc/ to hw/pci-host/
- Build them once for all targets
If it is convenient for PPC maintainers I can queue
this via my misc-hw tree.
Thanks,
Phil.
P
ppc4xx_pci.c is moved from the target specific ppc_ss[] meson
source set to pci_ss[] which is common to all targets: the
object is built once.
Declare PPC4XX_PCI selector in pci-host/Kconfig.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
---
MAINTAINERS |
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: BALATON Zoltan
Reviewed-by: Thomas Huth
---
hw/ppc/ppc440_pcix.c | 1 -
hw/ppc/ppc4xx_pci.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/hw/ppc/ppc440_pcix.c b/hw/ppc/ppc440_pcix.c
index df4ee374d0..d84418cb7b 100644
--- a/hw/ppc/ppc44
ppc440_pcix.c is moved from the target specific ppc_ss[] meson
source set to pci_ss[] which is common to all targets: the
object is built once.
Reviewed-by: Thomas Huth
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS| 2 +-
hw/{ppc => pci-host}/ppc440_pcix.c | 0
h
Reviewed-by: BALATON Zoltan
Reviewed-by: Thomas Huth
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 1 +
include/hw/pci-host/ppc4xx.h | 17 +
include/hw/ppc/ppc4xx.h | 5 -
hw/ppc/ppc440_bamboo.c | 1 +
hw/ppc/ppc440_pcix.c |
From: Shiju Jose
CXL spec 3.1 section 8.2.9.6 describes optional device specific features.
CXL devices supports features with changeable attributes.
Get Supported Features retrieves the list of supported device specific
features. The settings of a feature can be retrieved using Get Feature and
op
From: Shiju Jose
CXL spec 3.1 section 8.2.9.9.11.2 describes the DDR5 Error Check Scrub (ECS)
control feature.
The Error Check Scrub (ECS) is a feature defined in JEDEC DDR5 SDRAM
Specification (JESD79-5) and allows the DRAM to internally read, correct
single-bit errors, and write back corrected
From: Shiju Jose
Add support for the feature commands, device patrol scrub control and
DDR5 ECS control features.
CXL spec 3.1 section 8.2.9.6 describes optional device specific features.
CXL spec 3.1 section 8.2.9.9.11.1 describes the device patrol scrub control
feature.
CXL spec 3.1 section 8.
From: Shiju Jose
CXL spec 3.1 section 8.2.9.9.11.1 describes the device patrol scrub control
feature. The device patrol scrub proactively locates and makes corrections
to errors in regular cycle. The patrol scrub control allows the request to
configure patrol scrub input configurations.
The patr
On 15/2/24 10:15, Manos Pitsidianakis wrote:
Arguments `ram_block` are reassigned to local declarations `block`
without further use. Remove re-assignment to reduce noise.
Signed-off-by: Manos Pitsidianakis
---
system/physmem.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
dif
On Thu, Feb 15, 2024 at 8:55 AM Philippe Mathieu-Daudé
wrote:
> > if (defaults_enabled() && object_class_by_name("pci-ohci")) {
> > pci_create_simple(pci_bus, -1, "pci-ohci");
> > -usb_create_simple(usb_bus_find(-1), "usb-kbd");
> > -usb_create_simple(usb_bus_find(-
Albert Esteve writes:
> On Tue, Feb 6, 2024 at 12:11 AM Alex Bennée wrote:
>
> Albert Esteve writes:
>
> > Ensure that we cleanup all virtio shared
> > resources when the vhost devices is cleaned
> > up (after a hot unplug, or a crash).
> >
> > To do so, we add a new function to the virti
On 2/15/24 06:53, Christoph Müllner wrote:
On Wed, Feb 14, 2024 at 5:25 PM Andrew Jones wrote:
On Wed, Feb 14, 2024 at 02:38:34PM +0100, Christoph Müllner wrote:
On Wed, Feb 14, 2024 at 2:35 PM Daniel Henrique Barboza
wrote:
On 2/7/24 09:22, Christoph Müllner wrote:
The first patch o
Forgot to Cc Anton :/
On 15/2/24 09:46, Philippe Mathieu-Daudé wrote:
Since v2:
- Run check-qtest instead of check-unit in CI (Alex)
Almost 2 years later we got hundreds of cleanups patches
merged, so we can get this patch in. Building the 'any'
target has to be explictly requested in ./configu
On 15/2/24 10:17, Clément Chigot wrote:
This series allows leon3 emulations to record up 4 CPUs.
What is your base commit to apply this series?
It's commit 11be70677c70fdccd452a3233653949b79e97908
Merge tag 'pull-vfio-20240129' of https://github.com/legoater/qemu
into staging
Thanks,
On 31/1/24 09:50, Clément Chigot wrote:
According to the doc (see §4.2.15 in [1]), the reset operation should
not impact %SP.
[1] https://gaisler.com/doc/gr712rc-usermanual.pdf
Signed-off-by: Clément Chigot
---
hw/sparc/leon3.c | 3 ---
1 file changed, 3 deletions(-)
Reviewed-by: Philippe
This is resending of series 20240215082659.1378342-1-rkha...@yandex-team.ru,
where patch subjects numbers were broken in patch 2/2.
Sometimes, when migration fails, it is hard to find out
the cause of the problems: you have to grep qemu logs.
At the same time, there is MIGRATION event, which looks
This patch adds error description as reason for event MIGRATION in every
place that generates MIGRATION_STATE_FAILED
Signed-off-by: Roman Khapov
---
migration/migration.c | 62 ++-
migration/multifd.c | 8 +++---
migration/savevm.c| 12 -
3
This commit adds the optional field reason for the events, which
contains the string, describing reason of status changing.
For example: reason of migration fail.
Function migrate_set_state now accepts 4th argument: the reason to
pass to event. Every call of this function appended with NULL argume
yep，I found this commit too, already patch this commit and test it, the bug
can not reproduce any more
原始邮件
发件人：Fiona Ebner
时间：2024年2月15日 18:29
收件人：M_O_Bz ,qemu-block
抄送："deepa.srinivasan" ,qemu-devel
,ronniesahlberg ,pbonzini
,pl
主题：Re: double free or corruption (out)
On 2/15/24 10:50, Ziqiao Kong wrote:
target/i386: As specified by Intel Manual Vol2 3-180, cmp instructions
are not allowed to have lock prefix and a `UD` should be raised. Without
this patch, s1->T0 will be uninitialized and used in the case OP_CMPL.
Signed-off-by: Ziqiao Kong
---
target/i38
On Tue, Feb 13, 2024 at 6:26 PM Michael S. Tsirkin wrote:
> On Fri, Feb 02, 2024 at 10:32:15PM +0800, Hyman Huang wrote:
> > x-query-virtio-status returns several sets of virtio feature and
> > status flags. It goes back to v7.2.0.
> >
> > In the initial commit 90c066cd682 (qmp: add QMP command
On Thu, 8 Feb 2024 at 19:48, Nabih Estefan wrote:
>
> Accidentally added extra file to v2 that broke email sending (and was
> not meant to be upstreamed). Sending our v3 to skip that confusion.
>
> Removing testing for PCS registers since that doesn't exist on 7xx.
>
> Nabih Estefan (1):
> tests
On Thu, 15 Feb 2024 10:46, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
Add the 'any'-architecture target.
- Only consider 64-bit targets
- Do not use any hardware accelerator (except qtest)
- For architecture constants, use:
. max of supported targets phys/virt address space
On Mon, 12 Feb 2024 at 16:34, Inès Varhol wrote:
>
> Fixes: 52671f69f7a4 ("[PATCH v8 0/3] Add device STM32L4x5 EXTI")
> Signed-off-by: Inès Varhol
> ---
> hw/arm/stm32l4x5_soc.c | 69 --
> 1 file changed, 59 insertions(+), 10 deletions(-)
>
> diff --git a/
On Mon, 12 Feb 2024 at 16:34, Inès Varhol wrote:
>
> This commit adds a QTest that verifies each input line of a specific
> EXTI OR gate can influence the output line.
>
> Signed-off-by: Inès Varhol
> ---
> tests/qtest/stm32l4x5_exti-test.c | 97 +++
> 1 file changed,
Michael Tokarev writes:
> 14.02.2024 16:27, Fabiano Rosas :
>> Michael Tokarev writes:
> ..>>> This change, which is suggested for -stable, while simple by its own,
> seems
to depend on the previous changes in this series, which are not for
-stable.
In particular, whole "Finally
> Am 15.02.2024 um 09:31 schrieb Andreas Kemnade :
>
> On Wed, 14 Feb 2024 23:42:58 +0100
> "Arnd Bergmann" wrote:
>
>> On Wed, Feb 14, 2024, at 13:26, Dmitry Baryshkov wrote:
>>> On Tue, 13 Feb 2024 at 23:22, Linus Walleij
>>> wrote:
On Tue, Feb 13, 2024 at 9:12 PM Arnd Bergmann wr
target/i386/tcg: As specified by Intel Manual Vol2 3-180, cmp instructions
are not allowed to have lock prefix and a `UD` should be raised. Without
this patch, s1->T0 will be uninitialized and used in the case OP_CMPL.
Signed-off-by: Ziqiao Kong
---
target/i386/tcg/translate.c | 11 ++-
Have write_bootloader() take a void* and remove unused 'env' arg.
Philippe Mathieu-Daudé (2):
hw/sparc/leon3: Remove unused 'env' argument of write_bootloader()
hw/sparc/leon3: Have write_bootloader() take a void pointer argument
hw/sparc/leon3.c | 10 +++---
1 file changed, 3 insertions
Hello Qemu Developers! I'm from the downstream project Unicorn
Engine (https://github.com/unicorn-engine/unicorn). I identified a simple
bug that triggers a tcg assertion in QEMU. Although I used a usermode
usecase to illustrate the bug, it shall also affect system emulation.
Assume a binary looks
On Wed, 14 Feb 2024 23:42:58 +0100
"Arnd Bergmann" wrote:
> On Wed, Feb 14, 2024, at 13:26, Dmitry Baryshkov wrote:
> > On Tue, 13 Feb 2024 at 23:22, Linus Walleij
> > wrote:
> >> On Tue, Feb 13, 2024 at 9:12 PM Arnd Bergmann wrote:
> >> > On Tue, Feb 13, 2024, at 16:36, Guenter Roeck wrot
Directly use the void pointer argument returned
by memory_region_get_ram_ptr().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sparc/leon3.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c
index d096fb04cb..8717c72e77 100644
--- a/hw
(Resending this series since it looks like being ignored by the list)
Hello QEMU Developers! I'm from the downstream project Unicorn
Engine (https://github.com/unicorn-engine/unicorn). I identified a simple
bug that triggers a tcg assertion in QEMU. Although I used a usermode
usecase to illustrate
'CPUSPARCState *env' argument is unused, remove it.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sparc/leon3.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c
index 2dfb742566..d096fb04cb 100644
--- a/hw/sparc/leon3.c
+++ b/hw/sparc/le
target/i386: As specified by Intel Manual Vol2 3-180, cmp instructions
are not allowed to have lock prefix and a `UD` should be raised. Without
this patch, s1->T0 will be uninitialized and used in the case OP_CMPL.
Signed-off-by: Ziqiao Kong
---
target/i386/tcg/translate.c | 11 ++-
1 fi
On Fri, Feb 02, 2024 at 12:21:51PM -0300, Daniel Henrique Barboza wrote:
> The RVA22U64 and RVA22S64 profiles mandates certain extensions that,
> until now, we were implying that they were available.
>
> We can't do this anymore since named features also has a riscv,isa
> entry. Let's add them to
On 15/2/24 14:02, Manos Pitsidianakis wrote:
On Thu, 15 Feb 2024 10:46, Philippe Mathieu-Daudé
wrote:
From: Philippe Mathieu-Daudé
Add the 'any'-architecture target.
- Only consider 64-bit targets
- Do not use any hardware accelerator (except qtest)
- For architecture constants, use:
. max
Maybe add
On Thu, Feb 15, 2024 at 12:20:53PM +0300, Michael Tokarev wrote:
> > Akihiko Odaki (2):
> >hw/smbios: Fix OEM strings table option validation
> >hw/smbios: Fix port connector option validation
this
> > Dmitry Osipenko (1):
> >virtio-gpu: Correct virgl_renderer_r
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