On 15/01/2024 12:37, Peter Maydell wrote:
See inline.
On Mon, 15 Jan 2024 at 05:58, Shlomo Pongratz wrote:
Thank you.
Please see comments inline.
On Fri, Jan 12, 2024 at 7:03 PM Peter Maydell wrote:
On Tue, 9 Jan 2024 at 12:45, Shlomo Pongratz wrote:
Hi; thanks for this patch.
Hanlde wr
On 1/12/24 19:45, Richard Henderson wrote:
On 1/13/24 08:38, Daniel Henrique Barboza wrote:
MAXSZ() returns the value in bytes. Now that we have access to vlenb
we don't need to compensate with a '-3' in the scale to use 'vlen'.
MAXSZ() now works as follows:
LMUL lmul=scale MAXSZ (vlenb >
John Snow writes:
> declare, but don't initialize the type of "type" to be QAPISchemaType -
Declare
> and allow the value to be initialized during check(). This creates a
> form of delayed initialization for QAPISchemaType objects where the
> static typing only represents the fully-realized obj
On 12/01/2024 16.39, Philippe Mathieu-Daudé wrote:
Hi Thomas
+Laurent & Peter
On 12/1/24 11:00, Thomas Huth wrote:
It's been marked as deprecated since QEMU 8.1, so it should be fine
to remove this now.
Signed-off-by: Thomas Huth
---
docs/about/deprecated.rst | 6 --
docs/about
On Fri, 8 Dec 2023 at 02:40, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
> hw/arm/bcm2838_pcie.c | 74 +++
> hw/arm/meson.build| 5 ++-
> hw/arm/trace-events | 4 ++
> include/hw/arm/bcm2838_pcie.h | 53 +
John Snow writes:
> This field should always be present and defined after check() is
> called. Declare the property but allow its initialization to be delayed
> until check() so that it can be typed without the use of `Optional`.
>
> This helps simplify typing by avoiding the need to interrogate
>From the 68010 a word with the frame format and exception vector
are placed on the stack before the PC and SR.
M68K_FEATURE_QUAD_MULDIV is currently checked to workout if to do
this or not for the configured CPU but that flag isn't set for
68010 so currently the exception stack when 68010 is conf
John Snow writes:
> These methods should always return a str, it's only the default abstract
> implementation that doesn't. They can be marked "abstract", which
> requires subclasses to override the method with the proper return type.
>
> Signed-off-by: John Snow
> ---
> scripts/qapi/schema.py
(I've cc'd our PCI subsystem maintainers, because I'm not really
confident in reviewing a PCI controller model. Marcel, Michael:
this is one of 3 patches adding the pcie controller for the raspberry
pi 4 SoC. You can find the relevant patches also here:
https://patchew.org/QEMU/20231208023145.13857
On Fri, 8 Dec 2023 at 02:33, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
> hw/arm/bcm2838_pcie.c| 3 +++
> hw/arm/bcm2838_peripherals.c | 26 ++
> hw/arm/meson.build | 7 ---
> hw/arm/raspi4b.c
On Fri, 8 Dec 2023 at 02:33, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
> hw/misc/bcm2838_rng200.c | 152 +++
> hw/misc/meson.build | 1 +
> hw/misc/trace-events | 9 ++
> include/hw/misc/bcm2838_rng200.h | 51
On Fri, 8 Dec 2023 at 02:40, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
> hw/misc/bcm2838_rng200.c | 292 +--
> include/hw/misc/bcm2838_rng200.h | 10 +-
> 2 files changed, 275 insertions(+), 27 deletions(-)
>
> diff --git a/hw/misc/bcm28
Hi Peter,
On Mon, Jan 15, 2024 at 10:41:48AM +, Peter Maydell wrote:
> Date: Mon, 15 Jan 2024 10:41:48 +
> From: Peter Maydell
> Subject: Re: [PATCH 02/11] hw/core: Cleanup unused included headers in
> cpu-common.c
>
> On Mon, 15 Jan 2024 at 09:37, Zhao Liu wrote:
> >
> > From: Zhao Li
On Fri, 8 Dec 2023 at 02:34, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
The commit message doesn't seem to match the changes here.
> ---
> hw/arm/bcm2838_peripherals.c | 14 +
> hw/arm/raspi4b.c | 1 -
> hw/misc/bcm2838_rng200.c | 78
Hi Xiaoyao,
On Mon, Jan 15, 2024 at 12:27:43PM +0800, Xiaoyao Li wrote:
> Date: Mon, 15 Jan 2024 12:27:43 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH v7 15/16] i386: Use offsets get NumSharingCache for
> CPUID[0x801D].EAX[bits 25:14]
>
> On 1/15/2024 11:48 AM, Zhao Liu wrote:
> > Hi Xiao
Hi Xiaoyao,
On Mon, Jan 15, 2024 at 03:00:25PM +0800, Xiaoyao Li wrote:
> Date: Mon, 15 Jan 2024 15:00:25 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH v7 14/16] i386: Use CPUCacheInfo.share_level to encode
> CPUID[4]
>
> On 1/15/2024 2:25 PM, Zhao Liu wrote:
> > Hi Xiaoyao,
> >
> > On Mon, J
On Fri, 8 Dec 2023 at 02:33, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
> hw/arm/bcm2838_peripherals.c | 27 ++--
> hw/arm/raspi4b.c | 1 -
> hw/misc/bcm2838_thermal.c| 98
> hw/misc/meson.build
On Fri, 8 Dec 2023 at 02:40, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
> hw/arm/bcm2838_peripherals.c | 6 ++
> include/hw/arm/bcm2838_peripherals.h | 1 +
> 2 files changed, 7 insertions(+)
>
Reviewed-by: Peter Maydell
thanks
-- PMM
On Mon, Jan 15, 2024 at 7:40 PM Alex Bennée wrote:
>
> Bin Meng writes:
>
> > The Arm dtb changes caused an address change:
> >
> > DefinitionBlock ("", "SSDT", 1, "BOCHS ", "NVDIMM", 0x0001)
> > {
> > [ ... ]
> > -Name (MEMA, 0x43C8)
> > +Name (MEMA, 0x43D8)
> > }
>
>
On Sun, 14 Jan 2024 15:44:53 -0800 Brian Cain wrote:
>
> This is intended to address a coverity finding: CID 1527408.
>
> Signed-off-by: Brian Cain
> ---
Reviewed-by: Matheus Tavares Bernardino
On Fri, 8 Dec 2023 at 02:34, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
> hw/arm/bcm2838.c | 19 +++
> include/hw/arm/bcm2838_peripherals.h | 2 ++
> 2 files changed, 21 insertions(+)
>
> diff --git a/hw/arm/bcm2838.c b/hw/arm/bcm2838.c
>
Peter Xu writes:
> On Mon, Nov 27, 2023 at 05:25:50PM -0300, Fabiano Rosas wrote:
>> From: Nikolay Borisov
>>
>> Implement the outgoing migration side for the 'fixed-ram' capability.
>>
>> A bitmap is introduced to track which pages have been written in the
>> migration file. Pages are written
On Fri, 8 Dec 2023 at 02:36, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
> include/hw/arm/bcm2838_peripherals.h | 2 +
> tests/qtest/bcm2838-mailbox.c| 71
> tests/qtest/bcm2838-mailbox.h| 46 ++
> tests/qtest/meso
On Fri, 8 Dec 2023 at 02:36, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
> tests/qtest/bcm2838-mailbox.h | 139 ++
> 1 file changed, 139 insertions(+)
>
> diff --git a/tests/qtest/bcm2838-mailbox.h b/tests/qtest/bcm2838-mailbox.h
> index 1d02ca
On Fri, 8 Dec 2023 at 02:38, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
> tests/qtest/bcm2838-mailbox.h | 195 +-
> 1 file changed, 190 insertions(+), 5 deletions(-)
>
> diff --git a/tests/qtest/bcm2838-mailbox.h b/tests/qtest/bcm2838-mailbox.
On Fri, 8 Dec 2023 at 02:35, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
> tests/qtest/bcm2838-mailbox.c| 34 ++--
> tests/qtest/bcm2838-mailbox.h| 18 +-
> tests/qtest/bcm2838-mbox-property-test.c | 206 +++
> tests/qtest/meson.b
On Fri, 8 Dec 2023 at 02:40, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
> docs/system/arm/raspi.rst | 11 +++
> 1 file changed, 7 insertions(+), 4 deletions(-)
Typo in the commit message subject.
Otherwise
Reviewed-by: Peter Maydell
thanks
-- PMM
Hi Xiaoyao,
On Mon, Jan 15, 2024 at 03:45:58PM +0800, Xiaoyao Li wrote:
> Date: Mon, 15 Jan 2024 15:45:58 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH v7 10/16] i386/cpu: Introduce cluster-id to X86CPU
>
> On 1/15/2024 1:59 PM, Zhao Liu wrote:
> > (Also cc "machine core" maintainers.)
> >
> >
On Fri, 8 Dec 2023 at 02:36, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
> hw/misc/bcm2835_property.c | 47
> include/hw/arm/raspberrypi-fw-defs.h | 12 ++-
> 2 files changed, 58 insertions(+), 1 deletion(-)
>
> diff --git a/hw/misc/
Am 11.01.2024 um 12:45 hat Markus Armbruster geschrieben:
> Kevin Wolf writes:
>
> > Commit ff32bb53 tried to get minimal struct support into the string
> > output visitor by just making it return "". Unfortunately, it
> > forgot that the caller will still make more visitor calls for the
> > cont
On Fri, 8 Dec 2023 at 02:35, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
> hw/arm/bcm2838_peripherals.c | 16
> hw/arm/raspi4b.c | 17 -
> include/hw/arm/bcm2838_peripherals.h | 2 ++
> 3 files changed, 18 insertio
On Tue, 19 Dec 2023 at 16:11, Peter Maydell wrote:
>
> On Fri, 8 Dec 2023 at 02:32, Sergey Kambalin wrote:
> >
> > Introducing Raspberry Pi 4B model.
> > It contains new BCM2838 SoC, PCIE subsystem,
> > RNG200, Thermal sensor and Genet network controller.
> >
> > It can work with recent linux ker
Hi Xiaoyao,
On Mon, Jan 15, 2024 at 03:16:43PM +0800, Xiaoyao Li wrote:
> Date: Mon, 15 Jan 2024 15:16:43 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH v7 08/16] i386: Expose module level in CPUID[0x1F]
>
> On 1/15/2024 2:35 PM, Zhao Liu wrote:
> > On Mon, Jan 15, 2024 at 02:11:17PM +0800, Xiao
From: Marc-André Lureau
Hi,
The current post-loading code for scanout has a FIXME: it doesn't take the
resource region/rect into account. But there is more, when adding blob migration
support in commit f66767f75c9, I didn't realize that blob resources could be
used for scanouts. This situationn
From: Marc-André Lureau
The current post-loading code for scanout has a FIXME: it doesn't take
the resource region/rect into account. But there is more, when adding
blob migration support in commit f66767f75c9, I didn't realize that blob
resources could be used for scanouts. This situationn leads
From: Marc-André Lureau
qemu_create_displaysurface_pixman() never returns NULL.
Signed-off-by: Marc-André Lureau
---
hw/display/virtio-gpu.c | 4
1 file changed, 4 deletions(-)
diff --git a/hw/display/virtio-gpu.c b/hw/display/virtio-gpu.c
index f8a675eb30..a62ffb1627 100644
--- a/hw/dis
Am 05.12.2023 um 18:14 hat Peter Krempa geschrieben:
> Please see patches for rationale.
>
> Libvirt patches using this new flag will be posted soon-ish (after
> cleanup).
>
> v3:
> - changed name of flag to 'backing-mask-protocol' (Eric)
> - decided to keep Vladimir's R-b as he requested short
On 15/1/24 15:45, Zhao Liu wrote:
Hi Peter,
On Mon, Jan 15, 2024 at 10:41:48AM +, Peter Maydell wrote:
Date: Mon, 15 Jan 2024 10:41:48 +
From: Peter Maydell
Subject: Re: [PATCH 02/11] hw/core: Cleanup unused included headers in
cpu-common.c
On Mon, 15 Jan 2024 at 09:37, Zhao Liu wr
On 1/15/24 03:02, Philippe Mathieu-Daudé wrote:
Hi,
On 13/1/24 20:16, Guenter Roeck wrote:
Allwinner R40 supports two USB host ports shared between a USB 2.0 EHCI
host controller and a USB 1.1 OHCI host controller. Add support for both
of them.
If machine USB support is not enabled, create uni
(I've cc'd a few people who might have opinions on possible
command-line compatibility breakage.)
On Wed, 10 Jan 2024 at 14:38, Bohdan Kostiv wrote:
>
> Hello,
>
> I have faced an issue in using serial ports when I need to skip a couple of
> ports in the CLI.
>
> For example the ARM machine netd
On Mon, Jan 15, 2024 at 05:07:52PM +0100, Philippe Mathieu-Daudé wrote:
> Date: Mon, 15 Jan 2024 17:07:52 +0100
> From: Philippe Mathieu-Daudé
> Subject: Re: [PATCH 02/11] hw/core: Cleanup unused included headers in
> cpu-common.c
>
> On 15/1/24 15:45, Zhao Liu wrote:
> > Hi Peter,
> >
> > On M
Introduce support for the proposed new (fast-track) Zaamo and Zalrsc
extensions [1] which represent the AMO and LR/SC subsets of the A
extension.
The motivation for the subsets being available separately is that
certain classes of CPUs may choose to only implement a subset for
architectural conv
These extensions represent the atomic operations from A (Zaamo) and the
Load-Reserved/Store-Conditional operations from A (Zalrsc)
Signed-off-by: Rob Bradford
---
target/riscv/cpu.c | 5 +
target/riscv/cpu_cfg.h | 2 ++
2 files changed, 7 insertions(+)
diff --git a/target/riscv/cpu.c b/
Following the pattern for 'M' and Zmmul check if either the 'A'
extension is enabled or the appropriate split extension for the
instruction.
Also remove the assumption that only checking for 64-bit systems is
required for the double word variants.
Signed-off-by: Rob Bradford
---
target/riscv/in
On 15/1/24 17:12, Guenter Roeck wrote:
On 1/15/24 03:02, Philippe Mathieu-Daudé wrote:
Hi,
On 13/1/24 20:16, Guenter Roeck wrote:
Allwinner R40 supports two USB host ports shared between a USB 2.0 EHCI
host controller and a USB 1.1 OHCI host controller. Add support for both
of them.
If machin
Dear QEMU and KVM communities,
QEMU will apply for the Google Summer of Code and Outreachy internship
programs again this year. Regular contributors can submit project
ideas that they'd like to mentor by replying to this email before
January 30th.
Internship programs
---
GS
Peter Xu writes:
> On Mon, Nov 27, 2023 at 05:25:51PM -0300, Fabiano Rosas wrote:
>> Add the necessary code to parse the format changes for the 'fixed-ram'
>> capability.
>>
>> One of the more notable changes in behavior is that in the 'fixed-ram'
>> case ram pages are restored in one go rather
On Mon, 15 Jan 2024 at 13:51, Shlomo Pongratz wrote:
>
> On 15/01/2024 12:37, Peter Maydell wrote:
> > For instance, the kernel code suggests that pre-460A
> > there's a 32 bit limit register, and post-460A there
> > is a 64-bit limit (with an "UPPER_LIMIT" register to
> > access the top 32 bits),
When a chipset contain a USB controller, we can not simply
remove it. We could disable it, but that requires more changes
this series isn't aiming for. For more context:
https://lore.kernel.org/qemu-devel/56fde49f-7dc6-4f8e-9bbf-0336a20a9...@roeck-us.net/
Philippe Mathieu-Daudé (2):
hw/arm/allwi
The TUSB6010 USB controller is solderer on the N800 and N810
tablets, thus is always present.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/nseries.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
index 35aff46b4b..35deb74f65 100644
The USB Controllers are part of the chipset, thus are
always present and mapped in memory.
Reported-by: Guenter Roeck
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/allwinner-a10.c | 49 +-
1 file changed, 20 insertions(+), 29 deletions(-)
diff --git a
On Mon, 15 Jan 2024 at 16:56, Philippe Mathieu-Daudé wrote:
>
> When a chipset contain a USB controller, we can not simply
> remove it. We could disable it, but that requires more changes
> this series isn't aiming for. For more context:
> https://lore.kernel.org/qemu-devel/56fde49f-7dc6-4f8e-9bbf
On Tue, 19 Dec 2023 at 18:23, Samuel Tardieu wrote:
>
> Unreachable code in an error handling block is listed in issue
> https://gitlab.com/qemu-project/qemu/-/issues/2030.
>
> After removing this code, the `fail` label is now immediately followed
> by a test whose condition can never be true when
On Mon, 15 Jan 2024 at 09:22, Anastasia Belova wrote:
>
> j is used while loading an ELF file to byteswap segments'
> data. If data is larger than 2GB an overflow may happen.
> So j should be elf_word.
>
> This commit fixes a minor bug, maybe even a typo.
>
> Found by Linux Verification Center (li
On 1/15/24 08:30, Philippe Mathieu-Daudé wrote:
On 15/1/24 17:12, Guenter Roeck wrote:
On 1/15/24 03:02, Philippe Mathieu-Daudé wrote:
Hi,
On 13/1/24 20:16, Guenter Roeck wrote:
Allwinner R40 supports two USB host ports shared between a USB 2.0 EHCI
host controller and a USB 1.1 OHCI host con
On Sun, 14 Jan 2024 15:23:54 -0800 Brian Cain wrote:
>
> This update includes support for privileged instructions.
>
> Signed-off-by: Brian Cain
> ---
Reviewed-by: Matheus Tavares Bernardino
Tested-by: Matheus Tavares Bernardino
> diff --git a/tests/docker/dockerfiles/debian-hexagon-cross.do
On Thu, 11 Jan 2024 at 13:33, Rayhan Faizel wrote:
>
> This patch implements a 32 half word FIFO as per imx serial device
> specifications. If a non empty FIFO is below the trigger level, an ageing
> timer will tick for a duration of 8 characters. On expiry, AGTIM will be set
> triggering an inter
On Mon, 15 Jan 2024 at 13:54, Thomas Huth wrote:
>
> On 12/01/2024 16.39, Philippe Mathieu-Daudé wrote:
> > Hi Thomas
> >
> > +Laurent & Peter
> >
> > On 12/1/24 11:00, Thomas Huth wrote:
> >> It's been marked as deprecated since QEMU 8.1, so it should be fine
> >> to remove this now.
> >>
> >> Si
On 1/12/24 19:51, Richard Henderson wrote:
On 1/13/24 08:38, Daniel Henrique Barboza wrote:
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvv.c.inc | 26 +
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/target/riscv/insn_t
On Mon, Jan 15, 2024 at 05:39:19PM +, Peter Maydell wrote:
> On Mon, 15 Jan 2024 at 13:54, Thomas Huth wrote:
> >
> > On 12/01/2024 16.39, Philippe Mathieu-Daudé wrote:
> > > Hi Thomas
> > >
> > > +Laurent & Peter
> > >
> > > On 12/1/24 11:00, Thomas Huth wrote:
> > >> It's been marked as depr
On Mon, Jan 15, 2024 at 05:56:14PM +0100, Philippe Mathieu-Daudé wrote:
> The USB Controllers are part of the chipset, thus are
> always present and mapped in memory.
>
> Reported-by: Guenter Roeck
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Guenter Roeck
Tested-by: Guenter Roeck
Add watchdog timer support to Allwinner-H40 and Bananapi.
The watchdog timer is added as an overlay to the Timer
module memory map.
Signed-off-by: Guenter Roeck
---
docs/system/arm/bananapi_m2u.rst | 2 +-
hw/arm/Kconfig | 1 +
hw/arm/allwinner-r40.c | 8
inc
Add support for
- USB 2.0 EHCI/OHCI
- SATA/AHCI
- Watchdog
to Allwinner R40. The hardware is quite similar to Allwinner A10 and H3,
so the code is derived from the implementations for those SOCs.
Tested with bpim2u emulation by instantiating EHCI and OHCI keyboards,
by booting from USB, by booti
Allwinner R40 supports two USB host ports shared between a USB 2.0 EHCI
host controller and a USB 1.1 OHCI host controller. Add support for both
of them.
If machine USB support is not enabled, create unimplemented devices
for the USB memory ranges to avoid crashes when booting Linux.
Signed-off-b
Allwinner R40 supports an AHCI compliant SATA controller.
Add support for it.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Guenter Roeck
---
docs/system/arm/bananapi_m2u.rst | 1 +
hw/arm/Kconfig | 1 +
hw/arm/allwinner-r40.c | 12 +++-
include/hw/arm
Peter Xu writes:
> On Mon, Nov 27, 2023 at 05:25:53PM -0300, Fabiano Rosas wrote:
>> For the upcoming support to the new 'fixed-ram' migration stream
>> format, we cannot use multifd packets because each write into the
>> ramblock section in the migration file is expected to contain only the
>> g
On Fri, Jan 12, 2024 at 07:36:19PM +0900, Akihiko Odaki wrote:
> Coroutine may be pooled even after COROUTINE_TERMINATE if
> CONFIG_COROUTINE_POOL is enabled and fake stack should be saved in
> such a case to keep AddressSanitizerUseAfterReturn working. Even worse,
> I'm seeing stack corruption wit
On 1/15/24 15:46, Bin Meng wrote:
> On Mon, Jan 15, 2024 at 7:40 PM Alex Bennée wrote:
>>
>> Bin Meng writes:
>>
>>> The Arm dtb changes caused an address change:
>>>
>>> DefinitionBlock ("", "SSDT", 1, "BOCHS ", "NVDIMM", 0x0001)
>>> {
>>> [ ... ]
>>> -Name (MEMA, 0x43C8)
>>>
Peter Xu writes:
> On Thu, Jan 11, 2024 at 03:38:31PM -0300, Fabiano Rosas wrote:
>> Peter Xu writes:
>>
>> > On Mon, Nov 27, 2023 at 05:25:42PM -0300, Fabiano Rosas wrote:
>> >> Hi,
>> >>
>> >> In this v3:
>> >>
>> >> Added support for the "file:/dev/fdset/" syntax to receive multiple
>> >>
On Mon, Jan 15, 2024 at 7:18 AM Markus Armbruster wrote:
>
> John Snow writes:
>
> > Suggested-by: Markus Armbruster
> > Signed-off-by: John Snow
> > ---
> > scripts/qapi/pylintrc | 6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/scripts/qapi/pylintrc b/scrip
On 1/16/24 04:57, Daniel Henrique Barboza wrote:
I am now wondering if this is worth the trouble, and we should instead do:
+ int vlmax = cpu->cfg.vlenb >> (s->sew - s->lmul);
Like we're already doing in patch 9. Patch 12 would be a similar case.
This is more like what I expected to see.
Hi,
Ido reported that we are missing the CVDG emulation (which is very
similar to the existing CVD emulation). This series adds it along with
a test.
Best regards,
Ilya
Ilya Leoshkevich (2):
target/s390x: Emulate CVDG
tests/tcg/s390x: Test CONVERT TO DECIMAL
target/s390x/helper.h
Check the CVD's and CVDG's corner cases.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.target | 1 +
tests/tcg/s390x/cvd.c | 42 +
2 files changed, 43 insertions(+)
create mode 100644 tests/tcg/s390x/cvd.c
diff --git a/tests/tcg/s390x/M
CVDG is the same as CVD, except that it converts 64 bits into 128,
rather than 32 into 64. Use larger data types in the CVD helper and
reuse it.
Reported-by: Ido Plat
Signed-off-by: Ilya Leoshkevich
---
target/s390x/helper.h| 1 +
target/s390x/tcg/insn-data.h.inc | 1 +
target/s39
On Mon, Jan 15, 2024 at 8:16 AM Markus Armbruster wrote:
>
> John Snow writes:
>
> > Include entities don't have names, but we generally expect "entities" to
> > have names. Reclassify all entities with names as *definitions*, leaving
> > the nameless include entities as QAPISchemaEntity instance
> -Original Message-
> From: Brian Cain
> Sent: Sunday, January 14, 2024 5:21 PM
> To: Taylor Simpson ; qemu-devel@nongnu.org
> Cc: Matheus Bernardino (QUIC) ; Sid
> Manning ; Marco Liebel (QUIC)
> ; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng; a...@rev.ng
> Subject:
On 12/20/23 05:22, Samuel Tardieu wrote:
Unreachable code in an error handling block is listed in issue
https://gitlab.com/qemu-project/qemu/-/issues/2030.
After removing this code, the `fail` label is now immediately followed
by a test whose condition can never be true when coming explicitly
vi
On 1/13/24 07:57, Robbin Ehn wrote:
Commit f4e1168198 (linux-user: Split out host_sig{segv,bus}_handler)
introduced a bug, when returning from host_sigbus_handler the PC is
never set. Thus cpu_loop_exit_restore is called with a zero PC and
we immediate get a SIGSEGV.
Signed-off-by: Robbin Ehn
-
The Decodetree Specification can be found here
https://www.qemu.org/docs/master/devel/decodetree.html
Covers all 32-bit instructions, including HVX
We generate separate decoders for each instruction class. The reason
will be more apparent in the next patch in this series.
We add 2 new scripts
Now that we are using QEMU decodetree.py, remove the old decoder
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
---
target/hexagon/opcodes.h| 2 -
target/hexagon/decode.c | 344
target/hexagon/gen_dectree_import.c | 49
target/hexa
Replace the old Hexagon dectree.py with QEMU decodetree
Changes in v2
Suggested Python improvements from Brian Cain
Taylor Simpson (3):
Hexagon (target/hexagon) Use QEMU decodetree (32-bit instructions)
Hexagon (target/hexagon) Use QEMU decodetree (16-bit instructions)
Hexagon (
Section 10.3 of the Hexagon V73 Programmer's Reference Manual
A duplex is encoded as a 32-bit instruction with bits [15:14] set to 00.
The sub-instructions that comprise a duplex are encoded as 13-bit fields
in the duplex.
Create a decoder for each subinstruction class (a, l1, l2, s1, s2).
Exten
Hi,
This v2 contains changes proposed after the review from Richard. Most
notable change is in patch 11, where we simplified our lives a bit and
just calculated 'vlmax' using 'vlenb' instead of trying to use the TCG
global 'cpu_vl'.
Patch 10 also changed a bit to avoid the negative shift we were
Use s->cfg_ptr->vlenb instead of "s->cfg_ptr->vlen / 8" and
"s->cfg_ptr->vlen >> 3".
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvv.c.inc | 140
1 file changed, 70 insertions(+), 70 deletions(-)
diff --git a/target/riscv/insn_trans/trans_r
Use the new 'vlenb' CPU config to validate fractional LMUL. The original
comparison is done with 'vlen' and 'sew', both in bits. Adjust the shift
to use vlenb.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/vector_helper.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
d
Use the same vext_get_vlmax() logic to retrieve 'vlmax' in
trans_vrgather_vi() and trans_vrgather_vx().
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvv.c.inc | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c
Use s->cfg_ptr->vlenb instead of s->cfg_ptr->vlen / 8.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvvk.c.inc | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc
b/target/riscv/insn_trans/tran
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/gdbstub.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 58b3ace0fe..5ab0abda19 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -130,7 +130,
There is no need to keep both 'vlen' and 'vlenb'. All existing code
that requires 'vlen' is retrieving it via 'vlenb << 3'.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 8 +++-
target/riscv/cpu_cfg.h | 1 -
target/riscv/tcg/tcg-cpu.c | 4 +++-
3 files changed,
Use ctx->cfg_ptr->vlenb instead of ctx->cfg_ptr->vlen / 8.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvbf16.c.inc | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc
b/target/riscv/insn_trans/
Use 'cpu->cfg.vlenb' instead of 'cpu->cfg.vlen >> 3'.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/vector_helper.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index c1c3a4d1ea..cb944
Our usage of 'vlenb' is overwhelming superior than the use of 'vlen'.
We're using 'vlenb' most of the time, having to do 'vlen >> 3' or
'vlen / 8' in every instance.
In hindsight we would be better if the 'vlenb' property was introduced
instead of 'vlen'. That's not what happened, and now we can'
As a bonus, we're being more idiomatic using cpu->cfg.vlenb when
reading CSR_VLENB.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/csr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 674ea075a4..5c8d22452b 100644
--
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 11df226a00..7304e478c2 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -692,7 +692,11 @@ static inline u
Calculate the maximum vector size possible, 'max_sz', which is the size
in bytes 'vlenb' multiplied by the max value of LMUL (LMUL = 8, when
s->lmul = 3).
'max_sz' is then shifted right by 'scale', expressed as '3 - s->lmul',
which is clearer than doing 'scale = lmul - 3' and then using '-scale'
i
On 1/16/24 09:25, Daniel Henrique Barboza wrote:
Our usage of 'vlenb' is overwhelming superior than the use of 'vlen'.
We're using 'vlenb' most of the time, having to do 'vlen >> 3' or
'vlen / 8' in every instance.
In hindsight we would be better if the 'vlenb' property was introduced
instead o
On 1/16/24 09:25, Daniel Henrique Barboza wrote:
As a bonus, we're being more idiomatic using cpu->cfg.vlenb when
reading CSR_VLENB.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/csr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson
r~
On 1/16/24 09:25, Daniel Henrique Barboza wrote:
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/gdbstub.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson
r~
On 1/16/24 09:25, Daniel Henrique Barboza wrote:
Use ctx->cfg_ptr->vlenb instead of ctx->cfg_ptr->vlen / 8.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvbf16.c.inc | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
Reviewed-by: Richard Henderson
On 1/16/24 09:25, Daniel Henrique Barboza wrote:
Use s->cfg_ptr->vlenb instead of "s->cfg_ptr->vlen / 8" and
"s->cfg_ptr->vlen >> 3".
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvv.c.inc | 140
1 file changed, 70 insertions(+), 70 deleti
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