On Fri, Jan 05, 2024 at 03:04:46PM -0300, Fabiano Rosas wrote:
> Reviewed-by: Thomas Huth
> Signed-off-by: Fabiano Rosas
Reviewed-by: Peter Xu
--
Peter Xu
On Fri, Jan 05, 2024 at 03:04:47PM -0300, Fabiano Rosas wrote:
> We can run the migration tests with two different QEMU binaries to
> test migration compatibility between QEMU versions. This means we'll
> be running the tests with an older QEMU in either source or
> destination.
>
> We need to avo
From: Zhao Liu
In cpu_x86_cpuid(), there are many variables in representing the cpu
topology, e.g., topo_info, cs->nr_cores/cs->nr_threads.
Since the names of cs->nr_cores/cs->nr_threads does not accurately
represent its meaning, the use of cs->nr_cores/cs->nr_threads is prone
to confusion and m
From: Zhao Liu
CPUID[0xB] defines SMT, Core and Invalid types, and this leaf is shared
by Intel and AMD CPUs.
But for extended topology levels, Intel CPU (in CPUID[0x1F]) and AMD CPU
(in CPUID[0x8026]) have the different definitions with different
enumeration values.
Though CPUID[0x8026
From: Zhao Liu
At present, the subleaf 0x02 of CPUID[0x1F] is bound to the "die" level.
In fact, the specific topology level exposed in 0x1F depends on the
platform's support for extension levels (module, tile and die).
To help expose "module" level in 0x1F, decouple CPUID[0x1F] subleaf
with sp
From: Zhuocheng Ding
smp command has the "clusters" parameter but x86 hasn't supported that
level. "cluster" is a CPU topology level concept above cores, in which
the cores may share some resources (L2 cache or some others like L3
cache tags, depending on the Archs) [1][2]. For x86, the resource
From: Zhao Liu
Hi list,
This is the our v7 patch series, rebased on the master branch at the
commit d328fef93ae7 ("Merge tag 'pull-20231230' of
https://gitlab.com/rth7680/qemu into staging").
No more change since v6 [1] exclude the comment nit update.
Welcome your comments!
PS: Since v5, we
From: Zhao Liu
Refer to the fixes of cache_info_passthrough ([1], [2]) and SDM, the
CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] should use the
nearest power-of-2 integer.
The nearest power-of-2 integer can be calculated by pow2ceil() or by
using APIC ID offset (like L3 topology using
From: Zhao Liu
Currently, by default, the cache topology is encoded as:
1. i/d cache is shared in one core.
2. L2 cache is shared in one core.
3. L3 cache is shared in one die.
This default general setting has caused a misunderstanding, that is, the
cache topology is completely equated with a sp
On Fri, Jan 05, 2024 at 03:04:49PM -0300, Fabiano Rosas wrote:
> [This patch is not necessary anymore after 8.2 has been released]
>
> Add the 'since' annotations to recently added tests and adapt the
> postcopy test to use the older "uri" API when needed.
>
> Signed-off-by: Fabiano Rosas
You m
From: Zhuocheng Ding
Support module level in i386 cpu topology structure "X86CPUTopoInfo".
Since x86 does not yet support the "clusters" parameter in "-smp",
X86CPUTopoInfo.modules_per_die is currently always 1. Therefore, the
module level width in APIC ID, which can be calculated by
"apicid_bit
From: Zhao Liu
For i-cache and d-cache, current QEMU hardcodes the maximum IDs for CPUs
sharing cache (CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits
25:14]) to 0, and this means i-cache and d-cache are shared in the SMT
level.
This is correct if there's single thread per core, but is
From: Zhuocheng Ding
Add module_id member in X86CPUTopoIDs.
module_id can be parsed from APIC ID, so also update APIC ID parsing
rule to support module level. With this support, the conversions with
module level between X86CPUTopoIDs, X86CPUTopoInfo and APIC ID are
completed.
module_id can be a
From: Zhao Liu
The commit 8f4202fb1080 ("i386: Populate AMD Processor Cache Information
for cpuid 0x801D") adds the cache topology for AMD CPU by encoding
the number of sharing threads directly.
>From AMD's APM, NumSharingCache (CPUID[0x801D].EAX[bits 25:14])
means [1]:
The number of lo
From: Zhuocheng Ding
After i386 supports module level, it's time to add the test for module
level's parsing.
Signed-off-by: Zhuocheng Ding
Co-developed-by: Zhao Liu
Signed-off-by: Zhao Liu
Reviewed-by: Yanan Wang
Tested-by: Babu Moger
Tested-by: Yongwei Ma
Acked-by: Michael S. Tsirkin
---
From: Zhao Liu
Linux kernel (from v6.4, with commit edc0a2b595765 ("x86/topology: Fix
erroneous smp_num_siblings on Intel Hybrid platforms") is able to
handle platforms with Module level enumerated via CPUID.1F.
Expose the module level in CPUID[0x1F] if the machine has more than 1
modules.
(Tes
From: Zhuocheng Ding
As module-level topology support is added to X86CPU, now we can enable
the support for the cluster parameter on PC machines. With this support,
we can define a 5-level x86 CPU topology with "-smp":
-smp cpus=*,maxcpus=*,sockets=*,dies=*,clusters=*,cores=*,threads=*.
Additio
From: Zhao Liu
CPUID[4].EAX[bits 25:14] is used to represent the cache topology for
Intel CPUs.
After cache models have topology information, we can use
CPUCacheInfo.share_level to decide which topology level to be encoded
into CPUID[4].EAX[bits 25:14].
And since maximum_processor_id (original
From: Zhuocheng Ding
Introduce cluster-id other than module-id to be consistent with
CpuInstanceProperties.cluster-id, and this avoids the confusion
of parameter names when hotplugging.
Following the legacy smp check rules, also add the cluster_id validity
into x86_cpu_pre_plug().
Signed-off-by
From: Zhao Liu
CPUID[0x801D].EAX[bits 25:14] NumSharingCache: number of logical
processors sharing cache.
The number of logical processors sharing this cache is
NumSharingCache + 1.
After cache models have topology information, we can use
CPUCacheInfo.share_level to decide which topology le
On Mon, Jan 08, 2024 at 04:13:10PM +0800, Peter Xu wrote:
> On Fri, Jan 05, 2024 at 03:04:47PM -0300, Fabiano Rosas wrote:
> > We can run the migration tests with two different QEMU binaries to
> > test migration compatibility between QEMU versions. This means we'll
> > be running the tests with an
On 1/2/24 05:57, Richard Henderson wrote:
Use TARGET_PAGE_SIZE and MAP_FIXED_NOREPLACE.
We really should be attending to this earlier during
probe_guest_base, as well as better detection and
emulation of various Linux personalities.
Signed-off-by: Richard Henderson
---
linux-user/elfload.c |
On 1/2/24 05:57, Richard Henderson wrote:
AT_PAGESZ is supposed to advertise the guest page size.
The random adjustment made here using qemu_host_page_size
does not match anything else within linux-user.
The idea here is good, but should be done more systemically
via adjustment to TARGET_PAGE_SI
On 1/2/24 05:57, Richard Henderson wrote:
If reserved_va, then we have already reserved the entire
guest virtual address space; no need to remap page.
If !reserved_va, then use MAP_FIXED_NOREPLACE.
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 23 ++-
1 file
On 1/2/24 05:57, Richard Henderson wrote:
Use qemu_real_host_page_size.
If !reserved_va, use MAP_FIXED_NOREPLACE.
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/linux-user/elfload.c b/linux-user/elf
On 1/2/24 05:57, Richard Henderson wrote:
The host SHMLBA is by definition a multiple of the host page size.
Thus the remaining component of qemu_host_page_size is the
target page size.
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 4 ++--
1 file changed, 2 insertions(+), 2 del
On 1/2/24 05:57, Richard Henderson wrote:
Use qemu_real_host_page_size.
If the commpage is not within reserved_va, use MAP_FIXED_NOREPLACE.
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/linux-user/e
On 1/7/24 18:01, Nicholas Piggin wrote:
The 390x tag should be s390x.
Signed-off-by: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
.gitlab-ci.d/buildtest.yml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/.gitlab-ci.d/buildtest.yml b/.gitlab-ci.d/
On 1/2/24 05:57, Richard Henderson wrote:
Use qemu_real_host_page_size instead.
Signed-off-by: Richard Henderson
---
linux-user/mmap.c | 66 +++
1 file changed, 33 insertions(+), 33 deletions(-)
diff --git a/linux-user/mmap.c b/linux-user/mmap.c
i
On 1/7/24 18:01, Nicholas Piggin wrote:
The ppc64 and s390x tests were first marked skipIf GITLAB_CI by commit
c0c8687ef0f ("tests/avocado: disable BootLinuxPPC64 test in CI"), and
commit 0f26d94ec9e ("tests/acceptance: skip s390x_ccw_vrtio_tcg on
GitLab") due to being very heavy-weight for gitla
smilatncy tests in bios bits seems to generate some flakyness in running the
bits avocado tests. Disable them for now.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2077
CC: peter.mayd...@linaro.org
CC: cr...@redhat.com
CC: phi...@linaro.org
CC: bl...@redhat.com
CC: m...@redhat.com
CC:
Add smilatency test script in the bits avocado tests from bios-bits. No changes
have been made to the original test script. The test will be disabled in the
subsequent patch.
CC: peter.mayd...@linaro.org
CC: cr...@redhat.com
CC: phi...@linaro.org
CC: bl...@redhat.com
CC: m...@redhat.com
CC: waine.
smilatncy tests in bios bits seems to generate some flakyness in running the
bits avocado tests. Disable them for now.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2077
CC: peter.mayd...@linaro.org
CC: cr...@redhat.com
CC: phi...@linaro.org
CC: bl...@redhat.com
CC: m...@redhat.com
CC:
Add smilatency test script in the bits avocado tests from bios-bits. No changes
have been made to the original test script. The test will be disabled in the
subsequent patch.
CC: peter.mayd...@linaro.org
CC: cr...@redhat.com
CC: phi...@linaro.org
CC: bl...@redhat.com
CC: m...@redhat.com
CC: waine.
Import smilatency test from bios-bits and disable it. It is causing some
flakyness and occassional failures in bios-bits avocado tests.
Please see ticket https://gitlab.com/qemu-project/qemu/-/issues/2077
CC: peter.mayd...@linaro.org
CC: cr...@redhat.com
CC: phi...@linaro.org
CC: bl...@redhat.com
> On 07-Jan-2024, at 9:56 PM, Ani Sinha wrote:
>
> On Sat, Jan 6, 2024 at 5:39 PM Peter Maydell wrote:
>>
>> On Sat, 6 Jan 2024 at 05:41, Ani Sinha wrote:
>>>
>>> On Sat, Jan 6, 2024 at 10:05 AM Ani Sinha wrote:
On Sat, Jan 6, 2024 at 12:11 AM Peter Maydell
wrote:
>
On 1/2/24 05:57, Richard Henderson wrote:
This removes a hidden use of qemu_host_page_size, using instead
the existing host_page_size local within each function.
Signed-off-by: Richard Henderson
---
linux-user/mmap.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff -
On 1/2/24 05:57, Richard Henderson wrote:
Replace with the maximum of the real host page size
and the target page size. This is an exact replacement.
Signed-off-by: Richard Henderson
---
migration/ram.c | 22 ++
1 file changed, 18 insertions(+), 4 deletions(-)
diff --gi
On Fri, 5 Jan 2024 19:05:58 +0800
"" <273415...@qq.com> wrote:
> Dear Experts,
>
+CC linux-cxl as a lot more CXL focused folk there who may be interested
in this discussion.
> I am writing to seek your assistance about CXL emulation in QEMU. I
> am Zhou Tong and I am researching how to use
On 03/01/2024 18.40, Philippe Mathieu-Daudé wrote:
On 3/1/24 18:33, Alex Bennée wrote:
From: Daniel P. Berrangé
The npcm7xx_pwn-test takes 3 & 1/2 minutes in a --enable-debug build.
Bumping to 5 minutes will give more headroom.
Signed-off-by: Daniel P. Berrangé
Reviewed-by: Thomas Huth
Mess
On 1/2/24 05:57, Richard Henderson wrote:
All "goto fail" may be transformed to "return -1".
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/mmap.c | 62 ++-
1 file changed, 35 insertions(+), 27 deletions(-)
di
On 1/7/24 18:01, Nicholas Piggin wrote:
Add test for POWER10.
Signed-off-by: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
tests/avocado/boot_linux_console.py | 8
1 file changed, 8 insertions(+)
diff --git a/tests/avocado/boot_linux_console.py
b/tests/avoc
On 1/7/24 18:01, Nicholas Piggin wrote:
ppc has no avocado tests for the KVM backend. Add a KVM boot_linux.py
test for pseries.
Signed-off-by: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
tests/avocado/boot_linux.py | 8
1 file changed, 8 insertions(+)
diff
On 1/2/24 05:57, Richard Henderson wrote:
We cannot skip over the_end1 to the_end, because we fail to
record the validity of the guest page with the interval tree.
Remove "the_end" and rename "the_end1" to "the_end".
Signed-off-by: Richard Henderson
---
linux-user/mmap.c | 5 ++---
1 file ch
On Mon, 8 Jan 2024 at 10:35, Ani Sinha wrote:
>
> Add smilatency test script in the bits avocado tests from bios-bits. No
> changes
> have been made to the original test script. The test will be disabled in the
> subsequent patch.
>
> CC: peter.mayd...@linaro.org
> CC: cr...@redhat.com
> CC: phi.
Signed-off-by: Shlomo Pongratz
---
hw/pci-host/designware.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index dd9e389c07..7ce4a6b64d 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@
On 1/2/24 05:58, Richard Henderson wrote:
Since aarch64 binaries are generally built for multiple
page sizes, it is trivial to allow the page size to vary.
Signed-off-by: Richard Henderson
---
target/arm/cpu-param.h | 6 -
target/arm/cpu.c | 51
On 05/01/2024 20.11, Peter Maydell wrote:
https://gitlab.com/qemu-project/qemu/-/jobs/5871592479
failed with
$ htags -anT --tree-view=filetree -m qemu_init -t "Welcome to the QEMU
sourcecode"
htags: Negative exec line limit = -371
Does anybody have any idea what this is about ?
In case you h
On 1/2/24 05:58, Richard Henderson wrote:
Since alpha binaries are generally built for multiple
page sizes, it is trivial to allow the page size to vary.
Signed-off-by: Richard Henderson
---
target/alpha/cpu-param.h | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
dif
> On 08-Jan-2024, at 4:28 PM, Peter Maydell wrote:
>
> On Mon, 8 Jan 2024 at 10:35, Ani Sinha wrote:
>>
>> Add smilatency test script in the bits avocado tests from bios-bits. No
>> changes
>> have been made to the original test script. The test will be disabled in the
>> subsequent patch.
On 1/2/24 05:57, Richard Henderson wrote:
For reserved_va, place all non-fixed maps then proceed
as for MAP_FIXED.
Signed-off-by: Richard Henderson
---
linux-user/mmap.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/linux-user/mmap.c b/linux-user/mmap.c
ind
On 06/01/2024 14.01, Samuel Tardieu wrote:
An apparent copy-paste error tests for the presence of the
virtio-rng-ccw device in order to perform tests on the virtio-scsi-ccw
device.
Signed-off-by: Samuel Tardieu
---
tests/qtest/virtio-ccw-test.c | 2 +-
1 file changed, 1 insertion(+), 1 delet
On 1/2/24 05:57, Richard Henderson wrote:
These tests are confused, because -p does not change
the guest page size, but the host page size.
Signed-off-by: Richard Henderson
---
tests/tcg/alpha/Makefile.target | 3 ---
tests/tcg/arm/Makefile.target | 3 ---
tests/tcg/hppa/Makefil
On 1/2/24 05:57, Richard Henderson wrote:
Align allocation sizes to the maximum of host and target page sizes.
Signed-off-by: Richard Henderson
---
system/physmem.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/system/physmem.c b/system/physmem.c
index
On 07/01/2024 15.05, Thomas Weißschuh wrote:
misc/pvpanic.h from the Linux UAPI does not define a Linux UAPI but a
qemu device API.
This leads to a weird process when updates to the interface are needed:
1) Change to the specification in the qemu tree
2) Change to the header in the Linux tree
3)
On 07/01/2024 15.05, Thomas Weißschuh wrote:
The different components of pvpanic duplicate the list of supported
events. Move it to the shared header file to minimize changes when new
events are added.
Signed-off-by: Thomas Weißschuh
---
hw/misc/pvpanic-isa.c | 2 +-
hw/misc/pvpanic-pci.
On 1/2/24 05:57, Richard Henderson wrote:
Move the MAX_FIXED_NOREPLACE check for reserved_va earlier.
Move the computation of host_prot earlier.
Signed-off-by: Richard Henderson
---
linux-user/mmap.c | 66 +--
1 file changed, 53 insertions(+), 13 d
On 1/2/24 05:57, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
linux-user/mmap.c | 288 ++
1 file changed, 139 insertions(+), 149 deletions(-)
diff --git a/linux-user/mmap.c b/linux-user/mmap.c
index 8b0a26e50d..552656edd4 100644
--
On Fri, Jan 05, 2024 at 09:19:14AM -0300, Daniel Henrique Barboza wrote:
>
>
> On 1/5/24 06:06, Sia Jee Heng wrote:
> > RISC-V should also generate the SPCR in a manner similar to ARM.
> > Therefore, instead of replicating the code, relocate this function
> > to the common AML build.
> >
> > Sig
On 7/1/24 18:01, Nicholas Piggin wrote:
The 390x tag should be s390x.
Signed-off-by: Nicholas Piggin
---
.gitlab-ci.d/buildtest.yml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
On 7/1/24 22:40, Helge Deller wrote:
On 1/7/24 16:22, Peter Maydell wrote:
On Sun, 7 Jan 2024 at 07:20, Helge Deller wrote:
Update the TCI interpreter test matrix for big-endian hosts with
big- (hppa, hppa64) and little-endian (x86,x96-64) targets.
I used native ppc64 and hppa hosts for those
On 07/01/2024 18.01, Nicholas Piggin wrote:
The ppc64 and s390x tests were first marked skipIf GITLAB_CI by commit
c0c8687ef0f ("tests/avocado: disable BootLinuxPPC64 test in CI"), and
commit 0f26d94ec9e ("tests/acceptance: skip s390x_ccw_vrtio_tcg on
GitLab") due to being very heavy-weight for g
On 7/1/24 22:25, Mark Cave-Ayland wrote:
Declaration ROM binary images can be any arbitrary size, however if a host ROM
memory region is not aligned to qemu_target_page_size() then we fail the
"assert(!(iotlb & ~TARGET_PAGE_MASK))" check in tlb_set_page_full().
IIUC this isn't specific to NuBus
On 6/1/24 19:15, Samuel Tardieu wrote:
A SoC will not have a direct access to the NVIC embedded in its ARM
core. By aliasing the "num-prio-bits" property similarly to what is
done for the "num-irq" one, a SoC can easily configure it on its
armv7m instance.
Signed-off-by: Samuel Tardieu
Reviewed
writes:
> From: Ankit Agrawal
>
> NVIDIA GPU's support MIG (Mult-Instance GPUs) feature [1], which allows
> partitioning of the GPU device resources (including device memory) into
> several (upto 8) isolated instances. Each of the partitioned memory needs
> a dedicated NUMA node to operate. The
Hi Inès,
On 6/1/24 17:38, Inès Varhol wrote:
This patch adds a new STM32L4x5 SoC, it is necessary to add support for
the B-L475E-IOT01A board.
The implementation is derived from the STM32F405 SoC.
The implementation contains no peripherals, only memory regions are
implemented.
Tested-by: Philip
On 8/1/24 00:16, Bernhard Beschow wrote:
This is a follow-up on commit 89965db43cce "hw/isa/piix3: Avoid Xen-specific
variant of piix3_write_config()" which introduced
piix_intx_routing_notifier_xen(). This function is implemented in board code but
accesses the PCI configuration space of the PIIX
On 1/2/24 05:57, Richard Henderson wrote:
Work much harder to get alignment and mapping beyond the end
of the file correct. Both of which are excercised by our
test-mmap for alpha (8k pages) on any 4k page host.
Signed-off-by: Richard Henderson
---
linux-user/mmap.c | 156 +++
On 1/7/24 18:01, Nicholas Piggin wrote:
FreeBSD project provides qcow2 images that work well for testing QEMU.
Add pseries tests for HPT and Radix, KVM and TCG. This uses a short
term VM image, because FreeBSD has not set up long term builds for
ppc64 at present.
Other architectures could be add
Hi Nikita,
On 7/1/24 17:57, Nikita Ostrenkov wrote:
Signed-off-by: Nikita Ostrenkov
---
hw/arm/Kconfig| 3 +++
hw/arm/fsl-imx6.c | 25 ++
include/hw/arm/fsl-imx6.h | 44 ---
3 files changed, 51 insertions(+), 21 d
On Wed, 2024-01-03 at 17:33 +, Alex Bennée wrote:
> From: Daniel P. Berrangé
>
> The npcm7xx_pwn-test takes 3 & 1/2 minutes in a --enable-debug build.
> Bumping to 5 minutes will give more headroom.
>
> Signed-off-by: Daniel P. Berrangé
> Reviewed-by: Thomas Huth
> Message-ID: <20230717182
On Mon, 8 Jan 2024 at 11:03, Thomas Huth wrote:
>
> On 05/01/2024 20.11, Peter Maydell wrote:
> > https://gitlab.com/qemu-project/qemu/-/jobs/5871592479
> >
> > failed with
> >
> > $ htags -anT --tree-view=filetree -m qemu_init -t "Welcome to the QEMU
> > sourcecode"
> > htags: Negative exec line
Philippe Mathieu-Daudé writes:
> +Markus
>
> On 31/12/23 10:30, Avihai Horon wrote:
>> migration_channel_read_peek() calls qio_channel_readv_full() and handles
>> both cases of return value == 0 and return value < 0 the same way, by
>> calling error_setg() with errp. However, if return value < 0,
On 08/01/2024 12:01, Philippe Mathieu-Daudé wrote:
On 7/1/24 22:25, Mark Cave-Ayland wrote:
Declaration ROM binary images can be any arbitrary size, however if a host ROM
memory region is not aligned to qemu_target_page_size() then we fail the
"assert(!(iotlb & ~TARGET_PAGE_MASK))" check in tlb
Peter Xu writes:
> On Wed, Jan 03, 2024 at 12:05:29PM -0800, Steve Sistare wrote:
>> Migration of a guest in the suspended runstate is broken. The incoming
>> migration code automatically tries to wake the guest, which is wrong;
>> the guest should end migration in the same runstate it started.
On 1/7/24 18:05, Nicholas Piggin wrote:
is_prefix_insn_excp() loads the first word of the instruction address
which caused an exception, to determine whether or not it was prefixed
so the prefix bit can be set in [H]SRR1.
In case it was the instruction fetch itself that caused the exception,
the
make check-tcg fails on Fedora with:
vtimer.c:9:10: fatal error: inttypes.h: No such file or directory
Fedora has a minimal aarch64 cross-compiler, which satisfies the
configure checks, so it's chosen instead of the dockerized one.
There is no cross-version of inttypes.h, however.
Fix by usi
Respin of Gerd's series [*] using the LD/ST API.
v1 [*] cover:
When running qemu with edk2 efi firmware on aarch64 the efi
variable store in pflash can get corrupted. qemu not doing
proper block writes -- flush all or nothing to storage -- is
a hot candidate for being the root cause.
From: Gerd Hoffmann
Add an update buffer where all block updates are staged.
Flush or discard updates properly, so we should never see
half-completed block writes in pflash storage.
Drop a bunch of FIXME comments ;)
Signed-off-by: Gerd Hoffmann
Message-ID: <20240105135855.268064-3-kra...@redha
Similarly to commit c3d25271b2 ("hw/block/pflash_cfi02: Use the
ldst API in pflash_write") for CFI type 2, use the LD/ST API for
CFI type 1.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi01.c | 63 ++---
1 file changed, 8 insertions(+), 55 delet
Hi Ilya,
On 8/1/24 13:50, Ilya Leoshkevich wrote:
make check-tcg fails on Fedora with:
vtimer.c:9:10: fatal error: inttypes.h: No such file or directory
Fedora has a minimal aarch64 cross-compiler, which satisfies the
configure checks, so it's chosen instead of the dockerized one.
There i
On Mon, 8 Jan 2024 at 12:34, Peter Maydell wrote:
>
> On Mon, 8 Jan 2024 at 11:03, Thomas Huth wrote:
> >
> > On 05/01/2024 20.11, Peter Maydell wrote:
> > > https://gitlab.com/qemu-project/qemu/-/jobs/5871592479
> > >
> > > failed with
> > >
> > > $ htags -anT --tree-view=filetree -m qemu_init -
Hi! Thanks! I'll send a new version of this patch.
But what about fsl imx7? Should it also have PCIE_DEVICES?
пн, 8 янв. 2024 г. в 15:20, Philippe Mathieu-Daudé :
> Hi Nikita,
>
> On 7/1/24 17:57, Nikita Ostrenkov wrote:
> > Signed-off-by: Nikita Ostrenkov
> > ---
> > hw/arm/Kconfig
Hi Gerd,
On 8/1/24 13:53, Philippe Mathieu-Daudé wrote:
From: Gerd Hoffmann
Add an update buffer where all block updates are staged.
Flush or discard updates properly, so we should never see
half-completed block writes in pflash storage.
Drop a bunch of FIXME comments ;)
Signed-off-by: Gerd
On Mon, 2024-01-08 at 13:56 +0100, Philippe Mathieu-Daudé wrote:
> Hi Ilya,
>
> On 8/1/24 13:50, Ilya Leoshkevich wrote:
> > make check-tcg fails on Fedora with:
> >
> > vtimer.c:9:10: fatal error: inttypes.h: No such file or
> > directory
> >
> > Fedora has a minimal aarch64 cross-compiler
On Fri, 5 Jan 2024 at 19:32, Michael Tokarev wrote:
>
> The following changes since commit 0c1eccd368af8805ec0fb11e6cf25d0684d37328:
>
> Merge tag 'hw-cpus-20240105' of https://github.com/philmd/qemu into staging
> (2024-01-05 16:08:58 +)
>
> are available in the Git repository at:
>
> ht
On Sat, 6 Jan 2024 at 02:25, Song Gao wrote:
>
> The following changes since commit 0c1eccd368af8805ec0fb11e6cf25d0684d37328:
>
> Merge tag 'hw-cpus-20240105' of https://github.com/philmd/qemu into staging
> (2024-01-05 16:08:58 +)
>
> are available in the Git repository at:
>
> https://g
On Mon, 8 Jan 2024 at 07:34, Cédric Le Goater wrote:
>
> The following changes since commit 0c1eccd368af8805ec0fb11e6cf25d0684d37328:
>
> Merge tag 'hw-cpus-20240105' of https://github.com/philmd/qemu into staging
> (2024-01-05 16:08:58 +)
>
> are available in the Git repository at:
>
> h
On 8/1/24 13:46, Mark Cave-Ayland wrote:
On 08/01/2024 12:01, Philippe Mathieu-Daudé wrote:
On 7/1/24 22:25, Mark Cave-Ayland wrote:
Declaration ROM binary images can be any arbitrary size, however if a
host ROM
memory region is not aligned to qemu_target_page_size() then we fail the
"assert(
(+Thomas)
On 8/1/24 13:58, Nikita Ostrenkov wrote:
Hi! Thanks! I'll send a new version of this patch.
But what about fsl imx7? Should it also have PCIE_DEVICES?
Yeah I think so, we missed this in commit 02047622b7 ("hw/arm:
Express dependencies of the remaining IMX boards with Kconfig").
п
On 8/1/24 10:47, Pierrick Bouvier wrote:
On 1/2/24 05:57, Richard Henderson wrote:
Use qemu_real_host_page_size instead.
Signed-off-by: Richard Henderson
---
linux-user/mmap.c | 66 +++
1 file changed, 33 insertions(+), 33 deletions(-)
diff --git
On Fri, Dec 08, 2023 at 12:07:22PM +, Conor Dooley wrote:
> From: Conor Dooley
>
> A few months ago I submitted a patch to various lists, deprecating
> "riscv,isa" with a lengthy commit message [0] that is now commit
> aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa") in the Linux
> ke
On Mon, Dec 18, 2023 at 02:37:55PM +1000, Alistair Francis wrote:
...
> > +void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
> > +{
> > +const size_t maxlen = sizeof("rv128i");
> > +g_autofree char *isa_base = g_new(char, maxlen);
> > +g_autofree char *riscv_isa;
> > +
This commit adds a new B-L475E-IOT01A board using the STM32L475VG SoC
as well as a dedicated documentation file.
The implementation is derived from the Netduino Plus 2 machine.
There are no peripherals implemented yet, only memory regions.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe M
This patch adds a new STM32L4x5 SoC, it is necessary to add support for
the B-L475E-IOT01A board.
The implementation is derived from the STM32F405 SoC.
The implementation contains no peripherals, only memory regions are
implemented.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-
This patch adds a new STM32L4x5 SoC, it is necessary to add support for
the B-L475E-IOT01A board.
The implementation is derived from the STM32F405 SoC and NetduinoPlus2
board.
The implementation contains no peripherals, only memory regions are
implemented.
Changes from v5 to v6:
- in `stm32l4x5_so
Signed-off-by: Nikita Ostrenkov
---
hw/arm/Kconfig| 2 ++
hw/arm/fsl-imx6.c | 25 ++
include/hw/arm/fsl-imx6.h | 44 ---
3 files changed, 50 insertions(+), 21 deletions(-)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
in
Peter Xu writes:
> On Wed, Jun 07, 2023 at 10:27:15AM +0200, Juan Quintela wrote:
>> Fabiano Rosas wrote:
>> > We've found the source of flakiness in this test, so re-enable it.
>> >
>> > Signed-off-by: Fabiano Rosas
>> > ---
>> > tests/qtest/migration-test.c | 10 ++
>> > 1 file chang
On 1/7/24 18:01, Nicholas Piggin wrote:
The powernv and pseries machines both provide hypervisor facilities
that are supported by KVM. This is a large and complicated set of
features that don't get much system-level testing in ppc tests.
Add a new test case for these which runs QEMU KVM inside t
From: Helge Deller
The physical hardware allows DIMMs of 4 MB size and above, allowing up
to 3840 MB of memory, but is restricted by setup code to 3 GB.
Increase the limit to allow up to the maximum amount of memory.
Btw. the memory area from 0xf000. to 0x. is reserved by
the archite
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