Zhenzhong,
How about what's below instead ?
Thanks,
C.
I will resend the build fix with the proposal below since it addresses
Phil's concerns.
Thanks,
C.
--- a/hw/ppc/spapr_pci_vfio.c
+++ b/hw/ppc/spapr_pci_vfio.c
@@ -26,10 +26,12 @@
#include "hw/pci/pci_device.h"
#include "hw/vf
On 11/23/23 19:42, Cédric Le Goater wrote:
On 11/23/23 10:31, Harsh Prateek Bora wrote:
On 11/23/23 14:20, Cédric Le Goater wrote:
On 11/23/23 06:57, Harsh Prateek Bora wrote:
spapr_irq_init currently uses existing macro SPAPR_XIRQ_BASE to
refer to
the range of CPU IPIs during initializa
>-Original Message-
>From: Cédric Le Goater
>Sent: Friday, November 24, 2023 3:59 PM
>Subject: Re: [PATCH] hw/ppc: Improve build for PPC VFIO
>
>Zhenzhong,
>
>> How about what's below instead ?
>>
>>
>> Thanks,
>>
>> C.
>
>I will resend the build fix with the proposal below since it add
When the legacy and iommufd backends were introduced, a set of common
vfio-pci routines were exported in pci.c for both backends to use :
vfio_pci_pre_reset
vfio_pci_get_pci_hot_reset_info
vfio_pci_host_match
vfio_pci_post_reset
This introduced a build failure on PPC when --without-defaul
On 11/24/23 09:01, Harsh Prateek Bora wrote:
On 11/23/23 19:42, Cédric Le Goater wrote:
On 11/23/23 10:31, Harsh Prateek Bora wrote:
On 11/23/23 14:20, Cédric Le Goater wrote:
On 11/23/23 06:57, Harsh Prateek Bora wrote:
spapr_irq_init currently uses existing macro SPAPR_XIRQ_BASE to refe
Ping !!
Since [1] series had merged into master three weeks ago,
I ping this series again.
[1]:
https://lore.kernel.org/all/20231103062332.2413724-1-gaos...@loongson.cn/
Thanks.
Song Gao
在 2023/11/13 下午4:06, gaosong 写道:
Ping !
在 2023/10/25 下午5:29, Song Gao 写道:
Hi, Peter!
This series ad
On 11/21/23 20:09, Glenn Miles wrote:
Create a new powernv machine type, powernv10-rainier, that
will contain rainier-specific devices.
Signed-off-by: Glenn Miles
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
Changes from previous version:
- Formatting changes
- Capitalized "Rain
On 11/21/23 20:09, Glenn Miles wrote:
For power10-rainier, a pca9552 device is used for PCIe slot hotplug
power control by the Power Hypervisor code. The code expects that
some time after it enables power to a PCIe slot by asserting one of
the pca9552 GPIO pins 0-4, it should see a "power good"
On 11/21/23 20:09, Glenn Miles wrote:
For powernv10-rainier, the Power Hypervisor code expects to see a
pca9554 device connected to the 3rd PNV I2C engine on port 1 at I2C
address 0x25 (or left-justified address of 0x4A). This is used by
the hypervisor code to detect if a "Cable Card" is present
On 11/21/23 20:09, Glenn Miles wrote:
Specs are available here:
https://www.nxp.com/docs/en/data-sheet/PCA9554_9554A.pdf
This is a simple model supporting the basic registers for GPIO
mode. The device also supports an interrupt output line but the
model does not yet support this.
Reviewe
On 11/21/23 20:09, Glenn Miles wrote:
This series of patches includes support, tests and fixes for
adding PCA9552 and PCA9554 I2C devices to the powernv10 chip.
The PCA9552 device is used for PCIe slot hotplug power control
and monitoring, while the PCA9554 device is used for presence
detection
> On 23-Nov-2023, at 8:08 PM, Philippe Mathieu-Daudé wrote:
>
> The QOM API is lower level than the QDev one. When an instance is
> QDev and setting the property can not fail (using &error_abort),
> prefer qdev_prop_set_bit() over object_property_set_bool().
>
> Mechanical transformation usin
On Thu, Nov 23, 2023 at 05:39:18PM -0500, Michael S. Tsirkin wrote:
> On Thu, Nov 23, 2023 at 05:58:45PM +, Daniel P. Berrangé wrote:
> > The license of a code generation tool itself is usually considered
> > to be not a factor in the license of its output.
>
> Really? I would find it very sur
On Thu, Nov 23, 2023 at 03:51:07PM -0300, Daniel Henrique Barboza wrote:
> We'll add a new bare CPU type that won't have any default priv_ver. This
> means that the CPU will default to priv_ver = 0, i.e. 1.10.0.
>
> At the same we'll allow these CPUs to enable extensions at will, but
> then, if th
On Thu, Nov 23, 2023 at 03:51:14PM -0300, Daniel Henrique Barboza wrote:
> The TCG emulation implements all the extensions described in the
> RVA22U64 profile, both mandatory and optional. The mandatory extensions
> will be enabled via the profile flag. We'll leave the optional
> extensions to be e
On Fri, Nov 24, 2023 at 09:06:29AM +, Daniel P. Berrangé wrote:
> On Thu, Nov 23, 2023 at 05:39:18PM -0500, Michael S. Tsirkin wrote:
> > On Thu, Nov 23, 2023 at 05:58:45PM +, Daniel P. Berrangé wrote:
> > > The license of a code generation tool itself is usually considered
> > > to be not
Am 23.11.2023 um 18:16 hat Daniel P. Berrangé geschrieben:
> > Suggested-by is also common.
> >
> > As long as we are here, let's document Fixes: and Cc: ?
>
> The submitting-a-patch doc covers more general commit message information.
> I think this doc just ought to focus on tags that identify h
On Thu, Nov 23, 2023 at 04:15:26PM -0300, Daniel Henrique Barboza wrote:
> 'svade' is a RVA22S64 profile requirement, a profile we're going to add
> shortly. It is a named feature (i.e. not a formal extension, not defined
> in riscv,isa DT at this moment) defined in [1] as:
>
> "Page-fault excepti
On Thu, Nov 23, 2023 at 04:15:27PM -0300, Daniel Henrique Barboza wrote:
> Some profiles, like RVA22S64, has a priv_spec requirement.
>
> Make this requirement explicit for all profiles. We'll validate this
> requirement finalize() time and, in case the user chooses an
> incompatible priv_spec whi
(Cc'ing QAPI maintainer)
On 24/11/23 02:53, Daniel Hoffman wrote:
This was the only failure preventing `make check` from passing with sanitizers
enabled on my configuration.
IIUC this is due to visit_start_list() which expects a NULL list,
see qapi/qapi-visit-core.c:
bool visit_start_list(Vis
On 24/11/23 09:06, Cédric Le Goater wrote:
When the legacy and iommufd backends were introduced, a set of common
vfio-pci routines were exported in pci.c for both backends to use :
vfio_pci_pre_reset
vfio_pci_get_pci_hot_reset_info
vfio_pci_host_match
vfio_pci_post_reset
This introd
This part of the patchset creates a common pervasive chiplet model where it
houses the common units of a chiplets.
The chiplet control unit is common across chiplets and this commit implements
the pervasive chiplet model with chiplet control registers.
Signed-off-by: Chalapathi V
---
include/hw
This part of the patchset connects the nest1 chiplet model to p10 chip.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_chip.h | 2 ++
hw/ppc/pnv.c | 14 ++
2 files changed, 16 insertions(+)
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index 0a
Hello,
Thank you for the review and suggestions on V4.
The suggestions and changes requested in V4 are considered and incorporated in
V5.
In this version, couple of powerbus scom registers are modelled.
Hence the new qom-tree is as below.
(qemu) info qom-tree
/machine (powernv10-machine)
/chi
The nest1 chiplet handle the high speed i/o traffic over PCIe and others.
The nest1 chiplet consists of PowerBus Fabric controller,
nest Memory Management Unit, chiplet control unit and more.
This commit creates a nest1 chiplet model and initialize and realize the
pervasive chiplet model where chi
Am 24.11.2023 um 00:53 hat Michael S. Tsirkin geschrieben:
> On Thu, Nov 23, 2023 at 05:46:16PM +, Daniel P. Berrangé wrote:
> > On Thu, Nov 23, 2023 at 12:57:42PM +, Alex Bennée wrote:
> > > Daniel P. Berrangé writes:
> > >
> > > > There has been an explosion of interest in so called "AI
Daniel P. Berrangé writes:
> On Thu, Nov 23, 2023 at 05:39:18PM -0500, Michael S. Tsirkin wrote:
>> On Thu, Nov 23, 2023 at 05:58:45PM +, Daniel P. Berrangé wrote:
>> > The license of a code generation tool itself is usually considered
>> > to be not a factor in the license of its output.
>>
Peter Maydell writes:
> On Thu, 9 Nov 2023 at 20:59, Philippe Mathieu-Daudé wrote:
>>
>> Hi Peter,
>>
>> On 9/11/23 20:29, Peter Maydell wrote:
>> > On Thu, 9 Nov 2023 at 19:28, Philippe Mathieu-Daudé
>> > wrote:
>> >>
>> >> Missing review: #10
>> >>
>> >> Hi,
>> >>
>> >> This series add suppo
Am 23.11.2023 um 15:56 hat Manos Pitsidianakis geschrieben:
> On Thu, 23 Nov 2023 16:35, "Michael S. Tsirkin" wrote:
> > On Thu, Nov 23, 2023 at 11:40:26AM +, Daniel P. Berrangé wrote:
> > > There has been an explosion of interest in so called "AI" (LLM)
> > > code generators in the past year
On Fri, Nov 24, 2023 at 10:21:17AM +, Alex Bennée wrote:
> LLM's are just a tool like a compiler (albeit with spookier different
> internals).
We already generally don't accept compiler output in patches since
it is not source code by the definition of GPL.
--
MST
Kevin Wolf writes:
> Am 24.11.2023 um 00:53 hat Michael S. Tsirkin geschrieben:
>> On Thu, Nov 23, 2023 at 05:46:16PM +, Daniel P. Berrangé wrote:
>> > On Thu, Nov 23, 2023 at 12:57:42PM +, Alex Bennée wrote:
>> > > Daniel P. Berrangé writes:
>> > >
>> > > > +The QEMU maintainers thus
On Fri, Nov 24, 2023 at 11:25:55AM +0100, Kevin Wolf wrote:
> > - Automated codegen tool must be idempotent.
> > - Automated codegen tool must not use statistical modelling.
>
> How are these definitions related to your ability to sign the DCO?
Not only that - while the question of whether code g
On Fri Nov 24, 2023 at 6:36 PM AEST, Cédric Le Goater wrote:
> On 11/21/23 20:09, Glenn Miles wrote:
> > This series of patches includes support, tests and fixes for
> > adding PCA9552 and PCA9554 I2C devices to the powernv10 chip.
> >
> > The PCA9552 device is used for PCIe slot hotplug power con
Hi Shaoqin,
On 11/17/23 07:08, Shaoqin Huang wrote:
> The KVM_ARM_VCPU_PMU_V3_FILTER provide the ability to let the VMM decide
> which PMU events are provided to the guest. Add a new option
> `pmu-filter` as -accel sub-option to set the PMU Event Filtering.
you remind the reader the default policy
On Fri, Nov 24, 2023 at 10:33:49AM +, Alex Bennée wrote:
> That probably means we can never use even open source LLMs to generate
> code for QEMU because while the source data is all open source it won't
> necessarily be GPL compatible.
I would probably wait until the dust settles before we st
On Fri, 24 Nov 2023 at 10:42, Michael S. Tsirkin wrote:
>
> On Fri, Nov 24, 2023 at 10:33:49AM +, Alex Bennée wrote:
> > That probably means we can never use even open source LLMs to generate
> > code for QEMU because while the source data is all open source it won't
> > necessarily be GPL com
On Fri, 24 Nov 2023 12:25, Kevin Wolf wrote:
Am 23.11.2023 um 15:56 hat Manos Pitsidianakis geschrieben:
On Thu, 23 Nov 2023 16:35, "Michael S. Tsirkin" wrote:
> On Thu, Nov 23, 2023 at 11:40:26AM +, Daniel P. Berrangé wrote:
> > There has been an explosion of interest in so called "AI" (L
In PVH dom0, it uses the linux local interrupt mechanism,
when it allocs irq for a gsi, it is dynamic, and follow
the principle of applying first, distributing first. And
if you debug the kernel codes, you will find the irq
number is alloced from small to large, but the applying
gsi number is not,
Hi All,
This patch is the v2 of the implementation of passthrough when dom0 is PVH on
Xen.
Issues we encountered:
1. failed to map pirq for gsi
Problem: qemu will call xc_physdev_map_pirq() to map a passthrough device’s gsi
to pirq in function
xen_pt_realize(). But failed.
Reason: According to
Simon Ser writes:
Hello Simon,
> On Wednesday, November 22nd, 2023 at 13:49, Javier Martinez Canillas
> wrote:
>
>> Any objections to merge the series ?
>
> No objections from me :)
>
Perfect, I'll merge this series then to unblock the mutter MR. Thanks again!
--
Best regards,
Javier Marti
On Fri, Nov 24, 2023 at 10:43:05AM +, Peter Maydell wrote:
> On Fri, 24 Nov 2023 at 10:42, Michael S. Tsirkin wrote:
> >
> > On Fri, Nov 24, 2023 at 10:33:49AM +, Alex Bennée wrote:
> > > That probably means we can never use even open source LLMs to generate
> > > code for QEMU because whi
On 11/24/23 11:39, Nicholas Piggin wrote:
On Fri Nov 24, 2023 at 6:36 PM AEST, Cédric Le Goater wrote:
On 11/21/23 20:09, Glenn Miles wrote:
This series of patches includes support, tests and fixes for
adding PCA9552 and PCA9554 I2C devices to the powernv10 chip.
The PCA9552 device is used for
On 23/11/23, Samuel Tardieu wrote:
> This file is the only one involved in the compilation process which
> still uses the /bin/bash path.
>
> Signed-off-by: Samuel Tardieu
> ---
> target/hexagon/idef-parser/prepare | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/
On 23/11/23 18:33, Michael S. Tsirkin wrote:
On Thu, Nov 23, 2023 at 05:16:45PM +, Daniel P. Berrangé wrote:
On Thu, Nov 23, 2023 at 09:25:13AM -0500, Michael S. Tsirkin wrote:
On Thu, Nov 23, 2023 at 11:40:25AM +, Daniel P. Berrangé wrote:
Currently we have a short paragraph saying th
On Fri Nov 24, 2023 at 8:15 PM AEST, Chalapathi V wrote:
> This part of the patchset creates a common pervasive chiplet model where it
> houses the common units of a chiplets.
>
> The chiplet control unit is common across chiplets and this commit implements
> the pervasive chiplet model with chiple
On 21/11/23 23:26, del...@kernel.org wrote:
From: Helge Deller
SeaBIOS-hppa version 13 fixes a system reboot crash as reported
in https://gitlab.com/qemu-project/qemu/-/issues/1991
Signed-off-by: Helge Deller
---
pc-bios/hppa-firmware.img | Bin 681332 -> 681388 bytes
roms/seabios-hppa
For this and actually the last patch too, it would be good to mention
(possibly in a header comment in the file too) what actual functionality
is being provided/modeled. It looks like it's just modeling behaviour of
reads and writes for some registers.
Oh, and sorry I didn't follow development and
On Fri, Nov 24, 2023 at 12:11:30PM +0100, Philippe Mathieu-Daudé wrote:
> On 23/11/23 18:33, Michael S. Tsirkin wrote:
> > On Thu, Nov 23, 2023 at 05:16:45PM +, Daniel P. Berrangé wrote:
> > > On Thu, Nov 23, 2023 at 09:25:13AM -0500, Michael S. Tsirkin wrote:
> > > > On Thu, Nov 23, 2023 at 11
On Fri Nov 24, 2023 at 8:15 PM AEST, Chalapathi V wrote:
> This part of the patchset connects the nest1 chiplet model to p10 chip.
Seems fine to me. Should it just be squashed into patch 2?
Thanks,
Nick
>
> Signed-off-by: Chalapathi V
> ---
> include/hw/ppc/pnv_chip.h | 2 ++
> hw/ppc/pnv.c
blk_bs() may return NULL, which will be dereferenced without a check in
bdrv_commit().
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Signed-off-by: Dmitry Frolov
---
block/monitor/block-hmp-cmds.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/blo
On 23/11/23 05:42, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/arm/kvm_arm.h | 2 --
target/arm/kvm.c | 2 +-
2 files changed, 1 insertion(+), 3 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 23/11/23 05:42, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/arm/kvm_arm.h | 9 -
target/arm/kvm.c | 22 ++
target/arm/kvm64.c | 15 ---
3 files changed, 22 insertions(+), 24 deletions(-)
Reviewed-by: Philippe Mathi
On Fri, Nov 24, 2023 at 10:43:05AM +, Peter Maydell wrote:
> On Fri, 24 Nov 2023 at 10:42, Michael S. Tsirkin wrote:
> >
> > On Fri, Nov 24, 2023 at 10:33:49AM +, Alex Bennée wrote:
> > > That probably means we can never use even open source LLMs to generate
> > > code for QEMU because whi
On 23/11/23 05:42, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/arm/kvm_arm.h | 22
target/arm/kvm.c | 265 +++
target/arm/kvm64.c | 254 -
3 files changed, 265 insertions(+),
On Fri, Nov 24, 2023 at 11:37:15AM +, Daniel P. Berrangé wrote:
> On Fri, Nov 24, 2023 at 10:43:05AM +, Peter Maydell wrote:
> > On Fri, 24 Nov 2023 at 10:42, Michael S. Tsirkin wrote:
> > >
> > > On Fri, Nov 24, 2023 at 10:33:49AM +, Alex Bennée wrote:
> > > > That probably means we c
On Fri, Nov 24, 2023 at 06:39:21AM -0500, Michael S. Tsirkin wrote:
> On Fri, Nov 24, 2023 at 11:37:15AM +, Daniel P. Berrangé wrote:
> > On Fri, Nov 24, 2023 at 10:43:05AM +, Peter Maydell wrote:
> > > On Fri, 24 Nov 2023 at 10:42, Michael S. Tsirkin wrote:
> > > >
> > > > On Fri, Nov 24,
On Fri Nov 24, 2023 at 5:16 PM AEST, Cédric Le Goater wrote:
> On 11/24/23 07:39, Nicholas Piggin wrote:
[snip]
> > +static void pnv_chiptod_xscom_write(void *opaque, hwaddr addr,
> > +uint64_t val, unsigned size,
> > +bool i
Hi Richard,
On 23/11/23 05:42, Richard Henderson wrote:
Since kvm32.c was removed, there is no need to keep them separate.
This will allow more symbols to be unexported.
Signed-off-by: Richard Henderson
---
target/arm/kvm.c | 789 +++
target/arm/kvm
On Fri, Nov 24, 2023 at 10:21:17AM +, Alex Bennée wrote:
> Daniel P. Berrangé writes:
>
> > On Thu, Nov 23, 2023 at 05:39:18PM -0500, Michael S. Tsirkin wrote:
> >> On Thu, Nov 23, 2023 at 05:58:45PM +, Daniel P. Berrangé wrote:
> >> > The license of a code generation tool itself is usual
On 11/24/23 06:57, Andrew Jones wrote:
On Thu, Nov 23, 2023 at 04:15:27PM -0300, Daniel Henrique Barboza wrote:
Some profiles, like RVA22S64, has a priv_spec requirement.
Make this requirement explicit for all profiles. We'll validate this
requirement finalize() time and, in case the user ch
On 23/11/23 05:42, Richard Henderson wrote:
There is no need to do this in kvm_arch_init_vcpu per vcpu.
Inline kvm_arm_init_serror_injection rather than keep separate.
Signed-off-by: Richard Henderson
---
target/arm/kvm_arm.h | 8
target/arm/kvm.c | 13 -
2 files c
On 23/11/23 05:42, Richard Henderson wrote:
There is no need to do this in kvm_arch_init_vcpu per vcpu.
Inline kvm_arm_init_serror_injection rather than keep separate.
Signed-off-by: Richard Henderson
---
target/arm/kvm_arm.h | 8
target/arm/kvm.c | 13 -
2 files c
On 11/24/23 06:23, Andrew Jones wrote:
On Thu, Nov 23, 2023 at 03:51:07PM -0300, Daniel Henrique Barboza wrote:
We'll add a new bare CPU type that won't have any default priv_ver. This
means that the CPU will default to priv_ver = 0, i.e. 1.10.0.
At the same we'll allow these CPUs to enable
From: Fam Zheng
If the text description file is larger than DESC_SIZE, we force the last
byte in the buffer to be 0 and write it out.
This results in a corruption.
Try to allocate a big buffer in this case.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1923
Signed-off-by: Fam Zheng
On 23/11/23 05:42, Richard Henderson wrote:
From: Chao Du
The KVM_CAP_SET_GUEST_DEBUG is probed during kvm_init().
gdbserver will fail to start if the CAP is not supported.
So no need to make another probe here, like other targets.
Signed-off-by: Chao Du
Reviewed-by: Richard Henderson
Messag
On Tue, 21 Nov 2023 22:10:28 +
Volodymyr Babchuk wrote:
Probably typo in 'subj'
mc->max_cpus
is limit on maximum supported vCPUs and it shouldn't be set
by xen_arm_init()
patch itself though does the right thing by setting it
in xen_arm_machine_class_init()
Also below explanation, whil
On 23/11/23 05:42, Richard Henderson wrote:
Drop fprintfs and actually use the return values in the callers.
Signed-off-by: Richard Henderson
---
target/arm/kvm_arm.h | 20
target/arm/kvm.c | 23 ++-
2 files changed, 6 insertions(+), 37 deletions
On 23/11/23 05:41, Richard Henderson wrote:
This is primarily concerned with merging kvm64.c with kvm.c
and then unexporting everything that is not required outside.
r~
Chao Du (1):
target/arm: kvm64: remove a redundant KVM_CAP_SET_GUEST_DEBUG probe
Richard Henderson (20):
accel/kvm: Mak
It seems that comments to transitional/non-transitional devices are
mixed up.
Signed-off-by: Dmitry Frolov
---
include/hw/virtio/virtio-pci.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/hw/virtio/virtio-pci.h b/include/hw/virtio/virtio-pci.h
index 5a3f182f99..
On 11/24/23 12:40, Nicholas Piggin wrote:
On Fri Nov 24, 2023 at 5:16 PM AEST, Cédric Le Goater wrote:
On 11/24/23 07:39, Nicholas Piggin wrote:
[snip]
+static void pnv_chiptod_xscom_write(void *opaque, hwaddr addr,
+uint64_t val, unsigned size,
+
On 11/24/23 12:26, Nicholas Piggin wrote:
For this and actually the last patch too, it would be good to mention
(possibly in a header comment in the file too) what actual functionality
is being provided/modeled. It looks like it's just modeling behaviour of
reads and writes for some registers.
O
On 11/24/23 12:28, Nicholas Piggin wrote:
On Fri Nov 24, 2023 at 8:15 PM AEST, Chalapathi V wrote:
This part of the patchset connects the nest1 chiplet model to p10 chip.
Seems fine to me. Should it just be squashed into patch 2?
It is better to keep the model a part from the wiring because
On Tue, 21 Nov 2023 22:10:28 +
Volodymyr Babchuk wrote:
> From: Oleksandr Tyshchenko
>
> The bridge is needed for virtio-pci support, as QEMU can emulate the
> whole bridge with any virtio-pci devices connected to it.
>
> This patch provides a flexible way to configure PCIe brige resources
On 11/24/23 11:10, Philippe Mathieu-Daudé wrote:
On 24/11/23 09:06, Cédric Le Goater wrote:
When the legacy and iommufd backends were introduced, a set of common
vfio-pci routines were exported in pci.c for both backends to use :
vfio_pci_pre_reset
vfio_pci_get_pci_hot_reset_info
vfio_
On 22/11/23 11:38, Daniel P. Berrangé wrote:
On Wed, Nov 22, 2023 at 02:31:29PM +0400, Marc-André Lureau wrote:
Hi
On Thu, Nov 9, 2023 at 11:30 PM Philippe Mathieu-Daudé
wrote:
If the UART back-end chardev doesn't drain data as fast as stdout
does or blocks, buffer in the TX FIFO to try agai
On Fri Nov 24, 2023 at 10:26 PM AEST, Cédric Le Goater wrote:
> On 11/24/23 12:28, Nicholas Piggin wrote:
> > On Fri Nov 24, 2023 at 8:15 PM AEST, Chalapathi V wrote:
> >> This part of the patchset connects the nest1 chiplet model to p10 chip.
> >
> > Seems fine to me. Should it just be squashed i
On 11/24/23 07:39, Nicholas Piggin wrote:
One of the functions of the ChipTOD is to transfer TOD to the Core
(aka PC - Pervasive Core) timebase facility.
The ChipTOD can be programmed with a target address to send the TOD
value to. The hardware implementation seems to perform this by
sending the
Volodymyr Babchuk writes:
> Hi,
>
> Volodymyr Babchuk writes:
>
>> Hi Stefano,
>>
>> Stefano Stabellini writes:
>>
>>> On Wed, 22 Nov 2023, David Woodhouse wrote:
On Wed, 2023-11-22 at 15:09 -0800, Stefano Stabellini wrote:
> On Wed, 22 Nov 2023, David Woodhouse wrote:
> > On Wed
On Fri Nov 24, 2023 at 10:19 PM AEST, Cédric Le Goater wrote:
> On 11/24/23 12:26, Nicholas Piggin wrote:
> > For this and actually the last patch too, it would be good to mention
> > (possibly in a header comment in the file too) what actual functionality
> > is being provided/modeled. It looks li
Am 24.11.2023 um 12:30 hat Dmitry Frolov geschrieben:
> blk_bs() may return NULL, which will be dereferenced without a check in
> bdrv_commit().
>
> Found by Linux Verification Center (linuxtesting.org) with SVACE.
>
> Signed-off-by: Dmitry Frolov
Do you have a reproducer for a crash?
As far a
On Fri, 17 Nov 2023 08:17:02 +0100
Philippe Mathieu-Daudé wrote:
> Both 'netduinoplus2' and 'olimex-stm32-h405' machines ignore the
> CPU type requested by the command line. This might confuse users,
> since the following will create a machine with a Cortex-M4 CPU:
>
> $ qemu-system-aarch64 -M
Yuan Liu writes:
> when starting multifd live migration, if the compression method is
> enabled, compression method can be accelerated using accelerators.
>
> Signed-off-by: Yuan Liu
> Reviewed-by: Nanhai Zou
Reviewed-by: Fabiano Rosas
Hi Igor,
On 24/11/23 14:13, Igor Mammedov wrote:
On Fri, 17 Nov 2023 08:17:02 +0100
Philippe Mathieu-Daudé wrote:
Both 'netduinoplus2' and 'olimex-stm32-h405' machines ignore the
CPU type requested by the command line. This might confuse users,
since the following will create a machine with a
On Wed, 15 Nov 2023 17:18:53 +
Thierry Escande wrote:
> This patch removes the unused field use_acpi_hotplug_bridge from the
> ICH9LPCPMRegs structure as it is now part of AcpiPciHpState.
>
> Hotplug fields have been removed from piix4 state structure by commit
> 6536e427ce49 (pcihp: move fi
Hi,
I just did an audit of QDev properties from different
models sharing the same name, but of different types
(as of v8.2.0-rc1).
Nothing wrong, but some having the same meaning could
use the same type :)
Just sharing:
---
2 addr
hw/core/generic-loader.c:183:DEFINE_PROP_UINT64("addr",
On Wed, 15 Nov 2023 17:18:54 +
Thierry Escande wrote:
> This patch initializes use_acpi_root_pci_hotplug to true and enables
> device PCI hotplug on q35 machine by default.
>
> Signed-off-by: Thierry Escande
> ---
> hw/acpi/ich9.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/h
On Wed, 15 Nov 2023 17:18:54 +
Thierry Escande wrote:
> This patch initializes use_acpi_root_pci_hotplug to true and enables
> device PCI hotplug on q35 machine by default.
>
> Signed-off-by: Thierry Escande
> ---
> hw/acpi/ich9.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/h
Philippe Mathieu-Daudé writes:
> (Cc'ing QAPI maintainer)
>
> On 24/11/23 02:53, Daniel Hoffman wrote:
>> This was the only failure preventing `make check` from passing with
>> sanitizers
>> enabled on my configuration.
>
> IIUC this is due to visit_start_list() which expects a NULL list,
> see
On 11/24/23 08:55, Daniel Henrique Barboza wrote:
On 11/24/23 06:23, Andrew Jones wrote:
On Thu, Nov 23, 2023 at 03:51:07PM -0300, Daniel Henrique Barboza wrote:
We'll add a new bare CPU type that won't have any default priv_ver. This
means that the CPU will default to priv_ver = 0, i.e. 1
From: Shiju Jose
CXL spec 3.0 section 8.2.9.6 describes optional device specific features.
CXL devices supports features with changeable attributes.
Get Supported Features retrieves the list of supported device specific
features. The settings of a feature can be retrieved using Get Feature and
op
From: Shiju Jose
CXL spec 3.1 section 8.2.9.9.11.2 describes the DDR5 Error Check Scrub (ECS)
control feature.
The Error Check Scrub (ECS) is a feature defined in JEDEC DDR5 SDRAM
Specification (JESD79-5) and allows the DRAM to internally read, correct
single-bit errors, and write back corrected
From: Shiju Jose
CXL spec 3.1 section 8.2.9.9.11.1 describes the device patrol scrub control
feature. The device patrol scrub proactively locates and makes corrections
to errors in regular cycle. The patrol scrub control allows the request to
configure patrol scrub input configurations.
The patr
From: Shiju Jose
Add support for the feature commands, device patrol scrub control and
DDR5 ECS control features.
CXL spec 3.0 section 8.2.9.6 describes optional device specific features.
CXL spec 3.1 section 8.2.9.9.11.1 describes the device patrol scrub control
feature.
CXL spec 3.1 section 8.
On Wed, 15 Nov 2023 17:18:53 +
Thierry Escande wrote:
> Hi,
>
> This series fixes acpi_hotplug_bridge accessor names, adds new accessors
> for acpi-root-pci-hotplug property, and enables root PCI hotplug by
> default for Q35 machine.
hotplug on Q35 hostbridge is not implemented intentionall
Daniel, please have a look at Kevin's patch:
Subject: [PATCH for-8.2 1/2] qdev: Fix crash in array property getter
Date: Tue, 21 Nov 2023 18:34:15 +0100 (2 days, 20 hours, 26 minutes ago)
Message-ID: <20231121173416.346610-2-kw...@redhat.com>
https://lore.kernel.org/qemu-devel/2023
On 24.11.2023 16:06, Kevin Wolf wrote:
Am 24.11.2023 um 12:30 hat Dmitry Frolov geschrieben:
blk_bs() may return NULL, which will be dereferenced without a check in
bdrv_commit().
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Signed-off-by: Dmitry Frolov
Do you have a
On Mon, 13 Nov 2023 20:12:30 +
Salil Mehta wrote:
> CPU ctrl-dev MMIO region length could be used in ACPI GED and various other
> architecture specific places. Move ACPI_CPU_HOTPLUG_REG_LEN macro to more
> appropriate common header file.
>
> Signed-off-by: Salil Mehta
> Reviewed-by: Alex Be
From: Yihuan Pan
Replaces TABS with spaces to ensure have a consistent coding
style with an indentation of 4 spaces in the SH4 subsystem.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/376
Signed-off-by: Yihuan Pan
---
linux-user/sh4/termbits.h | 204 +++---
target/sh4/cpu.h
UG1087 states for the source channel that: if SIZE is programmed to 0, and the
DMA is started, the interrupts DONE and MEM_DONE will be asserted.
This implies that it is allowed for the guest to stop the source DMA by writing
a size of 0 to the SIZE register, so remove the LOG_GUEST_ERROR in that
It seems that the url changed a bit, and it triggers an error. Fix the URLs so
the documentation can be reached again.
Signed-off-by: Frederic Konrad
---
hw/dma/xlnx_csu_dma.c | 2 +-
include/hw/misc/xlnx-versal-cframe-reg.h | 2 +-
include/hw/misc/xlnx-versal-cfu.h
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