Stefan Hajnoczi writes:
> virtio-blk and virtio-scsi devices will need a way to specify the
> mapping between IOThreads and virtqueues. At the moment all virtqueues
> are assigned to a single IOThread or the main loop. This single thread
> can be a CPU bottleneck, so it is necessary to allow fine
Instructions in VEX exception class 6 generally look at the value of
VEX.W. Note that the manual places some instructions incorrectly in
class 4, for example VPERMQ which has no non-VEX encoding and no legacy
SSE analogue. AMD does a mess of its own, as documented in the comment
that this patch a
The new x86 decoder wants to compute EFLAGS before writeback, which
can be an issue for some instructions such as ARPL. Extract code
to compute the EFLAGS without clobbering CC_SRC, in case the ARPL
memory write causes a fault.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 18 +
The new decoder likes to compute the address in A0 very early, so the
gen_lea_v_seg in gen_pop_T0 would clobber the address of the memory
operand. Instead use T0 since it is already available and will be
overwritten immediately after.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c
It is not used anymore by the old decoder, inline the CMP case into CMPS and
SCAS.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 145 +++-
1 file changed, 12 insertions(+), 133 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/
In preparation for adding more similar checks, move the VEX.L=0 check
and several X86_SPECIAL_* checks to a new field, where each bit represent
a common check on unused bits, or a restriction on the processor mode.
Likewise, many SVM intercepts can be checked during the decoding phase,
the main ex
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 5 -
target/i386/tcg/translate.c | 27 +++
2 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index 01c46e6a789..fb
---
tests/tcg/i386/test-avx.py | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tests/tcg/i386/test-avx.py b/tests/tcg/i386/test-avx.py
index 641a2ef69eb..6063fb2d11d 100755
--- a/tests/tcg/i386/test-avx.py
+++ b/tests/tcg/i386/test-avx.py
@@ -9,7 +9,7 @@
archs = [
"SSE"
This includes:
- implementing SHA and CMPccXADD instruction extensions
- introducing a new mechanism for flags writeback that avoids a
tricky failure
- converting the more orthogonal parts of the one-byte opcode
map, as well as the CMOVcc and SETcc instructions.
Tested by booting several 32
ALU instructions can write to both memory and flags. If the CC_SRC*
and CC_DST locations have been written already when a memory access
causes a fault, the value in CC_SRC* and CC_DST might be interpreted
with the wrong CC_OP (the one that is in effect before the instruction.
Besides just using t
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 705 +---
1 file changed, 4 insertions(+), 701 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 1f3cc6361c0..6e091fdb7f6 100644
--- a/target/i386/tcg/translate.
The implementation was validated with OpenSSL and with the test vectors in
https://github.com/rust-lang/stdarch/blob/master/crates/core_arch/src/x86/sha.rs.
The instructions provide a ~25% improvement on hashing a 64 MiB file:
runtime goes down from 1.8 seconds to 1.4 seconds; instruction count on
Some instructions use YMM0 implicitly, or use YMM9 as a read-modify-write
register destination. Initialize those registers as well.
Signed-off-by: Paolo Bonzini
---
tests/tcg/i386/test-avx.c | 8
1 file changed, 8 insertions(+)
diff --git a/tests/tcg/i386/test-avx.c b/tests/tcg/i386/t
Use MO_SIGN to indicate signed vs. unsigned extension, and filter out
bits other than MO_SIGN and MO_SIZE.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/target/i386/tcg/translate.c
Move long-displacement Jcc, SETcc and CMOVcc to the new decoder.
While filling in the tables makes the code seem longer, the new
emitters are all just one line of code.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 56
target/i386/tcg/decode
The main difficulty here is that a page fault when writing to the destination
must not overwrite the flags. Therefore, the compute-flags helper must be
called with a temporary destination instead of using gen_jcc1*.
For simplicity, I am using an unconditional cmpxchg operation, that becomes
a NOP
gen_jcc() has been changed to accept a relative offset since the
new decoder was written. Adjust the J operand, which is meant
to be used with jump instructions such as gen_jcc(), to not
include the program counter and to not truncate the result, as
both operations are now performed by common code
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 157 ++
target/i386/tcg/decode-new.h | 3 +
target/i386/tcg/emit.c.inc | 340 +++
target/i386/tcg/translate.c | 38 ++--
4 files changed, 522 insertions(+), 16 deletions(-
Similar to gen_setcc1, make gen_cmovcc1 receive TCGv. This is more friendly
to simultaneous implementation in the old and the new decoder.
A small wart is that s->T0 of CMOV is currently the *second* argument (which
would ordinarily be in T1). Therefore, the condition as to be inverted in
order
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 116 ++
target/i386/tcg/decode-new.h | 3 +
target/i386/tcg/emit.c.inc | 201 +++
target/i386/tcg/translate.c | 2 +-
4 files changed, 321 insertions(+), 1 deletion(-
On Fri, Sep 8, 2023 at 12:54 AM Denis V. Lunev wrote:
> Unfortunately 271 IO test is broken if started in non-cached mode.
>
Is this a real world issue? For example in oVirt you cannot create a disk
with
size < 4k so there is no way that 4k is not a good alignment.
Should we fix the test to ref
On 09/10/2023 20:54, BALATON Zoltan wrote:
The initial value for BARs were set in reset method for emulating
legacy mode at start but this does not work because PCI code resets
BARs after calling device reset method. Remove this ineffective
default to avoid confusion.
Instead move setting the B
Hi,
I can confirm that the patch indeed fixes the issue.
Kind regards,
Edmund Raile
Tested-by: Edmund Raile
summary
adresses https://gitlab.com/qemu-project/qemu/-/issues/1150
replaces blocking gtk_clipboard_wait_is_text_available in gd_owner_change and
gtk_clipboard_wait_for_text in gd_clipboard_request with asynchronous
gtk_clipboard_request_text
uses serial_last and serial of QemuClipboardInfo to o
Hi,
On Thu, Sep 28, 2023 at 03:32:54PM +0100, Daniel P. Berrangé wrote:
> On Wed, Sep 27, 2023 at 01:25:42PM +0200, Victor Toso wrote:
> > This patch handles QAPI command types and generates data structures in
> > Go that decodes from QMP JSON Object to Go data structure and vice
> > versa.
> >
>
On Thu, 12 Oct 2023 13:12:36 +0900,
Philippe Mathieu-Daudé wrote:
>
> Host bridge device and PCI function #0 are inverted.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
> ---
> hw/pci-host/sh_pci.c | 16
> 1 file changed, 8 insertions(+), 8 deletions(-
On Thu, 12 Oct 2023 13:12:37 +0900,
Philippe Mathieu-Daudé wrote:
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
> ---
> hw/pci-host/sh_pci.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/hw/pci-host/sh_pci.c b/hw/pci-host/sh_pci.c
> inde
On Thu, 12 Oct 2023 13:12:35 +0900,
Philippe Mathieu-Daudé wrote:
>
> When multiple QOM types are registered in the same file,
> it is simpler to use the the DEFINE_TYPES() macro. In
> particular because type array declared with such macro
> are easier to review.
>
> Signed-off-by: Philippe Mathi
On 10/14/23 03:01, Paolo Bonzini wrote:
+static void prepare_update1_cc(X86DecodedInsn *decode, DisasContext *s, CCOp
op)
+{
+decode->cc_dst = s->T0;
+set_cc_op(s, op);
+}
You must delay the set_cc_op() until the end too, for the same reason. The function call
will emit discard opcod
On Sat, 14 Oct 2023, Mark Cave-Ayland wrote:
On 09/10/2023 20:54, BALATON Zoltan wrote:
The initial value for BARs were set in reset method for emulating
legacy mode at start but this does not work because PCI code resets
BARs after calling device reset method. Remove this ineffective
default t
Using interface's settings, let's enforce an always on link up.
Signed-off-by: Vincent Jardin
---
hw/net/virtio-net.c| 8
include/hw/virtio/virtio-net.h | 2 ++
2 files changed, 10 insertions(+)
diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index 29e33ea5ed..e731b4
On Sat, Oct 14, 2023 at 06:22:34PM +0200, Vincent Jardin wrote:
> Using interface's settings, let's enforce an always on link up.
>
> Signed-off-by: Vincent Jardin
What is going on here? Just don't set it down.
> ---
> hw/net/virtio-net.c| 8
> include/hw/virtio/virtio-net
On 10/14/23 00:35, Akihiko Odaki wrote:
TARGET_RISCV64 does not have riscv-32bit-cpu.xml so it shouldn't accept
MXL_RV32.
Signed-off-by: Akihiko Odaki
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/tcg/tcg-cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --
On 10/14/23 00:35, Akihiko Odaki wrote:
gdb_core_xml_file was assigned each time a CPU is instantiated before
this change.
Signed-off-by: Akihiko Odaki
---
target/riscv/cpu.c | 5 +
target/riscv/tcg/tcg-cpu.c | 4
2 files changed, 5 insertions(+), 4 deletions(-)
diff --
Hi!
I wanted to experiment with sector size = 4096, to see how an OS
reacts. And naturally, the first instinct is to try it in qemu.
But it turned to be.. difficult.
First, there's no documentation. But I remember seeing properties
of ide-hd device, like physical_sector_size etc. Ok.
$ qemu
Can't we make -drive if=none the default?
Yes, I know current default is ide, and whole world have to use if=none
explicitly
to undo this. I think at this point we can deprecate if=ide default and switch
to
if=none in the next release. I think it will be a welcome change.
/mjt
The initial value for BARs were set in reset method for emulating
legacy mode at start but this does not work because PCI code resets
BARs after calling device reset method. Remove this ineffective
default to avoid confusion.
Instead move setting the BARs to a callback on writing the PCI config
re
The AmigaOne is a rebranded MAI Teron board that uses U-Boot firmware
with patches to support AmigaOS and is very similar to pegasos2 so can
be easily emulated sharing most code with pegasos2. The reason to
emulate it is that AmigaOS comes in different versions for AmigaOne
and PegasosII which only
The Articia S is a generic chipset supporting several different CPUs
that were among others used on some PPC boards. This is a minimal
emulation of the parts needed for emulating the AmigaOne board.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/Kconfig | 5 +
hw/pci-host/articia.c
Changes in v3:
- Update values, comment and commit message in patch 1 again
Changes in v2:
- Update comment and commit message in patch 1 (Mark)
- Fix irq mapping in patch 2 (Volker)
Regards,
BALATON Zoltan
BALATON Zoltan (3):
via-ide: Fix legacy mode emulation
hw/pci-host: Add emulation of
On Sat, 14 Oct 2023, Mark Cave-Ayland wrote:
On 09/10/2023 20:54, BALATON Zoltan wrote:
The initial value for BARs were set in reset method for emulating
legacy mode at start but this does not work because PCI code resets
BARs after calling device reset method. Remove this ineffective
default to
From: Helge Deller
For SeaBIOS-hppa, the RTC and DebugOutputPort were in the I/O area of
the LASI chip of the emulated B160L machine.
Since we will add other machines without a LASI chip, move the emulated
devices into the I/O area of CPU#0 instead.
Signed-off-by: Helge Deller
---
hw/hppa/hppa
From: Helge Deller
The 64-bit PA-RISC machines use a Astro system bus adapter (SBA)
with Elroy PCI host chips.
Later generation Astro chips were named Pluto, Ike and REO.
Signed-off-by: Helge Deller
---
hw/pci-host/astro.c | 876
hw/pci-host/trace-e
From: Helge Deller
Signed-off-by: Helge Deller
---
hw/net/tulip.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/net/tulip.c b/hw/net/tulip.c
index 915e5fb595..11d866e431 100644
--- a/hw/net/tulip.c
+++ b/hw/net/tulip.c
@@ -1020,7 +1020,7 @@ static void tulip_class_init(
From: Helge Deller
Allow the Astro source to be built.
Signed-off-by: Helge Deller
---
hw/hppa/Kconfig | 1 +
hw/pci-host/Kconfig | 4
hw/pci-host/meson.build | 1 +
3 files changed, 6 insertions(+)
diff --git a/hw/hppa/Kconfig b/hw/hppa/Kconfig
index 5dd8b5b21e..ff8528aaa8 1
From: Helge Deller
Add code to create an emulated C3700 machine.
It includes the following components:
- HP Powerbar SP2 Diva BMC card (serial port only)
- PCI 4x serial card (for serial ports #1-#4)
- USB OHCI controller with USB keyboard and USB mouse
Signed-off-by: Helge Deller
---
hw/hppa/
From: Helge Deller
Provide necessary info to SeaBIOS-hppa.
Signed-off-by: Helge Deller
---
hw/hppa/machine.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index c6d8deffcf..be0caf4675 100644
--- a/hw/hppa/machine.c
From: Helge Deller
The new SeaBIOS-hppa version 10 includes initial support
for PA2.0 CPUs.
Signed-off-by: Helge Deller
---
hw/hppa/machine.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index cf28cb9586..c6d8deffcf 100644
From: Helge Deller
Those PS/2 ports are created with the LASI controller when
a 32-bit PA-RISC machine is created.
Mark them not user-createable to avoid showing them in
the qemu device list.
Signed-off-by: Helge Deller
Cc: qemu-sta...@nongnu.org
---
hw/input/lasips2.c | 4
1 file change
From: Helge Deller
This is a preparation patch to allow the creation of additional
hppa machine.
It splits out the creation of the machine into a
- machine_HP_common_init_cpus(), and a
- machine_HP_common_init_tail()
function.
This will allow to reuse the basic functions which are common to
all
From: Helge Deller
Signed-off-by: Helge Deller
---
MAINTAINERS | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index ceea4c2bf2..68d086a0f3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1174,7 +1174,7 @@ F: hw/*/etraxfs_*.c
HP-PARISC Machine
From: Helge Deller
This series adds a new PA-RISC machine emulation for the HP-PARISC
C3700 workstation.
The physical HP C3700 machine has a PA2.0 (64-bit) CPU, in contrast to
the existing emulation of a B160L workstation which is a 32-bit only
machine and where it's Dino PCI controller isn't 64
From: Helge Deller
Signed-off-by: Helge Deller
---
include/hw/pci/pci_ids.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h
index 85469b9b53..3c0e72df0e 100644
--- a/include/hw/pci/pci_ids.h
+++ b/include/hw/pci/pci_ids.h
@@ -171,6 +171,
On Sat, 14 Oct 2023, Michael Tokarev wrote:
Can't we make -drive if=none the default?
Yes, I know current default is ide, and whole world have to use if=none
explicitly
to undo this. I think at this point we can deprecate if=ide default and
switch to
if=none in the next release. I think it
On Sat, 14 Oct 2023, del...@kernel.org wrote:
From: Helge Deller
Those PS/2 ports are created with the LASI controller when
a 32-bit PA-RISC machine is created.
Mark them not user-createable to avoid showing them in
the qemu device list.
Signed-off-by: Helge Deller
Cc: qemu-sta...@nongnu.org
On Sat, 14 Oct 2023, del...@kernel.org wrote:
From: Helge Deller
Signed-off-by: Helge Deller
---
hw/net/tulip.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/net/tulip.c b/hw/net/tulip.c
index 915e5fb595..11d866e431 100644
--- a/hw/net/tulip.c
+++ b/hw/net/tulip.c
@@ -1
On Sat, 14 Oct 2023, del...@kernel.org wrote:
From: Helge Deller
The new SeaBIOS-hppa version 10 includes initial support
for PA2.0 CPUs.
Patch does a few misc things not mentioned in commit message. Would those
need to be split of in separate patch or mentioned here?
Regards,
BALATON Zolt
On 10/14/23 18:37, Michael S. Tsirkin wrote:
> On Sat, Oct 14, 2023 at 06:22:34PM +0200, Vincent Jardin wrote:
>> Using interface's settings, let's enforce an always on link up.
>>
>> Signed-off-by: Vincent Jardin
>
> What is going on here? Just don't set it down.
The purpose is to have a stable
On 2023/10/15 3:19, Daniel Henrique Barboza wrote:
On 10/14/23 00:35, Akihiko Odaki wrote:
gdb_core_xml_file was assigned each time a CPU is instantiated before
this change.
Signed-off-by: Akihiko Odaki
---
target/riscv/cpu.c | 5 +
target/riscv/tcg/tcg-cpu.c | 4
2 file
Use of the API was removed a while back, but the define wasn't.
Signed-off-by: Mike Frysinger
---
include/tcg/tcg-op.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index 80cfcf8104b6..3ead59e4594d 100644
--- a/include/tcg/tcg-op.h
+++ b/include
The following patches are queued for QEMU stable v8.1.2:
https://gitlab.com/qemu-project/qemu/-/commits/staging-8.1
Patch freeze is 2023-10-14 (frozen now), and the release is planned
for 2023-10-16:
https://wiki.qemu.org/Planning/8.1
This release supposed to finally fix some long-standing
From: Olaf Hering
python3 may not be the expected python version.
Use PYTHON to invoke python.
Fixes: 22e11539e1 ("edk2: replace build scripts")
Signed-off-by: Olaf Hering
Signed-off-by: Michael Tokarev
(cherry picked from commit 17b8d8ac3309e2cfed0d8cb3861afdcc23f66ce0)
diff --git a/roms/Ma
From: Max Chou
The operator (fwmacc16) of vfwmaccbf16.vf helper function should be
replaced by fwmaccbf16.
Fixes: adf772b0f7 ("target/riscv: Add support for Zvfbfwma extension")
Signed-off-by: Max Chou
Reviewed-by: LIU Zhiwei
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20231005095734.567
From: Alvin Chang
Fix the inverted order of pmpaddr13 and pmpaddr14 in csr_name().
Signed-off-by: Alvin Chang
Reviewed-by: Alistair Francis
Message-ID: <20230907084500.328-1-alvi...@andestech.com>
Signed-off-by: Alistair Francis
(cherry picked from commit cffa9954908830276c93b430681f66cc0e599
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