Re: [PATCH 1/1] hw/ide/core: terminate in-flight DMA on IDE bus reset

Am 25.09.23 um 21:53 schrieb John Snow: > On Thu, Sep 21, 2023 at 12:07 PM Simon Rowe wrote: >> >> When an IDE controller is reset, its internal state is being cleared >> before any outstanding I/O is cancelled. If a response to DMA is >> received in this window, the aio callback will incorrectly

[PATCH 1/1] target/loongarch: Clean up local variable shadowing

Fix: [1839/2601] Compiling C object libqemu-loongarch64-softmmu.fa.p/hw_loongarch_virt.c.o ../hw/loongarch/virt.c: In function 'loongarch_irq_init': ../hw/loongarch/virt.c:665:14: warning: declaration of 'i' shadows a previous local [-Wshadow=compatible-local] for (int i = 0; i < nu

Re: [RFC] Proposal of QEMU PCI Endpoint test environment

On Thu, Sep 21, 2023 at 02:41:54PM +0530, Kishon Vijay Abraham I wrote: > > PCI Endpoint function driver is implemented using the PCIe Endpoint > > framework, but it requires physical boards for testing, and it is difficult > > to test sufficiently. In order to find bugs and hardware-dependent > >

Re: [PATCH] m68k: Silence -Wshadow=local warnings in the m68k code

Le 25/09/2023 à 20:56, Thomas Huth a écrit : Rename the innermost variables to make the code compile without warnings when using -Wshadow=local. Signed-off-by: Thomas Huth --- hw/m68k/bootinfo.h | 10 -- disas/m68k.c| 8 target/m68k/translate.c | 8 --

Re: [PATCH v2 10/20] q800: add easc bool machine class property to switch between ASC and EASC

Le 09/09/2023 à 11:48, Mark Cave-Ayland a écrit : This determines whether the Apple Sound Chip (ASC) is set to enhanced mode (default) or to original mode. The real Q800 hardware used an EASC chip however a lot of older software only works with the older ASC chip. Adding this as a machine parame

Re: [PATCH v2 11/20] swim: add trace events for IWM and ISM registers

Le 09/09/2023 à 11:48, Mark Cave-Ayland a écrit : Signed-off-by: Mark Cave-Ayland --- hw/block/swim.c | 14 ++ hw/block/trace-events | 7 +++ 2 files changed, 21 insertions(+) diff --git a/hw/block/swim.c b/hw/block/swim.c index 333da08ce0..7df36ea139 100644 --- a/hw/

[PATCH 1/1] tcg/loongarch64: Fix buid error

From: gaosong Fix: In file included from ../tcg/tcg.c:735: /home1/gaosong/bugfix/qemu/tcg/loongarch64/tcg-target.c.inc: In function ‘tcg_out_vec_op’: /home1/gaosong/bugfix/qemu/tcg/loongarch64/tcg-target.c.inc:1855:9: error: a label can only be part of a statement and a declaration is no

Re: [PATCH 0/4] ui/console: multihead: fix crash, simplify logic

Hi Laszlo On Mon, Sep 25, 2023 at 7:36 PM Laszlo Ersek wrote: > Has this been queued by someone? Both Gerd and Marc-André are "odd > fixers", so I'm not sure who should be sending a PR with these patches > (and I don't see a pending PULL at >

Re: [PATCH v2 14/20] mac_via: work around underflow in TimeDBRA timing loop in SETUPTIMEK

Le 09/09/2023 à 11:48, Mark Cave-Ayland a écrit : The MacOS toolbox ROM calculates the number of branches that can be executed per millisecond as part of its timer calibration. Since modern hosts are considerably quicker than original hardware, the negative counter reaches zero before the calibra

Re: [PATCH v2 15/20] mac_via: workaround NetBSD ADB bus enumeration issue

Le 09/09/2023 à 11:48, Mark Cave-Ayland a écrit : NetBSD assumes it can send its first ADB command after sending the ADB_BUSRESET command in ADB_STATE_NEW without changing the state back to ADB_STATE_IDLE first as detailed in the ADB protocol. Add a workaround to detect this condition at the sta

Re: [PATCH v2 16/20] mac_via: implement ADB_STATE_IDLE state if shift register in input mode

Le 09/09/2023 à 11:48, Mark Cave-Ayland a écrit : NetBSD switches directly to IDLE state without switching the shift register to input mode. Duplicate the existing ADB_STATE_IDLE logic in input mode from when the shift register is in output mode which allows the ADB autopoll handler to handle the

Re: [PATCH v2 17/20] mac_via: always clear ADB interrupt when switching to A/UX mode

Le 09/09/2023 à 11:48, Mark Cave-Ayland a écrit : When the NetBSD kernel initialises it can leave the ADB interrupt asserted depending upon where in the ADB poll cycle the MacOS ADB interrupt handler is when the NetBSD kernel disables interrupts. The NetBSD ADB driver uses the ADB interrupt stat

Re: [PATCH v2 18/20] q800: add ESCC alias at 0xc000

Le 09/09/2023 à 11:48, Mark Cave-Ayland a écrit : Tests on real Q800 hardware show that the ESCC is addressable at multiple locations within the ESCC memory region - at least 0xc000, 0xc020 (as expected by the MacOS toolbox ROM) and 0xc040. All released NetBSD kernels before 10 use the 0xc000

Re: [PATCH v2 00/12] VIRTIO-IOMMU/VFIO: Don't assume 64b IOVA space

The original issue I found : After starting a VM which has two ice PFs and a virtio-iommu device, qemu-kvm and VM guest dmesg throw lots of duplicate VFIO_MAP_DMA errors After testing with Eric's build, the original issue is gone and the Tier1 regression test against ice PF and virtio iommu devic

Re: [PATCH v2 20/20] mac_via: extend timer calibration hack to work with A/UX

Le 09/09/2023 à 11:48, Mark Cave-Ayland a écrit : The A/UX timer calibration loop runs continuously until 2 consecutive iterations differ by at least 0x492 timer ticks. Modern hosts execute the timer calibration loop so fast that this situation never occurs causing a hang on boot. Use a similar

Re: [PATCH v2 19/20] q800: add alias for MacOS toolbox ROM at 0x40000000

Le 09/09/2023 à 11:48, Mark Cave-Ayland a écrit : According to the Apple Quadra 800 Developer Note document, the Quadra 800 ROM consists of 2 ROM code sections based at offsets 0x0 and 0x80. A/UX attempts to access the toolbox ROM at the lower offset during startup, so provide a memory alias

Re: [PATCH v2 12/20] swim: split into separate IWM and ISM register blocks

Le 09/09/2023 à 11:48, Mark Cave-Ayland a écrit : The swim chip provides an implementation of both Apple's IWM and ISM floppy disk controllers. Split the existing implementation into separate register banks for each controller, whilst also switching the IWM registers from 16-bit to 8-bit as imple

Re: [PATCH v2 13/20] swim: update IWM/ISM register block decoding

Le 09/09/2023 à 11:48, Mark Cave-Ayland a écrit : Update the IWM/ISM register block decoding to match the description given in the "SWIM Chip Users Reference". This allows us to validate the device response to the guest OS which currently only does just enough to indicate that the floppy drive is

[PATCH] analyze-migration: ignore RAM_SAVE_FLAG_MULTIFD_FLUSH

From: Marc-André Lureau Traceback (most recent call last): File "scripts/analyze-migration.py", line 605, in dump.read(dump_memory = args.memory) File "scripts/analyze-migration.py", line 542, in read section.read() File "scripts/analyze-migration.py", line 214, in read raise E

Re: [PATCH] MAINTAINERS: Add entry for rdma migration

On 25/09/2023 21:34, Peter Xu wrote: > It's not obvious to many that RDMA migration is in Odd Fixes stage for a > long time. Add an explicit sub entry for it (besides migration, which > already covers the rdma files) to be clear on that, meanwhile add Zhijian > as Reviewer, so Zhijian can see th

Re: [PATCH 12/12] io/channel-socket: qio_channel_socket_flush(): improve msg validation

Could you add a comment into the commit message why ee_data must be bigger than ee_info? On 9/25/23 22:40, Vladimir Sementsov-Ogievskiy wrote: Signed-off-by: Vladimir Sementsov-Ogievskiy --- io/channel-socket.c | 5 + 1 file changed, 5 insertions(+) diff --git a/io/channel-socket.c b/io

Re: [PATCH v2 0/3] migration-qtest: zero the first byte of each page on start

ping :)

Re: [PATCH 52/52] migration/rdma: Fix how we show device details on open

"Zhijian Li (Fujitsu)" writes: > On 18/09/2023 22:42, Markus Armbruster wrote: >> qemu_rdma_dump_id() dumps RDMA device details to stdout. >> >> rdma_start_outgoing_migration() calls it via qemu_rdma_source_init() >> and qemu_rdma_resolve_host() to show source device details. >> rdma_start_incom

Re: [PATCH 39/52] migration/rdma: Convert qemu_rdma_write_one() to Error

"Zhijian Li (Fujitsu)" writes: > On 26/09/2023 13:50, Li Zhijian wrote: >> >> >> On 18/09/2023 22:41, Markus Armbruster wrote: >>> Functions that use an Error **errp parameter to return errors should >>> not also report them to the user, because reporting is the caller's >>> job.  When the call

Re: [RFC] Proposal of QEMU PCI Endpoint test environment

On 2023/09/21 18:11, Kishon Vijay Abraham I wrote: +Vaishnav Hi Shunsuke, On 8/18/2023 7:16 PM, Shunsuke Mie wrote: Hi all, We are proposing to add a new test syste to Linux for PCIe Endpoint. That can be run on QEMU without real hardware. At present, partially we have confirmed that pci-

[PATCH v3 1/7] Update ACPI GED framework to support vcpu hot-(un)plug

ACPI GED shall be used to convey to the guest kernel about any cpu hot-(un)plug events. Therefore, existing ACPI GED framework inside QEMU needs to be enhanced to support CPU hot-(un)plug state and events. Co-authored-by: "Salil Mehta" Co-authored-by: "Salil Mehta" Cc: "Bernhard Beschow" Cc: "S

[PATCH v3 5/7] Add basic CPU hot-(un)plug support for Loongarch

Add CPU hot-(un)plug related hook functions and turn on the CPU hot-(un)plug custom switch. Cc: "Bernhard Beschow" Cc: "Salil Mehta" Cc: "Salil Mehta" Cc: Xiaojuan Yang Cc: Song Gao Cc: "Michael S. Tsirkin" Cc: Igor Mammedov Cc: Ani Sinha Cc: Paolo Bonzini Cc: Richard Henderson Cc: Eduar

[PATCH v3 0/7] *** Adds CPU hot-plug support to Loongarch ***

Hello everyone, We refer to the implementation of ARM CPU Hot-Plug to add GED-based CPU Hot-Plug support to Loongarch. The first 2 patches are changes to the QEMU common code, including adding GED support for CPU Hot-Plug, updating the ACPI table creation process. For the modification of the publ

[PATCH v3 3/7] Added CPU topology support for Loongarch

1.Add topological relationships for Loongarch VCPU and initialize topology member variables. 2.Add a description of the calculation method of the arch_id and the topological relationship of the CPU. Cc: "Bernhard Beschow" Cc: "Salil Mehta" Cc: "Salil Mehta" Cc: Xiaojuan Yang Cc: Song Gao Cc:

[PATCH v3 7/7] Update the ACPI table for the Loongarch CPU

Add new types of GED devices for Loongarch machines, add CPU hot-(un)plug event response and address spaces, and update the ACPI table. Cc: "Bernhard Beschow" Cc: "Salil Mehta" Cc: "Salil Mehta" Cc: Xiaojuan Yang Cc: Song Gao Cc: "Michael S. Tsirkin" Cc: Igor Mammedov Cc: Ani Sinha Cc: Pao

[PATCH v3 6/7] Add support of *unrealize* for Loongarch cpu

Add the unrealize function to the Loongarch CPU for cpu hot-(un)plug Cc: "Bernhard Beschow" Cc: "Salil Mehta" Cc: "Salil Mehta" Cc: Xiaojuan Yang Cc: Song Gao Cc: "Michael S. Tsirkin" Cc: Igor Mammedov Cc: Ani Sinha Cc: Paolo Bonzini Cc: Richard Henderson Cc: Eduardo Habkost Cc: Marcel

[PATCH v3 4/7] Optimize loongarch_irq_init function implementation

Optimize loongarch_irq_init function implementation and abstract the function loongarch_cpu_irq_init from it. Cc: "Bernhard Beschow" Cc: "Salil Mehta" Cc: "Salil Mehta" Cc: Xiaojuan Yang Cc: Song Gao Cc: "Michael S. Tsirkin" Cc: Igor Mammedov Cc: Ani Sinha Cc: Paolo Bonzini Cc: Richard He

[PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change

CPUs Control device(\\_SB.PCI0) register interface for the x86 arch is based on PCI and is IO port based and hence existing cpus AML code assumes _CRS objects would evaluate to a system resource which describes IO Port address. But on Loongarch arch CPUs control device(\\_SB.PRES) register interfac

[PATCH v2 1/2] migration: Fix rdma migration failed

Migration over RDMA failed since commit: 294e5a4034 ("multifd: Only flush once each full round of memory") with erors: qemu-system-x86_64: rdma: Too many requests in this message (3638950032).Bailing. migration with RDMA is different from tcp. RDMA has its own control message, and all traffic bet

[PATCH v2 2/2] migration/rdma: zore out head.repeat to make the error more clear

Previously, we got a confusion error that complains the RDMAControlHeader.repeat: qemu-system-x86_64: rdma: Too many requests in this message (3638950032).Bailing. Actually, it's caused by an unexpected RDMAControlHeader.type. After this patch, error will become: qemu-system-x86_64: Unknown contr

[PATCH RFC V2 00/37] Support of Virtual CPU Hotplug for ARMv8 Arch

[ *REPEAT: Sent patches got held at internal server yesterday* ] PROLOGUE To assist in review and set the right expectations from this RFC, please first read below sections *APPENDED AT THE END* of this cover letter, 1. Important *DISCLAIMER* [Section (X)] 2. Work presented at KVMForum

[PATCH RFC V2 01/37] arm/virt, target/arm: Add new ARMCPU {socket, cluster, core, thread}-id property

This shall be used to store user specified topology{socket,cluster,core,thread} and shall be converted to a unique 'vcpu-id' which is used as slot-index during hot(un)plug of vCPU. Co-developed-by: Salil Mehta Signed-off-by: Salil Mehta Co-developed-by: Keqian Zhu Signed-off-by: Keqian Zhu Sig

[PATCH RFC V2 02/37] cpus-common: Add common CPU utility for possible vCPUs

Adds various utility functions which might be required to fetch or check the state of the possible vCPUs. This also introduces concept of *disabled* vCPUs, which are part of the *possible* vCPUs but are not part of the *present* vCPU. This state shall be used during machine init time to check the p

[PATCH RFC V2 04/37] arm/virt, target/arm: Machine init time change common to vCPU {cold|hot}-plug

Refactor and introduce the common logic required during the initialization of both cold and hot plugged vCPUs. Also initialize the *disabled* state of the vCPUs which shall be used further during init phases of various other components like GIC, PMU, ACPI etc as part of the virt machine initializat

[PATCH RFC V2 05/37] accel/kvm: Extract common KVM vCPU {creation, parking} code

KVM vCPU creation is done once during the initialization of the VM when Qemu threads are spawned. This is common to all the architectures. If the architecture supports vCPU hot-{un}plug then this KVM vCPU creation could be deferred to later point as well. Some architectures might in any case creat

[PATCH RFC V2 03/37] hw/arm/virt: Move setting of common CPU properties in a function

Factor out CPU properties code common for {hot,cold}-plugged CPUs. This allows code reuse. Signed-off-by: Salil Mehta --- hw/arm/virt.c | 220 ++ include/hw/arm/virt.h | 4 + 2 files changed, 140 insertions(+), 84 deletions(-) diff --git a/hw/ar

[PATCH RFC V2 08/37] arm/virt: Init PMU at host for all possible vcpus

PMU for all possible vCPUs must be initialized at the VM initialization time. Refactor existing code to accomodate possible vCPUs. This also assumes that all processor being used are identical. Past discussion for reference: Link: https://lists.gnu.org/archive/html/qemu-devel/2020-06/msg00131.html

[PATCH RFC V2 09/37] hw/acpi: Move CPU ctrl-dev MMIO region len macro to common header file

CPU ctrl-dev MMIO region length could be used in ACPI GED (common ACPI code across architectures) and various other architecture specific places. To make these code places independent of compilation order, ACPI_CPU_HOTPLUG_REG_LEN macro should be moved to a header file. Signed-off-by: Salil Mehta

[PATCH RFC V2 06/37] arm/virt, kvm: Pre-create disabled possible vCPUs @machine init

In ARMv8 architecture, GIC needs all the vCPUs to be created and present when it is initialized. This is because: 1. GICC and MPIDR association must be fixed at the VM initialization time. This is represented by register GIC_TYPER(mp_afffinity, proc_num) 2. GICC(cpu interfaces), GICR(redistribut

[PATCH RFC V2 07/37] arm/virt, gicv3: Changes to pre-size GIC with possible vcpus @machine init

GIC needs to be pre-sized with possible vcpus at the initialization time. This is necessary because Memory regions and resources associated with GICC/GICR etc cannot be changed (add/del/modified) after VM has inited. Also, GIC_TYPER needs to be initialized with mp_affinity and cpu interface number

Re: [PATCH 05/12] device_tree: qmp_dumpdtb(): stronger assertion

On 26.09.23 04:26, Alistair Francis wrote: On Tue, Sep 26, 2023 at 6:42 AM Vladimir Sementsov-Ogievskiy wrote: Coverity mark this size, got from the buffer as untrasted value, it's s/untrasted/untrusted/g will fix. not good to use it as length when writing to file. Make the assertion m

[PATCH RFC V2 10/37] arm/acpi: Enable ACPI support for vcpu hotplug

ACPI is required to interface QEMU with the guest. Roughly falls into below cases, 1. Convey the possible vcpus config at the machine init time to the guest using various DSDT tables like MADT etc. 2. Convey vcpu hotplug events to guest(using GED) 3. Assist in evaluation of various ACPI methods

[PATCH RFC V2 13/37] hw/acpi: Init GED framework with cpu hotplug events

ACPI GED(as described in the ACPI 6.2 spec) can be used to generate ACPI events when OSPM/guest receives an interrupt listed in the _CRS object of GED. OSPM then maps or demultiplexes the event by evaluating _EVT method. This change adds the support of cpu hotplug event initialization in the exist

[PATCH RFC V2 11/37] hw/acpi: Add ACPI CPU hotplug init stub

ACPI CPU hotplug related initialization should only happend if ACPI_CPU_HOTPLUG support has been enabled for particular architecture. Add cpu_hotplug_hw_init() stub to avoid compilation break. Signed-off-by: Salil Mehta --- hw/acpi/acpi-cpu-hotplug-stub.c | 6 ++ 1 file changed, 6 insertions

[PATCH RFC V2 12/37] hw/acpi: Use qemu_present_cpu() API in ACPI CPU hotplug init

ACPI CPU Hotplug code assumes a virtual CPU is unplugged if the CPUState object is absent in the list of ths possible CPUs(CPUArchIdList *possible_cpus) maintained on per-machine basis. Use the earlier introduced qemu_present_cpu() API to check this state. This change should have no bearing on the

[PATCH RFC V2 15/37] arm/virt: Create GED dev before *disabled* CPU Objs are destroyed

ACPI CPU hotplug state (is_present=_STA.PRESENT, is_enabled=_STA.ENABLED) for all the possible vCPUs MUST be initialized during machine init. This is done during the creation of the GED device. VMM/Qemu MUST expose/fake the ACPI state of the disabled vCPUs to the Guest kernel as 'present' (_STA.PRE

[PATCH RFC V2 14/37] arm/virt: Add cpu hotplug events to GED during creation

Add CPU Hotplug event to the set of supported ged-events during the creation of GED device during VM init. Also initialize the memory map for CPU Hotplug control device used in event exchanges between Qemu/VMM and the guest. Signed-off-by: Salil Mehta --- hw/arm/virt.c | 5 - include

[PATCH RFC V2 16/37] hw/acpi: Update CPUs AML with cpu-(ctrl)dev change

CPUs Control device(\\_SB.PCI0) register interface for the x86 arch is based on PCI and is IO port based and hence existing cpus AML code assumes _CRS objects would evaluate to a system resource which describes IO Port address. But on ARM arch CPUs control device(\\_SB.PRES) register interface is m

[PATCH RFC V2 17/37] arm/virt/acpi: Build CPUs AML with CPU Hotplug support

Support of vCPU Hotplug requires sequence of ACPI handshakes between Qemu and Guest kernel when a vCPU is plugged or unplugged. Most of the AML code to support these handshakes already exists. This AML need to be build during VM init for ARM architecture as well if the GED support exists. Signed-o

[PATCH RFC V2 18/37] arm/virt: Make ARM vCPU *present* status ACPI *persistent*

ARM arch does not allow CPUs presence to be changed [1] after kernel has booted. Hence, firmware/ACPI/Qemu must ensure persistent view of the vCPUs to the Guest kernel even when they are not present in the QoM i.e. are unplugged or are yet-to-be-plugged References: [1] Check comment 5 in the bugzi

[PATCH RFC V2 19/37] hw/acpi: ACPI/AML Changes to reflect the correct _STA.{PRES, ENA} Bits to Guest

ACPI AML changes to properly reflect the _STA.PRES and _STA.ENA Bits to the guest during initialzation, when CPUs are hotplugged and after CPUs are hot-unplugged. Signed-off-by: Salil Mehta --- hw/acpi/cpu.c | 49 +++--- hw/acpi/generic_event_device.c

[PATCH RFC V2 20/37] hw/acpi: Update GED _EVT method AML with cpu scan

OSPM evaluates _EVT method to map the event. The cpu hotplug event eventually results in start of the cpu scan. Scan figures out the cpu and the kind of event(plug/unplug) and notifies it back to the guest. The change in this patch updates the GED AML _EVT method with the call to \\_SB.CPUS.CSCN w

[PATCH RFC V2 21/37] hw/arm: MADT Tbl change to size the guest with possible vCPUs

Changes required during building of MADT Table by QEMU to accomodate disabled possible vCPUs. This info shall be used by the guest kernel to size up its resources during boot time. This pre-sizing of the guest kernel done on possible vCPUs will facilitate hotplug of the disabled vCPUs. This change

[PATCH RFC V2 23/37] arm/virt: Release objects for *disabled* possible vCPUs after init

During machvirt_init(), QOM ARMCPU objects are also pre-created along with the corresponding KVM vCPUs in the host for all possible vCPUs. This necessary because of the architectural constraint, KVM restricts the deferred creation of the KVM vCPUs and VGIC initialization/sizing after VM init. Hence

[PATCH RFC V2 22/37] hw/acpi: Make _MAT method optional

From: Jean-Philippe Brucker The GICC interface on arm64 vCPUs is statically defined in the MADT, and doesn't require a _MAT entry. Although the GICC is indicated as present by the MADT entry, it can only be used from vCPU sysregs, which aren't accessible until hot-add. Co-developed-by: Jean-Phil

[PATCH RFC V2 24/37] hw/acpi: Update ACPI GED framework to support vCPU Hotplug

ACPI GED shall be used to convey to the guest kernel about any CPU hot-(un)plug events. Therefore, existing ACPI GED framework inside QEMU needs to be enhanced to support CPU hotplug state and events. Co-developed-by: Salil Mehta Signed-off-by: Salil Mehta Co-developed-by: Keqian Zhu Signed-off

[PATCH RFC V2 25/37] arm/virt: Add/update basic hot-(un)plug framework

Add CPU hot-unplug hooks and update hotplug hooks with additional sanity checks for use in hotplug paths. Note, Functional contents of the hooks(now left with TODO comment) shall be gradually filled in the subsequent patches in an incremental approach to patch and logic building which would be rou

Re: [PATCH 50/52] migration/rdma: Silence qemu_rdma_cleanup()

On 18/09/2023 22:42, Markus Armbruster wrote: > Functions that use an Error **errp parameter to return errors should > not also report them to the user, because reporting is the caller's > job. When the caller does, the error is reported twice. When it > doesn't (because it recovered from the e

[PATCH RFC V2 26/37] arm/virt: Changes to (un)wire GICC<->vCPU IRQs during hot-(un)plug

Refactors the existing GIC create code to extract common code to wire the vcpu<->gic interrupts. This function could be used with cold-plug case and also used when vCPU is hot-plugged. It also introduces a new function to unwire the vcpu<->gic interrupts for the vCPU hot-unplug cases. Co-developed

[PATCH RFC V2 27/37] hw/arm, gicv3: Changes to update GIC with vCPU hot-plug notification

vCPU hot-(un)plug events MUST be notified to the GIC. Introduce a notfication mechanism to update any such events to GIC so that it can update its vCPU to GIC CPU interface association. This is required to implement a workaround to the limitations posed by the ARM architecture. For details about t

[PATCH RFC V2 30/37] hw/arm: Changes required for reset and to support next boot

Updates the firmware config with the next boot cpus information and also registers the reset callback to be called when guest reboots to reset the cpu. Co-developed-by: Salil Mehta Signed-off-by: Salil Mehta Co-developed-by: Keqian Zhu Signed-off-by: Keqian Zhu Signed-off-by: Salil Mehta ---

Re: [PATCH 11/12] hw/core/loader: read_targphys(): add upper bound

On 25.09.23 23:12, Michael Tokarev wrote: 25.09.2023 22:40, Vladimir Sementsov-Ogievskiy wrote: Coverity doesn't like using "untrusted" values, coming from buffers and fd-s as length to do IO and allocations. And that's make sense. The "And that makes sense".  Just a nitpick in commit comment.

[PATCH RFC V2 28/37] hw/intc/arm-gicv3*: Changes required to (re)init the vCPU register info

vCPU register info needs to be re-initialized each time vCPU is hot-plugged. This has to be done both for emulation/TCG and KVM case. This is done in context to the GIC update notification for any vCPU hot-(un)plug events. This change adds that support and re-factors existing to maximize the code r

[PATCH RFC V2 29/37] arm/virt: Update the guest(via GED) about CPU hot-(un)plug events

During any vCPU hot-(un)plug, running guest VM needs to be intimated about the new vCPU being added or request the deletion of the vCPU which is already part of the guest VM. This is done using the ACPI GED event which eventually gets demultiplexed to a CPU hotplug event and further to specific hot

[PATCH RFC V2 31/37] physmem, gdbstub: Common helping funcs/changes to *unrealize* vCPU

Supporting vCPU Hotplug for ARM arch also means introducing new functionality of unrealizing the ARMCPU. This requires some new common functions. Defining them as part of architecture independent change so that this code could be reused by other interested parties. Signed-off-by: Salil Mehta ---

Re: [PATCH 24/52] migration/rdma: Return -1 instead of negative errno code

On 18/09/2023 22:41, Markus Armbruster wrote: > Several functions return negative errno codes on failure. Callers > check for specific codes exactly never. For some of the functions, > callers couldn't check even if they wanted to, because the functions > also return negative values that aren't

Re: [PATCH 25/52] migration/rdma: Dumb down remaining int error values to -1

On 18/09/2023 22:41, Markus Armbruster wrote: > This is just to make the error value more obvious. Callers don't > mind. > > Signed-off-by: Markus Armbruster Reviewed-by: Li Zhijian

Re: [PATCH 26/52] migration/rdma: Replace int error_state by bool errored

On 25/09/2023 15:09, Markus Armbruster wrote: > "Zhijian Li (Fujitsu)" writes: > >> On 18/09/2023 22:41, Markus Armbruster wrote: >>> All we do with the value of RDMAContext member @error_state is test >>> whether it's zero. Change to bool and rename to @errored. >>> >> >> make sense! >> >> Re

Re: [PATCH 12/12] io/channel-socket: qio_channel_socket_flush(): improve msg validation

On 26.09.23 12:04, Maksim Davydov wrote: Could you add a comment into the commit message why ee_data must be bigger than ee_info? As I understand, in this case ee_data is lower bound and ee_info is upper bound of notification: https://docs.kernel.org/networking/msg_zerocopy.html#notification-

Re: [PATCH v4 13/14] MAINTAINERS: add maintainer of simpletrace.py

> You're welcome to be the maintainer. I haven't touched it in years. > > When you have reviewed future simpletrace.py patches you can either post > your Reviewed-by and I'll include them in my tracing pull requests, or > you could send pull requests to the qemu.git maintainer yourself > (requir

[PATCH] mailmap: Fix Andrey Drobyshev author email

From: Andrey Drobyshev This fixes authorship of commits 2848289168, 52b10c9c0c as the mailing list rewrote the "From:" field in the corresponding patches. See commit 3bd2608db7 ("maint: Add .mailmap entries for patches claiming list authorship") for explanation. Signed-off-by: Andrey Drobyshev

Re: [PATCH 01/12] hw/core/loader: load_at(): check size

On Mon, 25 Sept 2023 at 20:41, Vladimir Sementsov-Ogievskiy wrote: > > This @size parameter often comes from fd. We'd better check it before > doing read and allocation. > > Chose 1G as high enough empiric bound. Empirical for who? > Signed-off-by: Vladimir Sementsov-Ogievskiy > --- > hw/core/

[PATCH v5 04/14] simpletrace: changed naming of edict and idtoname to improve readability

From: Mads Ynddal Readability is subjective, but I've expanded the naming of the variables and arguments, to help with understanding for new eyes on the code. Signed-off-by: Mads Ynddal Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Stefan Hajnoczi --- scripts/simpletrace.py | 34 +

[PATCH v5 07/14] simpletrace: define exception and add handling

From: Mads Ynddal Define `SimpleException` to differentiate our exceptions from generic exceptions (IOError, etc.). Adapted simpletrace to support this and output to stderr. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Stefan Hajnoczi Signed-off-by: Mads Ynddal --- scripts/simpletrace.py

[PATCH v5 02/14] simpletrace: annotate magic constants from QEMU code

From: Mads Ynddal It wasn't clear where the constants and structs came from, so I added comments to help. Reviewed-by: Stefan Hajnoczi Signed-off-by: Mads Ynddal --- scripts/simpletrace.py | 5 + 1 file changed, 5 insertions(+) diff --git a/scripts/simpletrace.py b/scripts/simpletrace.py

[PATCH v5 00/14] simpletrace: refactor and general improvements

From: Mads Ynddal I wanted to use simpletrace.py for an internal project, so I tried to update and polish the code. Some of the commits resolve specific issues, while some are more subjective. I've tried to divide it into commits so we can discuss the individual changes, and I'm ready to pull th

[PATCH v5 14/14] scripts/analyse-locks-simpletrace.py: changed iteritems() to items()

From: Mads Ynddal Python 3 removed `dict.iteritems()` in favor of `dict.items()`. This means the script currently doesn't work on Python 3. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Stefan Hajnoczi Signed-off-by: Mads Ynddal --- scripts/analyse-locks-simpletrace.py | 2 +- 1 file chan

[PATCH v5 13/14] MAINTAINERS: add maintainer of simpletrace.py

From: Mads Ynddal In my work to refactor simpletrace.py, I noticed that there's no maintainer of it, and has the status of "odd fixes". I'm using it from time to time, so I'd like to maintain the script. I've added myself as reviewer under "Tracing" to be informed of changes that might affect si

[PATCH v5 11/14] simpletrace: move event processing to Analyzer class

From: Mads Ynddal Moved event processing to the Analyzer class to separate specific analyzer logic (like caching and function signatures) from the _process function. This allows for new types of Analyzer-based subclasses without changing the core code. Note, that the fn_cache is important for pe

[PATCH v5 03/14] simpletrace: improve parsing of sys.argv; fix files never closed.

From: Mads Ynddal The arguments extracted from `sys.argv` named and unpacked to make it clear what the arguments are and what they're used for. The two input files were opened, but never explicitly closed. File usage changed to use `with` statement to take care of this. At the same time, ownersh

[PATCH v5 09/14] simpletrace: refactor to separate responsibilities

From: Mads Ynddal Moved event_mapping and event_id_to_name down one level in the function call-stack to keep variable instantiation and usage closer (`process` and `run` has no use of the variables; `read_trace_records` does). Instead of passing event_mapping and event_id_to_name to the bottom o

[PATCH v5 08/14] simpletrace: made Analyzer into context-manager

From: Mads Ynddal Instead of explicitly calling `begin` and `end`, we can change the class to use the context-manager paradigm. This is mostly a styling choice, used in modern Python code. But it also allows for more advanced analyzers to handle exceptions gracefully in the `__exit__` method (not

[PATCH v5 01/14] simpletrace: add __all__ to define public interface

From: Mads Ynddal It was unclear what was the supported public interface. I.e. when refactoring the code, what functions/classes are important to retain. Reviewed-by: Stefan Hajnoczi Signed-off-by: Mads Ynddal --- scripts/simpletrace.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sc

[PATCH v5 10/14] simpletrace: move logic of process into internal function

From: Mads Ynddal To avoid duplicate code depending on input types and to better handle open/close of log with a context-manager, we move the logic of process into _process. Reviewed-by: Stefan Hajnoczi Signed-off-by: Mads Ynddal --- scripts/simpletrace.py | 26 ++ 1 f

[PATCH v5 12/14] simpletrace: added simplified Analyzer2 class

From: Mads Ynddal By moving the dynamic argument construction to keyword-arguments, we can remove all of the specialized handling, and streamline it. If a tracing method wants to access these, they can define the kwargs, or ignore it be placing `**kwargs` at the end of the function's arguments li

[PATCH v5 06/14] simpletrace: improved error handling on struct unpack

From: Mads Ynddal A failed call to `read_header` wouldn't be handled the same for the two different code paths (one path would try to use `None` as a list). Changed to raise exception to be handled centrally. This also allows for easier unpacking, as errors has been filtered out. Reviewed-by: Ph

[PATCH v5 05/14] simpletrace: update code for Python 3.11

From: Mads Ynddal The call to `getargspec` was deprecated and in Python 3.11 it has been removed in favor of `getfullargspec`. `getfullargspec` is compatible with QEMU's requirement of at least Python version 3.6. Reviewed-by: Stefan Hajnoczi Reviewed-by: Philippe Mathieu-Daudé Signed-off-by:

[PATCH RFC V2 32/37] target/arm: Add support of *unrealize* ARMCPU during vCPU Hot-unplug

vCPU Hot-unplug will result in QOM CPU object unrealization which will do away with all the vCPU thread creations, allocations, registrations that happened as part of the realization process. This change introduces the ARM CPU unrealize function taking care of exactly that. Note, initialized KVM v

[PATCH RFC V2 33/37] target/arm/kvm: Write CPU state back to KVM on reset

From: Jean-Philippe Brucker When a KVM vCPU is reset following a PSCI CPU_ON call, its power state is not synchronized with KVM at the moment. Because the vCPU is not marked dirty, we miss the call to kvm_arch_put_registers() that writes to KVM's MP_STATE. Force mp_state synchronization. Signed-

Re: [PATCH 02/12] hw/i386/intel_iommu: vtd_slpte_nonzero_rsvd(): reduce magic numbers

On Mon, 25 Sept 2023 at 20:41, Vladimir Sementsov-Ogievskiy wrote: > > Add a constant and clear assertion. The assertion also tells Coverity > that we are not going to overflow the array. > > Signed-off-by: Vladimir Sementsov-Ogievskiy > --- > hw/i386/intel_iommu.c | 11 --- > 1 file cha

[PATCH RFC V2 34/37] target/arm/kvm, tcg: Register/Handle SMCCC hypercall exits to VMM/Qemu

From: Author Salil Mehta Add registration and Handling of HVC/SMC hypercall exits to VMM Co-developed-by: Salil Mehta Signed-off-by: Salil Mehta Co-developed-by: Jean-Philippe Brucker Signed-off-by: Jean-Philippe Brucker Signed-off-by: Salil Mehta --- target/arm/arm-powerctl.c | 51 +

[PATCH RFC V2 35/37] hw/arm: Support hotplug capability check using _OSC method

Physical CPU hotplug results in (un)setting of ACPI _STA.Present bit. AARCH64 platforms do not support physical CPU hotplug. Virtual CPU hotplug support being implemented toggles ACPI _STA.Enabled Bit to achieve hotplug functionality. This is not same as physical CPU hotplug support. In future, if

[PATCH RFC V2 36/37] tcg/mttcg: enable threads to unregister in tcg_ctxs[]

From: Miguel Luis [This patch is just for reference. It has problems as it does not takes care of the TranslationBlocks and their assigned regions during CPU unrealize] When using TCG acceleration in a multi-threaded context each vCPU has its own thread registered in tcg_ctxs[] upon creation and

[PATCH RFC V2 37/37] hw/arm/virt: Expose cold-booted CPUs as MADT GICC Enabled

Hotpluggable CPUs MUST be exposed as 'online-capable' as per the new change. But cold booted CPUs if made 'online-capable' during boot time might not get detected in the legacy OS. Hence, can cause compatibility problems. Original Change Link: https://bugzilla.tianocore.org/show_bug.cgi?id=3706 S

Re: [PATCH v4 12/14] simpletrace: added simplified Analyzer2 class

>> +class Formatter2(Analyzer2): > > Was this class part of the benchmark? It appears to be unused. > >> +def __init__(self): >> +self.last_timestamp_ns = None >> + >> +def catchall(self, *rec_args, event, timestamp_ns, pid, event_id): >> +if self.las

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