Re: [PATCH v2 07/20] audio: add Apple Sound Chip (ASC) emulation

Am 09.09.23 um 11:48 schrieb Mark Cave-Ayland: > The Apple Sound Chip was primarily used by the Macintosh II to generate sound > in hardware which was previously handled by the toolbox ROM with software > interrupts. > > Implement both the standard ASC and also the enhanced ASC (EASC) functionality

[PATCH v4 03/21] softmmu: Fix CPUSTATE.nr_cores' calculation

From: Zhuocheng Ding >From CPUState.nr_cores' comment, it represents "number of cores within this CPU package". After 003f230e37d7 ("machine: Tweak the order of topology members in struct CpuTopology"), the meaning of smp.cores changed to "the number of cores in one die", but this commit missed

[PATCH v4 02/21] tests: Rename test-x86-cpuid.c to test-x86-topo.c

From: Zhao Liu The tests in this file actually test the APIC ID combinations. Rename to test-x86-topo.c to make its name more in line with its actual content. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Philippe Mathieu-Daudé Acked-by: Michael S. Tsirkin --- Changes since v3:

[PATCH v4 01/21] i386: Fix comment style in topology.h

From: Zhao Liu For function comments in this file, keep the comment style consistent with other files in the directory. Signed-off-by: Zhao Liu Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Yanan Wang Reviewed-by: Xiaoyao Li Acked-by: Michael S. Tsirkin --- Changes since v3: * Optimized

[PATCH v4 05/21] i386/cpu: Fix i/d-cache topology to core level for Intel CPU

From: Zhao Liu For i-cache and d-cache, current QEMU hardcodes the maximum IDs for CPUs sharing cache (CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits 25:14]) to 0, and this means i-cache and d-cache are shared in the SMT level. This is correct if there's single thread per core, but is

[PATCH v4 07/21] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid()

From: Zhao Liu In cpu_x86_cpuid(), there are many variables in representing the cpu topology, e.g., topo_info, cs->nr_cores/cs->nr_threads. Since the names of cs->nr_cores/cs->nr_threads does not accurately represent its meaning, the use of cs->nr_cores/cs->nr_threads is prone to confusion and m

[PATCH v4 14/21] i386/cpu: Introduce cluster-id to X86CPU

From: Zhuocheng Ding Introduce cluster-id other than module-id to be consistent with CpuInstanceProperties.cluster-id, and this avoids the confusion of parameter names when hotplugging. Following the legacy smp check rules, also add the cluster_id validity into x86_cpu_pre_plug(). Signed-off-by

[PATCH v4 06/21] i386/cpu: Use APIC ID offset to encode cache topo in CPUID[4]

From: Zhao Liu Refer to the fixes of cache_info_passthrough ([1], [2]) and SDM, the CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] should use the nearest power-of-2 integer. The nearest power-of-2 integer can be calculated by pow2ceil() or by using APIC ID offset (like L3 topology using

[PATCH v4 08/21] i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB]

From: Zhao Liu CPUID[0xB] defines SMT, Core and Invalid types, and this leaf is shared by Intel and AMD CPUs. But for extended topology levels, Intel CPU (in CPUID[0x1F]) and AMD CPU (in CPUID[0x8026]) have the different definitions with different enumeration values. Though CPUID[0x8026

[PATCH v4 12/21] i386: Expose module level in CPUID[0x1F]

From: Zhao Liu Linux kernel (from v6.4, with commit edc0a2b595765 ("x86/topology: Fix erroneous smp_num_siblings on Intel Hybrid platforms") is able to handle platforms with Module level enumerated via CPUID.1F. Expose the module level in CPUID[0x1F] if the machine has more than 1 modules. (Tes

[PATCH v4 09/21] i386: Decouple CPUID[0x1F] subleaf with specific topology level

From: Zhao Liu At present, the subleaf 0x02 of CPUID[0x1F] is bound to the "die" level. In fact, the specific topology level exposed in 0x1F depends on the platform's support for extension levels (module, tile and die). To help expose "module" level in 0x1F, decouple CPUID[0x1F] subleaf with sp

[PATCH v4 00/21] Support smp.clusters for x86 in QEMU

From: Zhao Liu Hi list, (CC k...@vger.kernel.org for better browsing.) This is the our v4 patch series, rebased on the master branch at the commit 9ef497755afc2 ("Merge tag 'pull-vfio-20230911' of https://github.com/legoater/qemu into staging"). Comparing with v3 [1], v4 mainly refactors the C

[PATCH v4 20/21] i386: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 25:14]

From: Zhao Liu CPUID[0x801D].EAX[bits 25:14] NumSharingCache: number of logical processors sharing cache. The number of logical processors sharing this cache is NumSharingCache + 1. After cache models have topology information, we can use CPUCacheInfo.share_level to decide which topology le

[PATCH v4 17/21] i386: Add cache topology info in CPUCacheInfo

From: Zhao Liu Currently, by default, the cache topology is encoded as: 1. i/d cache is shared in one core. 2. L2 cache is shared in one core. 3. L3 cache is shared in one die. This default general setting has caused a misunderstanding, that is, the cache topology is completely equated with a sp

[PATCH v4 19/21] i386: Use offsets get NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14]

From: Zhao Liu The commit 8f4202fb1080 ("i386: Populate AMD Processor Cache Information for cpuid 0x801D") adds the cache topology for AMD CPU by encoding the number of sharing threads directly. >From AMD's APM, NumSharingCache (CPUID[0x801D].EAX[bits 25:14]) means [1]: The number of lo

[PATCH v4 13/21] i386: Support module_id in X86CPUTopoIDs

From: Zhuocheng Ding Add module_id member in X86CPUTopoIDs. module_id can be parsed from APIC ID, so also update APIC ID parsing rule to support module level. With this support, the conversions with module level between X86CPUTopoIDs, X86CPUTopoInfo and APIC ID are completed. module_id can be a

[PATCH v4 21/21] i386: Add new property to control L2 cache topo in CPUID.04H

From: Zhao Liu The property x-l2-cache-topo will be used to change the L2 cache topology in CPUID.04H. Now it allows user to set the L2 cache is shared in core level or cluster level. If user passes "-cpu x-l2-cache-topo=[core|cluster]" then older L2 cache topology will be overrode by the new t

[PATCH v4 16/21] hw/i386/pc: Support smp.clusters for x86 PC machine

From: Zhuocheng Ding As module-level topology support is added to X86CPU, now we can enable the support for the cluster parameter on PC machines. With this support, we can define a 5-level x86 CPU topology with "-smp": -smp cpus=*,maxcpus=*,sockets=*,dies=*,clusters=*,cores=*,threads=*. Additio

[PATCH v4 11/21] i386: Support modules_per_die in X86CPUTopoInfo

From: Zhuocheng Ding Support module level in i386 cpu topology structure "X86CPUTopoInfo". Since x86 does not yet support the "clusters" parameter in "-smp", X86CPUTopoInfo.modules_per_die is currently always 1. Therefore, the module level width in APIC ID, which can be calculated by "apicid_bit

[PATCH v4 10/21] i386: Introduce module-level cpu topology to CPUX86State

From: Zhuocheng Ding smp command has the "clusters" parameter but x86 hasn't supported that level. "cluster" is a CPU topology level concept above cores, in which the cores may share some resources (L2 cache or some others like L3 cache tags, depending on the Archs) [1][2]. For x86, the resource

[PATCH v4 04/21] hw/cpu: Update the comments of nr_cores and nr_dies

From: Zhao Liu In the nr_threads' comment, specify it represents the number of threads in the "core" to avoid confusion. Also add comment for nr_dies in CPUX86State. Signed-off-by: Zhao Liu --- Changes since v3: * The new patch split out of CPUSTATE.nr_cores' fix. (Xiaoyao) --- include/hw/co

[PATCH v4 15/21] tests: Add test case of APIC ID for module level parsing

From: Zhuocheng Ding After i386 supports module level, it's time to add the test for module level's parsing. Signed-off-by: Zhuocheng Ding Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Yanan Wang Acked-by: Michael S. Tsirkin --- tests/unit/test-x86-t

[PATCH v4 18/21] i386: Use CPUCacheInfo.share_level to encode CPUID[4]

From: Zhao Liu CPUID[4].EAX[bits 25:14] is used to represent the cache topology for Intel CPUs. After cache models have topology information, we can use CPUCacheInfo.share_level to decide which topology level to be encoded into CPUID[4].EAX[bits 25:14]. And since maximum_processor_id (original

Re: [QEMU PATCH v4 10/13] virtio-gpu: Resource UUID

On 2023/09/13 23:18, Albert Esteve wrote: On Wed, Sep 13, 2023 at 3:43 PM Akihiko Odaki > wrote: On 2023/09/13 21:58, Albert Esteve wrote: > > > On Wed, Sep 13, 2023 at 2:22 PM Akihiko Odaki mailto:akihiko.od...@daynix.com> >

Re: [PATCH v11 6/9] gfxstream + rutabaga: add initial support for gfxstream

Am 14. September 2023 04:38:51 UTC schrieb Gurchetan Singh : >On Wed, Sep 13, 2023 at 4:58 AM Bernhard Beschow wrote: > >> >> >> Am 23. August 2023 01:25:38 UTC schrieb Gurchetan Singh < >> gurchetansi...@chromium.org>: >> >This adds initial support for gfxstream and cross-domain. Both >> >fe

Re: [PATCH v4 04/21] hw/cpu: Update the comments of nr_cores and nr_dies

On 14/9/23 09:21, Zhao Liu wrote: From: Zhao Liu In the nr_threads' comment, specify it represents the number of threads in the "core" to avoid confusion. Also add comment for nr_dies in CPUX86State. Signed-off-by: Zhao Liu --- Changes since v3: * The new patch split out of CPUSTATE.nr_cor

[PATCH v3] hw/cxl: Fix out of bound array access

According to cxl_interleave_ways_enc(), fw->num_targets is allowed to be up to 16. This also corresponds to CXL specs. So, the fw->target_hbs[] array is iterated from 0 to 15. But it is statically declared of length 8. Thus, out of bound array access may occur. Found by Linux Verification Center (

Re: [PATCH v4 03/21] softmmu: Fix CPUSTATE.nr_cores' calculation

Hi, On 14/9/23 09:21, Zhao Liu wrote: From: Zhuocheng Ding From CPUState.nr_cores' comment, it represents "number of cores within this CPU package". After 003f230e37d7 ("machine: Tweak the order of topology members in struct CpuTopology"), the meaning of smp.cores changed to "the number of c

Re: [PATCH v4 10/21] i386: Introduce module-level cpu topology to CPUX86State

On 14/9/23 09:21, Zhao Liu wrote: From: Zhuocheng Ding smp command has the "clusters" parameter but x86 hasn't supported that level. "cluster" is a CPU topology level concept above cores, in which the cores may share some resources (L2 cache or some others like L3 cache tags, depending on the A

Re: [PATCH v4 21/21] i386: Add new property to control L2 cache topo in CPUID.04H

On 14/9/23 09:21, Zhao Liu wrote: From: Zhao Liu The property x-l2-cache-topo will be used to change the L2 cache topology in CPUID.04H. Now it allows user to set the L2 cache is shared in core level or cluster level. If user passes "-cpu x-l2-cache-topo=[core|cluster]" then older L2 cache to

Re: [PATCH 4/5] elf2dmp: use Linux mmap with MAP_NORESERVE when possible

On 2023/09/14 7:46, Viktor Prutyanov wrote: Glib's g_mapped_file_new maps file with PROT_READ|PROT_WRITE and MAP_PRIVATE. This leads to premature physical memory allocation of dump file size on Linux hosts and may fail. On Linux, mapping the file with MAP_NORESERVE limits the allocation by availa

Re: [PATCH v5 3/3] hw/nvme: add nvme management interface model

Hi Klaus, On Thu, 2023-09-14 at 08:51 +0200, Klaus Jensen wrote: > On Sep 12 13:50, Andrew Jeffery wrote: > > Hi Klaus, > > > > On Tue, 2023-09-05 at 10:38 +0200, Klaus Jensen wrote: > > > > > > > > +static void nmi_handle_mi_config_get(NMIDevice *nmi, NMIRequest > > > > *request) > > > > +{ > >

[PATCH v3 2/3] linux-user/syscall.c: do_ppoll: consolidate and fix the forgotten unlock_user

in do_ppoll we've one place where unlock_user isn't done at all, while other places use 0 for the size of the area being unlocked instead of the actual size. Instead of open-coding calls to unlock_user(), jump to the end of this function and do a single call to unlock there. Note: original code c

[PATCH v3 3/3] linux-user/syscall.c: do_ppoll: eliminate large alloca

do_ppoll() in linux-user/syscall.c uses alloca() to allocate an array of struct pullfds on the stack. The only upper boundary for number of entries for this array is so that whole thing fits in INT_MAX. This is definitely too much for stack allocation. Use heap allocation when large number of en

[PATCH v3 0/3] linux-user/syscall.c: do_ppoll: eliminate large alloca

This is a v3 patch (now patchset) which eliminates guest-controlled alloca from linux-user:poll. I now split out 2 unrelated preparational changes into its own patches, for easy review. The small optmization which were here in v1 is still there. In huge number of use cases, poll() et all are cal

[PATCH v3 1/3] linux-user/syscall.c: do_ppoll: simplify time64 host<=>target conversion expressions

replace if (time64) { time64-expr } else { time32-expr } expressions which are difficult to read with a much shorter and easier to read arithmetic-if constructs. Signed-off-by: Michael Tokarev --- linux-user/syscall.c | 27 +-- 1 file changed, 9 insertions(+), 18 deletion

Re: [PATCH] vhost: Add a defensive check in vhost_commit against wrong deallocation

Hi Jason, On 9/14/23 05:46, Jason Wang wrote: > On Wed, Sep 13, 2023 at 3:47 PM Eric Auger wrote: >> In vhost_commit(), it may happen that dev->mem_sections and >> dev->tmp_sections are equal, in which case, unconditionally >> freeing old_sections at the end of the function will also free >> dev-

Re: [PATCH 3/5] elf2dmp: introduce merging of physical memory runs

On 2023/09/14 7:46, Viktor Prutyanov wrote: DMP supports 42 physical memory runs at most. So, merge adjacent physical memory ranges from QEMU ELF when possible to minimize total number of runs. Signed-off-by: Viktor Prutyanov --- contrib/elf2dmp/main.c | 56 +++

Re: [PATCH 5/5] elf2dmp: rework PDB_STREAM_INDEXES::segments obtaining

On 2023/09/14 7:46, Viktor Prutyanov wrote: PDB for Windows 11 kernel has slightly different structure compared to previous versions. Since elf2dmp don't use the other fields, copy only 'segments' field from PDB_STREAM_INDEXES. I suggest replacing the sidx member of struct pdb_reader with a sin

Re: [PATCH v2 08/20] asc: generate silence if FIFO empty but engine still running

On 9/9/23 11:48, Mark Cave-Ayland wrote: MacOS (un)helpfully leaves the FIFO engine running even when all the samples have been written to the hardware, and expects the FIFO status flags and IRQ to be updated continuously. There is an additional problem in that not all audio backends guarante

[RFC PATCH v2 2/2] hw/riscv: hart: allow other cpu instance

From: Nikita Shubin Allow using instances derivative from RISCVCPU Signed-off-by: Nikita Shubin --- hw/riscv/riscv_hart.c | 20 include/hw/riscv/riscv_hart.h | 2 +- 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/r

[RFC PATCH v2 0/2] hw/riscv: hart: allow other cpu instance

From: Nikita Shubin Currently it is not possible to overload instance of RISCVCPU, i.e. something like this: static const TypeInfo riscv_cpu_type_infos[] = { { .name = TYPE_ANOTHER_RISCV_CPU, .parent = TYPE_RISCV_CPU, .instance_size = sizeof(MyCPUState), .in

[RFC PATCH v2 1/2] hw/riscv: hart: replace array access with qemu_get_cpu()

From: Nikita Shubin Replace all RISCVHartArrayState->harts[idx] with qemu_get_cpu()/cpu_by_arch_id(). cpu_index is guaranteed to be continuus by cpu_get_free_index(), so they can be accessed in same order they were added. "Hart IDs might not necessarily be numbered contiguously in a multiproces

Re: [PATCH v4 1/2] tests: bump libvirt-ci for libasan and libxdp

On Wed, Sep 13, 2023 at 08:34:36PM +0200, Ilya Maximets wrote: > This pulls in the fixes for libasan version as well as support for > libxdp that will be used for af-xdp netdev in the next commits. > > Signed-off-by: Ilya Maximets > --- > tests/docker/dockerfiles/debian-amd64-cross.docker | 2

Re: [PATCH v4 2/2] net: add initial support for AF_XDP network backend

On Wed, Sep 13, 2023 at 08:34:37PM +0200, Ilya Maximets wrote: > AF_XDP is a network socket family that allows communication directly > with the network device driver in the kernel, bypassing most or all > of the kernel networking stack. In the essence, the technology is > pretty similar to netmap

Re: [PULL 00/17] Net patches

On Wed, Sep 13, 2023 at 08:46:42PM +0200, Ilya Maximets wrote: > On 9/8/23 16:15, Daniel P. Berrangé wrote: > > On Fri, Sep 08, 2023 at 04:06:35PM +0200, Ilya Maximets wrote: > >> On 9/8/23 14:15, Daniel P. Berrangé wrote: > >>> On Fri, Sep 08, 2023 at 02:00:47PM +0200, Ilya Maximets wrote: >

Re: [PATCH v3 3/3] linux-user/syscall.c: do_ppoll: eliminate large alloca

On Thu, Sep 14, 2023 at 10:43:37AM +0300, Michael Tokarev wrote: > do_ppoll() in linux-user/syscall.c uses alloca() to allocate > an array of struct pullfds on the stack. The only upper > boundary for number of entries for this array is so that > whole thing fits in INT_MAX. This is definitely to

Re: [PATCH v3] hw/loongarch: Add virtio-mmio bus support

在 2023/9/11 下午4:59, Tianrui Zhao 写道: Add virtio-mmio bus support for LoongArch, so that devices could be added in the virtio-mmio bus. Signed-off-by: Tianrui Zhao Change-Id: Ib882005106562e0dfe74122a7fa2430fa081bfb2 --- hw/loongarch/Kconfig | 1 + hw/loongarch/acpi-build.c | 25 +

Re: [PATCH v6 52/57] target/loongarch: Implement xvreplve xvinsve0 xvpickve

在 2023/9/14 上午11:16, Richard Henderson 写道: On 9/13/23 19:26, Song Gao wrote: +static bool gen_xvrepl128(DisasContext *ctx, arg_vv_i *a, MemOp mop)   { -    int ofs; -    TCGv_i64 desthigh, destlow, high, low; +    int index = LSX_LEN / (8 * (1 << mop)); -    if (!avail_LSX(ctx)) { -    retur

Re: [PATCH v6 51/57] target/loongarch: Implement xvinsgr2vr xvpickve2gr

在 2023/9/14 上午11:02, Richard Henderson 写道: On 9/13/23 19:26, Song Gao wrote: +static inline int vec_reg_offset(int regno, int index, MemOp mop) +{ +    const uint8_t size = 1 << mop; +    int offs = index * size; + +#if HOST_BIG_ENDIAN +    if (size < 8 ) { +    offs ^ = (8 - size); +    } +

Re: [PATCH v3 3/3] linux-user/syscall.c: do_ppoll: eliminate large alloca

14.09.2023 11:18, Daniel P. Berrangé wrote: On Thu, Sep 14, 2023 at 10:43:37AM +0300, Michael Tokarev wrote: do_ppoll() in linux-user/syscall.c uses alloca() to allocate an array of struct pullfds on the stack. The only upper boundary for number of entries for this array is so that whole thing

Re: [QEMU PATCH v4 10/13] virtio-gpu: Resource UUID

On Thu, Sep 14, 2023 at 9:17 AM Akihiko Odaki wrote: > On 2023/09/13 23:18, Albert Esteve wrote: > > > > > > On Wed, Sep 13, 2023 at 3:43 PM Akihiko Odaki > > wrote: > > > > On 2023/09/13 21:58, Albert Esteve wrote: > > > > > > > > > On Wed, Se

Re: [PATCH] mem/x86: add processor address space check for VM memory

On 14.09.23 07:53, Ani Sinha wrote: On 12-Sep-2023, at 9:04 PM, David Hildenbrand wrote: [...] diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 54838c0c41..d187890675 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -908,9 +908,12 @@ static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64

Re: [PATCH v3] hw/loongarch: Add virtio-mmio bus support

在 2023/9/11 下午4:59, Tianrui Zhao 写道: +static void fdt_add_virtio_mmio_node(LoongArchMachineState *lams) +{ +int i; +MachineState *ms = MACHINE(lams); + +for (i = VIRT_VIRTIO_MMIO_NUM - 1; i >= 0; i--) { +char *nodename; +hwaddr base = VIRT_VIRTIO_MMIO_BASE + i * VIRT_V

[PATCH] target/mips: Fix MSA BZ/BNZ opcodes displacement

The PC offset is *signed*. Cc: qemu-sta...@nongnu.org Reported-by: Sergey Evlashev Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1624 Fixes: c7a9ef7517 ("target/mips: Introduce decode tree bindings for MSA ASE") Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa.decode | 4

Re: [PATCH v1 00/22] vfio: Adopt iommufd

Hi Zhenzhong On 8/30/23 12:37, Zhenzhong Duan wrote: > Hi All, > > As the kernel side iommufd cdev and hot reset feature have been queued, > also hwpt alloc has been added in Jason's for_next branch [1], I'd like > to update a new version matching kernel side update and with rfc flag > removed. Qe

[PATCH] target/mips: Fix TX79 LQ/SQ opcodes

The base register address offset is *signed*. Cc: qemu-sta...@nongnu.org Fixes: 82a9f9 ("target/mips/tx79: Introduce LQ opcode (Load Quadword)") Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/tx79.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mi

RE: [PATCH v1 00/22] vfio: Adopt iommufd

Hi Eric, >-Original Message- >From: Eric Auger >Sent: Thursday, September 14, 2023 5:04 PM >To: Duan, Zhenzhong ; qemu-devel@nongnu.org >Cc: alex.william...@redhat.com; c...@redhat.com; j...@nvidia.com; >nicol...@nvidia.com; Martins, Joao ; >pet...@redhat.com; jasow...@redhat.com; Tian, K

[PATCH] hw/qxl: move check of slot_id before accessing guest_slots

If slot_id >= NUM_MEMSLOTS, buffer overflow is possible. So the check should be upper than d->guest_slots[slot_id] where size of d->guest_slots is NUM_MEMSLOTS. Fixes: e954ea2873 ("qxl: qxl_add_memslot: remove guest trigerrable panics") Signed-off-by: Anastasia Belova --- hw/display/qxl.c | 11 +

[PATCH v6 0/3] hw/{i2c,nvme}: mctp endpoint, nvme management interface model

This adds a generic MCTP endpoint model that other devices may derive from. Also included is a very basic implementation of an NVMe-MI device, supporting only a small subset of the required commands. Since this all relies on i2c target mode, this can currently only be used with an SoC that includ

Re: [PATCH v9 00/12] Add VIRTIO sound card

On Wed, Sep 13, 2023 at 10:33:07AM +0300, Emmanouil Pitsidianakis wrote: This patch series adds an audio device implementing the recent virtio sound spec (1.2) and a corresponding PCI wrapper device. v9 can be found online at: https://gitlab.com/epilys/qemu/-/tree/virtio-snd-v9 Ref 06e6b17186

[PATCH v6 3/3] hw/nvme: add nvme management interface model

From: Klaus Jensen Add the 'nmi-i2c' device that emulates an NVMe Management Interface controller. Initial support is very basic (Read NMI DS, Configuration Get). This is based on previously posted code by Padmakar Kalghatgi, Arun Kumar Agasar and Saurav Kumar. Reviewed-by: Jonathan Cameron S

[PATCH v6 1/3] hw/i2c: add smbus pec utility function

From: Klaus Jensen Add i2c_smbus_pec() to calculate the SMBus Packet Error Code for a message. Reviewed-by: Jonathan Cameron Signed-off-by: Klaus Jensen --- hw/i2c/smbus_master.c | 26 ++ include/hw/i2c/smbus_master.h | 2 ++ 2 files changed, 28 insertions(+)

[PATCH v6 2/3] hw/i2c: add mctp core

From: Klaus Jensen Add an abstract MCTP over I2C endpoint model. This implements MCTP control message handling as well as handling the actual I2C transport (packetization). Devices are intended to derive from this and implement the class methods. Parts of this implementation is inspired by code

Re: [PATCH v9 00/12] Add VIRTIO sound card

On Thu, 14 Sep 2023 12:54, Stefano Garzarella wrote: We are seeing something strange with the virtio-sound Linux driver. It seems that the driver modifies the buffers after exposing them to the device via the avail ring. I need more information about this bug. What is the unexpected behavior

Re: [sdl-qemu] [PATCH 0/1] There are no checks, virDomainChrSourceDefNew can return 0

CC-ing qemu-devel with a patch solely for libvirt doesn't make sense. Also 'libvirt-security' list is private and is is intended as a first contact list for stuff to be embargoed. It makes little sense to include it when posting to the public 'libvir-list'. On Thu, Sep 14, 2023 at 09:44:13 +,

Re: [PATCH v2 07/24] accel/tcg: Validate placement of CPUNegativeOffsetState

On 9/14/23 04:44, Richard Henderson wrote: Verify that the distance between CPUNegativeOffsetState and CPUArchState is no greater than any alignment requirements. Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/include/e

Re: [sdl-qemu] [PATCH 1/1] No checks, dereferencing possible

On Thu, Sep 14, 2023 at 09:44:16 +, Миронов Сергей Владимирович wrote: > No checks, dereferencing possible. > > > Return value of a function 'virDomainChrSourceDefNew' > is dereferenced at qemu_command.c without checking > for NULL, but it is usually checked for this function. This descripti

Re: [PATCH v9 00/12] Add VIRTIO sound card

On Thu, Sep 14, 2023 at 01:02:05PM +0300, Manos Pitsidianakis wrote: On Thu, 14 Sep 2023 12:54, Stefano Garzarella wrote: We are seeing something strange with the virtio-sound Linux driver. It seems that the driver modifies the buffers after exposing them to the device via the avail ring. I n

Re: [PATCH v2 08/24] accel/tcg: Move CPUNegativeOffsetState into CPUState

On 9/14/23 04:44, Richard Henderson wrote: Retain the separate structure to emphasize its importance. Enforce CPUArchState always follows CPUState without padding. Signed-off-by: Richard Henderson --- include/exec/cpu-all.h| 22 +- include/hw/core/cpu.h | 14 +++

Re: [PATCH 11/11] qdev: Rework array properties based on list visitor

On Fri, 8 Sept 2023 at 15:37, Kevin Wolf wrote: > > Until now, array properties are actually implemented with a hack that > uses multiple properties on the QOM level: a static "foo-len" property > and after it is set, dynamically created "foo[i]" properties. > > In external interfaces (-device on

Re: [PATCH v2 09/24] accel/tcg: Remove CPUState.icount_decr_ptr

On 9/14/23 04:44, Richard Henderson wrote: We can now access icount_decr directly. Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 1 - include/hw/core/cpu.h | 2 -- hw/core/cpu-common.c | 4 ++-- 3 files changed, 2 insertions(+), 5 deletions(-) diff --git a/include/exe

Re: [PATCH v2 13/24] accel/tcg: Replace CPUState.env_ptr with cpu_env()

On 9/14/23 04:44, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 1 - include/hw/core/cpu.h| 9 ++--- target/arm/common-semi-target.h | 2 +- accel/tcg/cpu-exec.c | 8 accel/tcg/cp

Re: [PATCH v2 15/24] accel/tcg: Remove env_neg()

On 9/14/23 04:44, Richard Henderson wrote: Replace the single use within env_tlb() and remove. Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 13 + 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index

Re: [PATCH v2 16/24] tcg: Remove TCGContext.tlb_fast_offset

On 9/14/23 04:44, Richard Henderson wrote: Now that there is no padding between CPUNegativeOffsetState and CPUArchState, this value is constant across all targets. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 1 - accel/tcg/translate-all.c | 2 -- tcg/tcg.c

Re: [PATCH v2 02/24] accel/tcg: Move CPUTLB definitions from cpu-defs.h

On 9/14/23 04:44, Richard Henderson wrote: Accept that we will consume space in CPUState for CONFIG_USER_ONLY, since we cannot test CONFIG_SOFTMMU within hw/core/cpu.h. Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 150 include/hw/cor

Re: [PATCH] vdpa net: zero vhost_vdpa iova_tree pointer at cleanup

QE tested this patch with real nic,guest can works well after cancelling migration. Tested-by: Lei Yang On Thu, Sep 14, 2023 at 11:23 AM Jason Wang wrote: > > On Wed, Sep 13, 2023 at 8:34 PM Eugenio Pérez wrote: > > > > Not zeroing it causes a SIGSEGV if the live migration is cancelled, at > >

Re: [PATCH v3 3/3] linux-user/syscall.c: do_ppoll: eliminate large alloca

14.09.2023 11:26, Michael Tokarev wrote: 14.09.2023 11:18, Daniel P. Berrangé wrote: .. -    struct pollfd *pfd = NULL; +    struct pollfd *pfd = NULL, *heap_pfd = NULL; g_autofree struct pollfd *heap_pdf = NULL; ...   out: +    g_free(heap_pfd); This can be dropped with g_autofree usage

Re: [PATCH v3 3/3] linux-user/syscall.c: do_ppoll: eliminate large alloca

On Thu, Sep 14, 2023 at 02:05:21PM +0300, Michael Tokarev wrote: > 14.09.2023 11:26, Michael Tokarev wrote: > > 14.09.2023 11:18, Daniel P. Berrangé wrote: > .. > > > > -    struct pollfd *pfd = NULL; > > > > +    struct pollfd *pfd = NULL, *heap_pfd = NULL; > > > > > > g_autofree struct pollfd *h

[PATCH 2/2] iotests: add new test case for image streaming

Check if we can list named block nodes when the block-stream is finalized but not yet dismissed This previously led to a crash Signed-off-by: Andrey Zhadchenko --- tests/qemu-iotests/030 | 17 + tests/qemu-iotests/030.out | 4 ++-- 2 files changed, 19 insertions(+), 2 deleti

[PATCH 0/2] block: do not try to list nearly-dropped filters

QEMU crashes on QMP command 'query-named-block-nodes' if we have finalized but not dismissed block job with filter, for example block-stream. This happens because the filter no longer has references from which QEMU can query block info. Skip such filters while listing block nodes. This patchset al

[PATCH 1/2] block: do not try to list nearly-dropped filters

When the block job ends, it removes filter from the tree. However the last reference to filter bds is dropped when the job is destroyed. So when we have finalized but not dismissed job, if we try to 'query-named-block-nodes', QEMU will stumble upon a half-dead filter and crash, since the filter now

Re: [PATCH] mem/x86: add processor address space check for VM memory

> On 14-Sep-2023, at 2:07 PM, David Hildenbrand wrote: > > On 14.09.23 07:53, Ani Sinha wrote: >>> On 12-Sep-2023, at 9:04 PM, David Hildenbrand wrote: >>> >>> [...] >>> > diff --git a/hw/i386/pc.c b/hw/i386/pc.c > index 54838c0c41..d187890675 100644 > --- a/hw/i386/pc.c > +

[risu PATCH v3 5/7] s390x: Update the configure script for s390x support

Auto-detect s390x hosts and add s390x information to the help text. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Thomas Huth --- configure | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/configure b/configure index ca2d7db..2f7c580 100755 --- a/configure +++ b/confi

[risu PATCH v3 3/7] s390x: Add simple s390x.risu file

This only adds a limited set of s390x instructions for initial testing. More instructions will be added later. Signed-off-by: Thomas Huth --- s390x.risu | 81 ++ 1 file changed, 81 insertions(+) create mode 100644 s390x.risu diff --git a/s390

[risu PATCH v3 2/7] s390x: Add basic s390x support to the C code

With these changes, it is now possible to compile the "risu" binary for s390x hosts. Signed-off-by: Thomas Huth --- risu_reginfo_s390x.c | 140 +++ risu_reginfo_s390x.h | 25 risu_s390x.c | 51 test_s390x.S | 53

[risu RFC PATCH v3 7/7] Add a travis.yml file for testing RISU in the Travis-CI

Travis-CI offers native build machines for aarch64, ppc64le and s390x, so this is very useful for testing RISU on these architectures. While compiling works fine for all architectures, running the binary currently only works for s390x (the aarch64 runner reports a mismatch when comparing the regist

[risu PATCH v3 6/7] build-all-archs: Add s390x to the script that builds all architectures

To avoid regressions, let's check s390x also via this file. Suggested-by: Peter Maydell Signed-off-by: Thomas Huth --- build-all-archs | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/build-all-archs b/build-all-archs index e5dcfc8..e89851b 100755 --- a/build-all-archs +++

[risu PATCH v3 0/7] Add support for s390x to RISU

Hi Peter! Here are some patches that add basic support for s390x to RISU. It's still quite limited, e.g. no support for load/store memory operations yet, but the basics with simple 16-bit or 32-bit instructions work *now* already fine. (I'm also already experimenting in extending RISU to support

[risu PATCH v3 1/7] Pass siginfo_t->si_addr to the reginfo_init() function

On s390x, we need the si_addr from the siginfo_t to get to the address of the illegal instruction (the PSW address in the ucontext_t is already pointing to the next instruction there). So let's prepare for that situation and pass the si_addr to the reginfo_init() function everywhere. Signed-off-by

[risu PATCH v3 4/7] s390x: Add basic risugen perl module for s390x

This implements support for simple 16-bit and 32-bit instructions. Support for 48-bit instructions and support for load/store memory instructions is not implemented yet. Signed-off-by: Thomas Huth --- risugen_s390x.pm | 186 +++ 1 file changed, 186 ins

Re: [PATCH] mem/x86: add processor address space check for VM memory

We requested a to hotplug a maximum of "8 GiB", and sized the area slightly larger to allow for some flexibility when it comes to placing DIMMs in that "device-memory" area. Right but here in this example you do not hot plug memory while the VM is running. We can hot plug 8G yes, but the memory

Re: [PULL 14/14] ui: add precondition for dpy_get_ui_info()

On Tue, Sep 12, 2023 at 02:46:48PM +0400, marcandre.lur...@redhat.com wrote: > From: Marc-André Lureau > > Ensure that it only get called when dpy_ui_info_supported(). The > function should always return a result. There should be a non-null > console or active_console. Empirically that does not

Re: [PATCH v2 0/3] docs: update x86 CPU model ABI matrix docs

Ping for review please. This series still applies to git master. On Tue, Jul 18, 2023 at 10:26:28AM +0100, Daniel P. Berrangé wrote: > Changed in v2: > > - Tweaked commit messages > - Also add GraniteRapids CPU model > > Daniel P. Berrangé (3): > scripts: drop comment about autogenerated CPU

Re: [PATCH 11/11] qdev: Rework array properties based on list visitor

Am 14.09.2023 um 12:24 hat Peter Maydell geschrieben: > On Fri, 8 Sept 2023 at 15:37, Kevin Wolf wrote: > > > > Until now, array properties are actually implemented with a hack that > > uses multiple properties on the QOM level: a static "foo-len" property > > and after it is set, dynamically crea

Re: [PATCH v3 2/5] test-bdrv-drain: avoid race with BH in IOThread drain test

On Wed, Sep 13, 2023 at 11:08:54AM -0500, Eric Blake wrote: > On Tue, Sep 12, 2023 at 07:10:34PM -0400, Stefan Hajnoczi wrote: > > This patch fixes a race condition in test-bdrv-drain that is difficult > > to reproduce. test-bdrv-drain sometimes fails without an error message > > on the block pull

[RFC PATCH 0/3] Refactor PPI logic/definitions for virt/sbsa-ref

While reviewing Marcin's patch this morning, cross referencing different specifications and looking at various places around the source code in order to convinced myself he really hadn't missed something out (the existing plumbing made it *so* clean to add), my brain broke slightly at keeping track

[RFC PATCH 3/3] hw/arm/sbsa-ref: use bsa.h for PPI definitions

Use the private peripheral interrupt definitions from bsa.h instead of defining them locally. Refactor to use PPI() to convert from INTID macro where necessary. Signed-off-by: Leif Lindholm --- hw/arm/sbsa-ref.c | 24 +++- 1 file changed, 11 insertions(+), 13 deletions(-) di

[RFC PATCH 1/3] include/hw/arm: move BSA definitions to bsa.h

virt.h defines a number of IRQs that are ultimately described by Arm's Base System Architecture specification. Move these to a dedicated header so that they can be reused by other platforms that do the same. Include that header from virt.h to minimise churn. Signed-off-by: Leif Lindholm --- incl

[RFC PATCH 2/3] {include/}hw/arm: refactor BSA/virt PPI logic

GIC Private Peripheral Interrupts (PPI) are defined as GIC INTID 16-31. As in, PPI0 is INTID16 .. PPI15 is INTID31. Arm's Base System Architecture specification (BSA) lists the mandated and recommended private interrupt IDs by INTID, not by PPI index. But current definitions in qemu define them by

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