[PATCH 0/8] ACPI: X86 AML generation and GPE tracing cleanup

This series contains changes from my effort to bring the VIA south bridges to the PC machine [1]. The first part of the series resolves the AcpiCpuAmlIfClass::madt_cpu virtual method which frees ACPI controllers from worrying about CPU AML generation. The second part minimizes an Intel-specific ass

[PATCH 3/8] hw/acpi/acpi_dev_interface: Remove now unused madt_cpu virtual method

This virtual method was always set to the x86-specific pc_madt_cpu_entry(), even in piix4 which is also used in MIPS. The previous changes use pc_madt_cpu_entry() otherwise, so madt_cpu can be dropped. Since pc_madt_cpu_entry() is now only used in x86-specific code, the stub in hw/acpi/acpi-x86-st

[PATCH 1/8] hw/i386/acpi-build: Use pc_madt_cpu_entry() directly

This is x86-specific code, so there is no advantage in using pc_madt_cpu_entry() behind an architecture-agnostic interface. Signed-off-by: Bernhard Beschow --- hw/i386/acpi-common.h | 3 +-- hw/i386/acpi-build.c | 3 +-- hw/i386/acpi-common.c | 5 ++--- hw/i386/acpi-microvm.c | 3 +-- 4 file

[PATCH 5/8] hw/i386: Remove now redundant TYPE_ACPI_GED_X86

Now that TYPE_ACPI_GED_X86 doesn't assign AcpiDeviceIfClass::madt_cpu any more it is the same as TYPE_ACPI_GED. Signed-off-by: Bernhard Beschow --- include/hw/acpi/generic_event_device.h | 2 -- hw/i386/generic_event_device_x86.c | 27 -- hw/i386/microvm.c

[PATCH 6/8] hw/i386/acpi-build: Determine SMI command port just once

The SMI command port is currently hardcoded by means of the ACPI_PORT_SMI_CMD macro. This hardcoding is Intel specific and doesn't match VIA, for example. There is already the AcpiFadtData::smi_cmd attribute which is used when building the FADT. Let's also use it when building the DSDT which confin

Re: [PATCH for-8.2 v3 5/6] vfio/migration: Add P2P support for VFIO migration

Test result of multiple Mellanox CX-7 VFs migration: PASS [1] create two VFs and bind them to mlx5_vfio_pci driver [2] start a VM with two VFs [3] migrate the VM [4] check if the VM works well Tested-by: YangHang Liu Best Regards, YangHang Liu On Wed, Aug 2, 2023 at 4:43 PM Cédric Le Goater

[PATCH 4/8] hw/acpi/acpi_dev_interface: Remove now unused #include "hw/boards.h"

The "hw/boards.h" is unused since the previous commit. Since its removal requires include fixes in various unrelated files to keep the code compiling it has been split in a dedicated commit. Signed-off-by: Bernhard Beschow --- hw/acpi/hmat.h | 3 ++- include/hw/acpi/acpi_de

[PATCH 7/8] hw/acpi: Trace GPE access in all device models, not just PIIX4

Signed-off-by: Bernhard Beschow Reviewed-by: Igor Mammedov Reviewed-by: Philippe Mathieu-Daudé --- hw/acpi/core.c | 5 + hw/acpi/piix4.c | 3 --- hw/acpi/trace-events | 8 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/hw/acpi/core.c b/hw/acpi/core.c inde

[PATCH 8/8] hw/acpi/core: Trace enable and status registers of GPE separately

The bit positions of both registers are related. Tracing the registers independently results in the same offsets across these registers which eases debugging. Signed-off-by: Bernhard Beschow Acked-by: Igor Mammedov --- hw/acpi/core.c | 10 +++--- hw/acpi/trace-events | 6 -- 2 fi

[PATCH 2/8] hw/acpi/cpu: Have build_cpus_aml() take a build_madt_cpu_fn callback

build_cpus_aml() is architecture independent but needs to create architecture- specific CPU AML. So far this was achieved by using a virtual method from TYPE_ACPI_DEVICE_IF. However, build_cpus_aml() would resolve this interface from global (!) state. This makes it quite incomprehensible where this

Re: [PATCH for-8.2 v3 0/6] vfio/migration: Add P2P support for VFIO migration

Test result of multiple Mellanox CX-7 VFs migration: PASS [1] create two VFs and bind them to mlx5_vfio_pci driver [2] start a VM with two VFs [3] migrate the VM [4] check if the VM works well Tested-by: YangHang Liu Best Regards, YangHang Liu On Wed, Aug 2, 2023 at 4:16 PM Avihai Horon wrote

Re: [PATCH v1 0/7] Introduce model for IBM's FSP

Hi Ninad, On Fri, 25 Aug 2023 at 20:51, Ninad Palsule wrote: > > Hello, > > Please review the patch-set. > > This is a first step towards introducing model for IBM's Flexible > Service Interface. The full functionality will be implemented over the > time. You have a typo in the subject, I think

[PATCH] accel/kvm: Fix dirty reaper thread crash

From: alloc kvm_dirty_ring_reaper_init is called much early than vcpu creation, so it's possibe the reaper get a crash before vcpu mmap kvm_dirty_gfns. Add a machine done notifier to ensure dirty reaper get run after vcpu inited. Signed-off-by: alloc --- accel/kvm/kvm-all.c | 9 +++-- 1 fi

Re: [PATCH v1 1/7] hw/fsi: Introduce IBM's Local bus

On Fri, 25 Aug 2023 at 20:31, Ninad Palsule wrote: > > This is a part of patchset where IBM's Flexible Service Interface is > introduced. > > The LBUS is modelled to maintain the qdev bus hierarchy and to take > advantage of the object model to automatically generate the CFAM > configuration block

[RFC PATCH v2 1/6] cpu: Add new API cpu_type_by_name

cpu_type_by_name is used to get the cpu type name from the command line -cpu. Currently it is only used by parse_cpu_option. In the next patch, it will be used by other cpu query functions. Signed-off-by: LIU Zhiwei --- cpu.c | 31 +++ 1 file changed, 19 insertions(+

[RFC PATCH v2 0/6] Add API for list cpu extensions

Some times we want to know what is the really mean of one cpu option. For example, in RISC-V, we usually specify a cpu in this way: -cpu rv64,v=on If we don't look into the source code, we can't get the ISA extensions of this -cpu command line. In this patch set, we add one list_cpu_props API for

[RFC PATCH v2 2/6] target/riscv: Add API list_cpu_props

This API used for output current configuration for one specified CPU. Currently only RISC-V frontend implements this API. Signed-off-by: LIU Zhiwei --- cpu.c | 8 include/exec/cpu-common.h | 1 + target/riscv/cpu.c| 14 ++ target/riscv/cpu.h

Re: [RFC PATCH 2/3] target/riscv: Add API list_cpu_props

On 2023/8/25 21:46, Daniel Henrique Barboza wrote: On 8/25/23 09:16, LIU Zhiwei wrote: This API used for output current configuration for one specified CPU. Currently only RISC-V frontend implements this API. Signed-off-by: LIU Zhiwei ---   cpu.c |  8   include

[RFC PATCH v2 3/6] softmmu/vl: Add qemu_cpu_opts QemuOptsList

This make the cpu works the similar way like the -device option. For device option, """ ./qemu-system-riscv64 -device e1000,help e1000 options: acpi-index=- (default: 0) addr= - Slot and optional function number, example: 06.0 or 06 (default: -1) autonegotiation= - on/off (de

[RFC PATCH v2 4/6] target/riscv: Add default value for misa property

Before this patch, " qemu-system-riscv64 -device rv64-riscv-cpu,v=true,help ... v= - Vector operations ... " After this patch, " v= - Vector operations (default: false) " Signed-off-by: LIU Zhiwei --- target/riscv/cpu.c | 12 ++-- 1 file changed, 6 insertio

[RFC PATCH v2 5/6] target/riscv: Add defalut value for string property

Before this patch, """ qemu-system-riscv64 -device rv64-riscv-cpu,v=true,help ... vext_spec= ... """ After this patch, """ vext_spec=- (default: "v1.0") """ Signed-off-by: LIU Zhiwei --- hw/core/qdev-prop-internal.h | 2 ++ hw/core/qdev-properties.c| 7 +++ include/hw/qdev-pr

Re: [PATCH v1 7/7] hw/arm: Hook up FSI module in AST2600

On Fri, 25 Aug 2023 at 20:35, Ninad Palsule wrote: > > This patchset introduces IBM's Flexible Service Interface(FSI). > > Time for some fun with inter-processor buses. FSI allows a service > processor access to the internal buses of a host POWER processor to > perform configuration or debugging.

[RFC PATCH v2 6/6] linux-user: Move qemu_cpu_opts to cpu.c

Make qemu_cpu_opts also works for linux user mode. Notice, currently qdev monitor is not included in linux user mode. We just output current enabled extentions for RISC-V(without the hint to print all properties with -device). With this patch, """ qemu-riscv64 -cpu rv64,help Enabled extensions:

Re: [PATCH v1 0/7] Introduce model for IBM's FSP

Hello Ninad, On 8/25/23 22:30, Ninad Palsule wrote: Hello, Please review the patch-set. This is a first step towards introducing model for IBM's Flexible Service Interface. The full functionality will be implemented over the time. Ninad Palsule (7): hw/fsi: Introduce IBM's Local bus hw/

Re: [PATCH v3 1/3] hw/i2c/aspeed: Fix Tx count and Rx size error in buffer pool mode

On 8/16/23 11:44, Hang Yu wrote: Hello! Thank you for your review!Sorry I forgot to cc other maintainers so I resend this mail. From: "Cédric Le Goater" Date: 2023-08-16 16:32:58 To: Hang Yu ,qemu-devel@nongnu.org Cc: koml...@google.com,pe...@pjd.dev,Peter Maydell ,Andrew Jeffery ,Joel Stan

Re: [PATCH v1 6/7] hw/fsi: Aspeed APB2OPB interface

On Fri, 25 Aug 2023 at 20:31, Ninad Palsule wrote: > > This is a part of patchset where IBM's Flexible Service Interface is > introduced. > > An APB-to-OPB bridge enabling access to the OPB from the ARM core in > the AST2600. Hardware limitations prevent the OPB from being directly > mapped into A

Re: [PATCH v1 4/7] hw/fsi: Introduce IBM's FSI

On Fri, 25 Aug 2023 at 20:44, Ninad Palsule wrote: > > This is a part of patchset where IBM's Flexible Service Interface is > introduced. > > This commit models the FSI bus. CFAM is hanging out of FSI bus. The bus > is model such a way that it is embeded inside the FSI master which is a > bus cont

Re: [PATCH v1 5/7] hw/fsi: IBM's On-chip Peripheral Bus

On Fri, 25 Aug 2023 at 20:35, Ninad Palsule wrote: > > This is a part of patchset where IBM's Flexible Service Interface is > introduced. > > The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in > POWER processors. This now makes an appearance in the ASPEED SoC due > to tight integ

[PATCH] tests/avocado/machine_aspeed.py: Update SDK images

Switch to the latest v8.06 release which introduces interesting changes for the AST2600 I2C and I3C models. Also take the AST2600 A2 images instead of the default since QEMU tries to model The AST2600 A3 SoC. Signed-off-by: Cédric Le Goater --- Requires patches from Hang Yu [1] [1] https

[RESEND PATCH] target/ppc: Fix the order of kvm_enable judgment about kvmppc_set_interrupt()

It's unnecessary for non-KVM accelerators(TCG, for example), to call this function, so change the order of kvm_enable() judgment. The static inline function that returns -1 directly does not work in TCG's situation. Signed-off-by: jianchunfu --- hw/ppc/ppc.c | 8 ++-- target/ppc/kvm.c

Re: [PATCH v2 2/4] qcow2: add configurations for zoned format extension

Markus Armbruster 于2023年8月21日周一 21:13写道： > > Sam Li writes: > > > To configure the zoned format feature on the qcow2 driver, it > > requires following arguments: the device size, zoned profile, > > zoned model, zone size, zone capacity, number of conventional > > zones, limits on zone resources (

Re: [PATCH v2 2/4] qcow2: add configurations for zoned format extension

Stefan Hajnoczi 于2023年8月21日周一 21:31写道： > > On Mon, Aug 14, 2023 at 04:58:00PM +0800, Sam Li wrote: > > diff --git a/block/qcow2.h b/block/qcow2.h > > index f789ce3ae0..3694c8d217 100644 > > --- a/block/qcow2.h > > +++ b/block/qcow2.h > > @@ -236,6 +236,20 @@ typedef struct Qcow2CryptoHeaderExtensi

Re: [PATCH v2 2/4] qcow2: add configurations for zoned format extension

On 8/28/23 18:22, Sam Li wrote: > Stefan Hajnoczi 于2023年8月21日周一 21:31写道： >> >> On Mon, Aug 14, 2023 at 04:58:00PM +0800, Sam Li wrote: >>> diff --git a/block/qcow2.h b/block/qcow2.h >>> index f789ce3ae0..3694c8d217 100644 >>> --- a/block/qcow2.h >>> +++ b/block/qcow2.h >>> @@ -236,6 +236,20 @@ typ

Re: [PATCH v2 2/4] qcow2: add configurations for zoned format extension

Damien Le Moal 于2023年8月28日周一 18:13写道： > > On 8/28/23 18:22, Sam Li wrote: > > Stefan Hajnoczi 于2023年8月21日周一 21:31写道： > >> > >> On Mon, Aug 14, 2023 at 04:58:00PM +0800, Sam Li wrote: > >>> diff --git a/block/qcow2.h b/block/qcow2.h > >>> index f789ce3ae0..3694c8d217 100644 > >>> --- a/block/qcow2

Re: [PATCH v2 2/4] qcow2: add configurations for zoned format extension

On 8/28/23 19:18, Sam Li wrote: > Damien Le Moal 于2023年8月28日周一 18:13写道： >> >> On 8/28/23 18:22, Sam Li wrote: >>> Stefan Hajnoczi 于2023年8月21日周一 21:31写道： On Mon, Aug 14, 2023 at 04:58:00PM +0800, Sam Li wrote: > diff --git a/block/qcow2.h b/block/qcow2.h > index f789ce3ae0..3694c

[PULL 03/14] python: mkvenv: tweak the matching of --diagnose to depspecs

Move the matching between the "absent" array and dep_specs[0] inside the loop, preparing for the possibility of having multiple canaries among the installed packages. Signed-off-by: Paolo Bonzini --- python/scripts/mkvenv.py | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a

[PULL 13/14] configure: fix container_hosts misspellings and duplications

container_hosts is matched against $cpu, so it must contain QEMU canonical architecture names, not Debian architecture names. Also do not set $container_hosts inside the loop, since it is already set before. Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- configure | 3 +-- 1 fi

[PULL 11/14] tests/docker: add python3-tomli dependency to containers

Instead of having CI pick tomli from the vendored wheel at configure time, place it in the containers. Signed-off-by: Paolo Bonzini --- .gitlab-ci.d/cirrus/freebsd-13.vars | 2 +- .gitlab-ci.d/cirrus/macos-12.vars| 2 +- tests/docker/dockerfiles/centos8.docker

[PULL 04/14] python: mkvenv: introduce TOML-like representation of dependencies

We would like to place all Python dependencies in the same file, so that we can add more information without having long and complex command lines. The plan is to have a TOML file with one entry per package, for example [avocado] avocado-framework = { accepted = "(>=88.1, <93.0)", inst

[PULL 05/14] python: mkvenv: add ensuregroup command

Introduce a new subcommand that retrieves the packages to be installed from a TOML file. This allows being more flexible in using the system version of a package, while at the same time using a known-good version when installing the package. This is important for packages that sometimes have backw

[PULL 14/14] configure: remove unnecessary mkdir -p

It is already included in the symlink shell function. Signed-off-by: Paolo Bonzini --- configure | 1 - 1 file changed, 1 deletion(-) diff --git a/configure b/configure index 08bf24b689c..b9bd008592a 100755 --- a/configure +++ b/configure @@ -1775,7 +1775,6 @@ fi for target in $target_list; do

[PULL 00/14] Python, i386 changes for 2023-08-28

The following changes since commit 50e7a40af372ee5931c99ef7390f5d3d6fbf6ec4: Merge tag 'pull-target-arm-20230824' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2023-08-24 10:08:33 -0400) are available in the Git repository at: https://gitlab.com/bonzini/qemu.git tags/for

[PULL 02/14] dockerfiles: bump tricore cross compiler container to Debian 11

With the release of version 12 on June 10, 2023, Debian 10 is not supported anymore. Modify the cross compiler container to build on a newer version. Signed-off-by: Paolo Bonzini --- tests/docker/dockerfiles/debian-tricore-cross.docker | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff

[PULL 12/14] target/i386: add support for VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE

From: Ake Koomsin Current QEMU can expose waitpkg to guests when it is available. However, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE is still not recognized and masked by QEMU. This can lead to an unexpected situation when a L1 hypervisor wants to expose waitpkg to a L2 guest. The L1 hypervisor c

[PULL 01/14] configure: fix and complete detection of tricore tools

The tricore tools are not detected when they are installed in the host system, only if they are taken from an external container. For this reason the build-tricore-softmmu job was not running the TCG tests. In addition the container provides all tools, not just as/ld/gcc, so there is no need to s

[PULL 06/14] lcitool: bump libvirt-ci submodule and regenerate

This brings in a newer version of the pipewire mapping, so rename it. Python 3.9 and 3.10 do not seem to work in OpenSUSE LEAP 15.5 (weird, because 3.9 persisted from 15.3 to 15.4) so bump the Python runtime version to 3.11. Signed-off-by: Paolo Bonzini --- .../dockerfiles/debian-amd64-cross.do

[PULL 10/14] Revert "tests: Use separate virtual environment for avocado"

This reverts commit e8e4298feadae7924cf7600bb3bcc5b0a8d7cbe9. ensuregroup allows to specify both the acceptable versions of avocado, and a locked version to be used when avocado is not installed as a system pacakge. This lets us install avocado in pyvenv/ using "mkvenv.py" and reuse the distro pa

[PULL 09/14] configure: switch to ensuregroup

Using the new ensuregroup command, the desired versions of meson and sphinx can be placed in pythondeps.toml rather than configure. The meson.install entry in pythondeps.toml matches the version that is found in python/wheels. This ensures that mkvenv.py uses the bundled wheel even if PyPI is ena

[PULL 07/14] configure: never use PyPI for Meson

Since there is a vendored copy, there is no point in choosing online operation. Signed-off-by: Paolo Bonzini --- configure | 6 -- 1 file changed, 6 deletions(-) diff --git a/configure b/configure index f2bd8858d6c..f13f0662b98 100755 --- a/configure +++ b/configure @@ -1018,13 +1018,7 @@ f

[PULL 08/14] python: use vendored tomli

Debian only introduced tomli in the bookworm release. Use a vendored wheel to avoid requiring a package that is only in bullseye-backports and is also absent in Ubuntu 20.04. While at it, fix an issue in the vendor.py scripts which does not add a newline after each package and hash. Signed-off-b

Re: [PATCH v2 2/4] qcow2: add configurations for zoned format extension

Damien Le Moal 于2023年8月28日周一 18:22写道： > > On 8/28/23 19:18, Sam Li wrote: > > Damien Le Moal 于2023年8月28日周一 18:13写道： > >> > >> On 8/28/23 18:22, Sam Li wrote: > >>> Stefan Hajnoczi 于2023年8月21日周一 21:31写道： > > On Mon, Aug 14, 2023 at 04:58:00PM +0800, Sam Li wrote: > > diff --git a/bl

[PATCH v2 04/11] target/tricore: Implement FTOU insn

Signed-off-by: Bastian Koppelmann --- v1 -> v2: - Remove special case for NAN input - Clarified, why we need arg < 0.0 special case target/tricore/fpu_helper.c | 32 +++ target/tricore/helper.h | 1 + target/tricore/translate.c

[PATCH v2 02/11] target/tricore: Implement CRCN insn

reported in https://gitlab.com/qemu-project/qemu/-/issues/1667 Signed-off-by: Bastian Koppelmann --- v1 -> v2: - Removed useless deposits in crc_div() - Replaced final deposit() with extract() in helper_crcn() - Add trap for CRCN insn if not feature_162 target/tricore/helper.h

[PATCH v2 11/11] target/tricore: Fix FTOUZ being ISA v1.3.1 up

Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann --- target/tricore/translate.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index cc2030be14..9770839749 100644 --- a/target/tricore/translate.c ++

[PATCH v2 03/11] target/tricore: Correctly handle FPU RM from PSW

when we reconstructed PSW using psw_read(), we were trying to clear the cached USB bits out of env->PSW. The mask was wrong and we would clear PSW.RM as well. when we write the PSW using psw_write() we update the rounding modes in env->fp_status for softfloat. The order of bits used by TriCore is

[PATCH v2 01/11] tests/tcg/tricore: Bump cpu to tc37x

we don't want to exclude ISA v1.6.2 insns from our tests. Acked-by: Richard Henderson Signed-off-by: Bastian Koppelmann --- tests/tcg/tricore/Makefile.softmmu-target | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/tests/tcg/tricor

[PATCH v2 00/11] TriCore 1.6.2 insn and bugfixes

Hi, this series implements the insns reported in [1], as well as ftou. Also I fixed two bugs in the insert insn which I came across during testing. Cheers, Bastian [1] https://gitlab.com/qemu-project/qemu/-/issues/1667 v1 -> v2: - Removed useless deposits in crc_div() - Replaced final d

[PATCH v2 07/11] target/tricore: Implement hptof insn

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1667 Signed-off-by: Bastian Koppelmann --- v1 -> v2: - Removed special case for f_arg being infinity - Clarified, why we need a special case for arg being NAN target/tricore/fpu_helper.c | 36 +++ t

[PATCH v2 06/11] target/tricore: Implement ftohp insn

reported in https://gitlab.com/qemu-project/qemu/-/issues/1667 Signed-off-by: Bastian Koppelmann --- v1 -> v2: - Removed special case for f_arg being infinity - Clarified, why we need a special case for arg being NAN target/tricore/fpu_helper.c | 38 +++

[PATCH v2 10/11] target/tricore: Replace cpu_*_code with translator_*

Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann --- target/tricore/translate.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 403533c564..cc2030be14 100644 --- a/target/tricore/translate.c

[PATCH v2 09/11] target/tricore: Swap src and dst reg for RCRR_INSERT

Signed-off-by: Bastian Koppelmann --- target/tricore/translate.c | 8 tests/tcg/tricore/asm/macros.h | 9 + tests/tcg/tricore/asm/test_insert.S | 5 + 3 files changed, 18 insertions(+), 4 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/tra

[PATCH v2 08/11] target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0

we would crash if width was 0 for these insns, as tcg_gen_deposit() is undefined for that case. For TriCore, width = 0 is a mov from the src reg to the dst reg, so we special case this here. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann --- target/tricore/translate.c

[PATCH v2 05/11] target/tricore: Clarify special case for FTOUZ insn

this is not something other ISAs do, so clarify it with a comment. Signed-off-by: Bastian Koppelmann --- target/tricore/fpu_helper.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c index 3aefeb776e..d0c474c5f3 100644 --- a/target

Re: [PATCH v2 3/4] qcow2: add zoned emulation capability

Stefan Hajnoczi 于2023年8月23日周三 03:48写道： > > On Mon, Aug 14, 2023 at 04:58:01PM +0800, Sam Li wrote: > > By adding zone operations and zoned metadata, the zoned emulation > > capability enables full emulation support of zoned device using > > a qcow2 file. The zoned device metadata includes zone typ

Re: [PATCH 2/8] hw/acpi/cpu: Have build_cpus_aml() take a build_madt_cpu_fn callback

On 28/8/23 09:36, Bernhard Beschow wrote: build_cpus_aml() is architecture independent but needs to create architecture- specific CPU AML. So far this was achieved by using a virtual method from TYPE_ACPI_DEVICE_IF. However, build_cpus_aml() would resolve this interface from global (!) state. Thi

Re: [PATCH 3/8] hw/acpi/acpi_dev_interface: Remove now unused madt_cpu virtual method

On 28/8/23 09:36, Bernhard Beschow wrote: This virtual method was always set to the x86-specific pc_madt_cpu_entry(), even in piix4 which is also used in MIPS. The previous changes use pc_madt_cpu_entry() otherwise, so madt_cpu can be dropped. Since pc_madt_cpu_entry() is now only used in x86-sp

Re: [PATCH 4/8] hw/acpi/acpi_dev_interface: Remove now unused #include "hw/boards.h"

On 28/8/23 09:36, Bernhard Beschow wrote: The "hw/boards.h" is unused since the previous commit. Since its removal requires include fixes in various unrelated files to keep the code compiling it has been split in a dedicated commit. Signed-off-by: Bernhard Beschow --- hw/acpi/hmat.h

Re: [PATCH 5/8] hw/i386: Remove now redundant TYPE_ACPI_GED_X86

On 28/8/23 09:36, Bernhard Beschow wrote: Now that TYPE_ACPI_GED_X86 doesn't assign AcpiDeviceIfClass::madt_cpu any more it is the same as TYPE_ACPI_GED. Signed-off-by: Bernhard Beschow --- include/hw/acpi/generic_event_device.h | 2 -- hw/i386/generic_event_device_x86.c | 27 --

Re: [PATCH 8/8] hw/acpi/core: Trace enable and status registers of GPE separately

On 28/8/23 09:36, Bernhard Beschow wrote: The bit positions of both registers are related. Tracing the registers independently results in the same offsets across these registers which eases debugging. Signed-off-by: Bernhard Beschow Acked-by: Igor Mammedov --- hw/acpi/core.c | 10 +

Re: [PATCH 6/8] hw/i386/acpi-build: Determine SMI command port just once

On 28/8/23 09:36, Bernhard Beschow wrote: The SMI command port is currently hardcoded by means of the ACPI_PORT_SMI_CMD macro. This hardcoding is Intel specific and doesn't match VIA, for example. There is already the AcpiFadtData::smi_cmd attribute which is used when building the FADT. Let's als

Re: [PATCH 1/8] hw/i386/acpi-build: Use pc_madt_cpu_entry() directly

On 28/8/23 09:36, Bernhard Beschow wrote: This is x86-specific code, so there is no advantage in using pc_madt_cpu_entry() behind an architecture-agnostic interface. Signed-off-by: Bernhard Beschow --- hw/i386/acpi-common.h | 3 +-- hw/i386/acpi-build.c | 3 +-- hw/i386/acpi-common.c |

Re: [PATCH 1/3] hw/mips/jazz: Remove the big_endian variable

Hi Thomas, On 25/8/23 19:51, Thomas Huth wrote: There is an easier way to get a value that can be used to decide whether the target is big endian or not: Simply use the target_words_bigendian() function instead. Signed-off-by: Thomas Huth --- hw/mips/jazz.c | 10 ++ 1 file changed,

Re: [PATCH] chardev/char-pty: Avoid losing bytes when the other side just (re-)connected

On 17/08/2023 19.09, Thomas Huth wrote: On 17/08/2023 15.47, Marc-André Lureau wrote: Hi On Thu, Aug 17, 2023 at 5:06 PM Daniel P. Berrangé wrote: On Thu, Aug 17, 2023 at 02:00:26PM +0200, Thomas Huth wrote: On 17/08/2023 12.32, Daniel P. Berrangé wrote: On Wed, Aug 16, 2023 at 11:07:43PM

Re: [RFC PATCH 1/3] cpu: Add new API cpu_type_by_name

On 25/8/23 14:16, LIU Zhiwei wrote: cpu_type_by_name is used to get the cpu type name from the command line -cpu. Currently it is only used by parse_cpu_option. In the next patch, it will be used by other cpu query functions. Signed-off-by: LIU Zhiwei --- cpu.c | 31 +++--

Re: [RFC PATCH v2 4/6] target/riscv: Add default value for misa property

On 8/28/23 05:45, LIU Zhiwei wrote: Before this patch, " qemu-system-riscv64 -device rv64-riscv-cpu,v=true,help ... v= - Vector operations ... " After this patch, " v= - Vector operations (default: false) " Signed-off-by: LIU Zhiwei --- Reviewed-by: Daniel He

Re: [PATCH v2 08/11] target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0

On 28/8/23 13:26, Bastian Koppelmann wrote: we would crash if width was 0 for these insns, as tcg_gen_deposit() is undefined for that case. For TriCore, width = 0 is a mov from the src reg to the dst reg, so we special case this here. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppel

Re: [RFC PATCH v2 5/6] target/riscv: Add defalut value for string property

On 8/28/23 05:45, LIU Zhiwei wrote: Before this patch, """ qemu-system-riscv64 -device rv64-riscv-cpu,v=true,help ... vext_spec= ... """ After this patch, """ vext_spec=- (default: "v1.0") """ Signed-off-by: LIU Zhiwei --- Code LGTM. Assuming that we'll need a new API to set d

Re: [RFC PATCH v2 6/6] linux-user: Move qemu_cpu_opts to cpu.c

On 8/28/23 05:45, LIU Zhiwei wrote: Make qemu_cpu_opts also works for linux user mode. Notice, currently qdev monitor is not included in linux user mode. We just output current enabled extentions for RISC-V(without the hint to print all properties with -device). With this patch, """ qemu-risc

Re: [PATCH 1/3] hw/mips/jazz: Remove the big_endian variable

On 28/08/2023 14.19, Philippe Mathieu-Daudé wrote: Hi Thomas, On 25/8/23 19:51, Thomas Huth wrote: There is an easier way to get a value that can be used to decide whether the target is big endian or not: Simply use the target_words_bigendian() function instead. Signed-off-by: Thomas Huth ---

Help with QEMU DBUS display

Hi! I'm currently attempting to use qemu's DBUS display from within a go application, using the godbus library. However, I'm hitting some roadblocks, and this is probably because I'm a bit confused about how qemu's peer-to-peer dbus connection wo

Re: [PATCH v2 47/58] i386/tdx: Wire REPORT_FATAL_ERROR with GuestPanic facility

On 8/21/2023 5:58 PM, Daniel P. Berrangé wrote: On Fri, Aug 18, 2023 at 05:50:30AM -0400, Xiaoyao Li wrote: Originated-from: Isaku Yamahata Signed-off-by: Xiaoyao Li --- qapi/run-state.json | 17 +-- softmmu/runstate.c| 49 +++ targ

Re: [PATCH] tests/avocado/machine_aspeed.py: Update SDK images

On Mon, 28 Aug 2023 at 09:01, Cédric Le Goater wrote: > > Switch to the latest v8.06 release which introduces interesting > changes for the AST2600 I2C and I3C models. Also take the AST2600 A2 > images instead of the default since QEMU tries to model The AST2600 A3 > SoC. Is there any value in te

Re: [RFC PATCH v2 0/6] Add API for list cpu extensions

On Mon, 28 Aug 2023 16:45:30 +0800 LIU Zhiwei wrote: > Some times we want to know what is the really mean of one cpu option. > For example, in RISC-V, we usually specify a cpu in this way: > -cpu rv64,v=on > > If we don't look into the source code, we can't get the ISA extensions > of this -cpu

Re: [PATCH v3] migration: hold the BQL during setup

Ping Am 14.07.23 um 10:20 schrieb Fiona Ebner: > Ping > > Am 30.06.23 um 16:18 schrieb Fiona Ebner: >> This is intended to be a semantic revert of commit 9b09503752 >> ("migration: run setup callbacks out of big lock"). There have been so >> many changes since that commit (e.g. a new setup callba

Re: [PATCH] tests/avocado/machine_aspeed.py: Update SDK images

On 8/28/23 15:54, Joel Stanley wrote: On Mon, 28 Aug 2023 at 09:01, Cédric Le Goater wrote: Switch to the latest v8.06 release which introduces interesting changes for the AST2600 I2C and I3C models. Also take the AST2600 A2 images instead of the default since QEMU tries to model The AST2600 A

[PULL 0/3] Dirty page rate and dirty page limit 20230828 patches

From: Hyman The following changes since commit 50e7a40af372ee5931c99ef7390f5d3d6fbf6ec4: Merge tag 'pull-target-arm-20230824' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2023-08-24 10:08:33 -0400) are available in the git repository at: https://github.com/newfriday/q

Re: [PATCH v2 2/4] qcow2: add configurations for zoned format extension

Stefan Hajnoczi 于2023年8月21日周一 21:31写道： > > On Mon, Aug 14, 2023 at 04:58:00PM +0800, Sam Li wrote: > > diff --git a/block/qcow2.h b/block/qcow2.h > > index f789ce3ae0..3694c8d217 100644 > > --- a/block/qcow2.h > > +++ b/block/qcow2.h > > @@ -236,6 +236,20 @@ typedef struct Qcow2CryptoHeaderExtensi

Re: [PATCH v2 3/8] machine: Print supported CPU models instead of typenames

On Mon, 31 Jul 2023 15:07:30 +1000 Gavin Shan wrote: > On 7/27/23 19:00, Igor Mammedov wrote: > > On Thu, 27 Jul 2023 15:16:18 +1000 > > Gavin Shan wrote: > > > >> On 7/27/23 09:08, Richard Henderson wrote: > >>> On 7/25/23 17:32, Gavin Shan wrote: > -static const char *q800_machine_

[PATCH 5/8] target/translate: Restrict 'exec/cpu_ldst.h' to user emulation

Only handle_sigsegv_accerr_write(), declared with user emulation, requires "exec/cpu_ldst.h" (for the abi_ptr typedef). Signed-off-by: Philippe Mathieu-Daudé --- include/exec/exec-all.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/exec/exec-all.h b/include/exec/exe

[PATCH 7/8] target/helper: Remove unnecessary 'qemu/main-loop.h' header

"qemu/main-loop.h" declares functions related to QEMU's main loop mutex, which these files don't access. Remove the unused "qemu/main-loop.h" header. Signed-off-by: Philippe Mathieu-Daudé --- target/riscv/pmu.h | 2 -- target/arm/ptw.c | 1 - target/loongarc

[PATCH 3/8] target/translate: Include missing 'exec/cpu_ldst.h' header

All these files access the CPU LD/ST API declared in "exec/cpu_ldst.h". Signed-off-by: Philippe Mathieu-Daudé --- target/avr/helper.c | 1 + target/i386/tcg/fpu_helper.c | 1 + target/i386/tcg/sysemu/excp_helper.c | 1 + target/loongarch/cpu.c | 1 + target

[PATCH 1/8] target/ppc/pmu: Include missing 'qemu/timer.h' header

Since commit c2eff582a3 ("target/ppc: PMU basic cycle count for pseries TCG") pmu_update_cycles() uses QEMU_CLOCK_VIRTUAL and calls qemu_clock_get_ns(), both defined in "qemu/timer.h". Signed-off-by: Philippe Mathieu-Daudé --- target/ppc/power8-pmu.c | 1 + 1 file changed, 1 insertion(+) diff -

[PATCH 8/8] target/mips: Remove unused headers in lcsr_helper.c

This files only access the address_space_ld/st API, declared in "exec/cpu-all.h", already included by "cpu.h". Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/sysemu/lcsr_helper.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/target/mips/tcg/sysemu/lcsr_helper.c b/target/mips/

[PATCH 0/8] target/translate: Remove unused "exec/cpu_ldst.h" / "qemu/main-loop.h"

Yet another boring 'header cleanups' series :/ Philippe Mathieu-Daudé (8): target/ppc/pmu: Include missing 'qemu/timer.h' header target/riscv/pmu: Restrict 'qemu/log.h' include to source target/translate: Include missing 'exec/cpu_ldst.h' header target/translate: Remove unnecessary 'exec/c

[PATCH 2/8] target/riscv/pmu: Restrict 'qemu/log.h' include to source

Declarations from "riscv/pmu.h" don't need anything from "qemu/log.h", reduce it's inclusion to the source. Signed-off-by: Philippe Mathieu-Daudé --- target/riscv/pmu.h | 1 - target/riscv/pmu.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/pmu.h b/target/riscv

[PATCH 4/8] target/translate: Remove unnecessary 'exec/cpu_ldst.h' header

All these files only access the translator_ld/st API declared in "exec/translator.h". The CPU ld/st API from declared in "exec/cpu_ldst.h" is not used, remove it. Signed-off-by: Philippe Mathieu-Daudé --- target/alpha/translate.c | 1 - target/hexagon/translate.c| 1 - target/hppa/trans

[PATCH] linux-user/riscv: Add new extensions to hwprobe

This patch adds the new extensions in linux 6.5 to the hwprobe syscall. And fixes RVC check to OR with correct value. The previous variable contains 0 therefore it did work. Signed-off-by: Robbin Ehn --- linux-user/syscall.c | 14 +- 1 file changed, 13 insertions(+), 1 deletion(-)

[PATCH 6/8] target/helpers: Remove unnecessary 'exec/cpu_ldst.h' header

These files don't use the CPU ld/st API, remove the unnecessary "exec/cpu_ldst.h" header. Signed-off-by: Philippe Mathieu-Daudé --- target/cris/op_helper.c | 1 - target/mips/tcg/fpu_helper.c | 1 - target/mips/tcg/sysemu/lcsr_helper.c | 1 - target/s390x/tcg/excp_helper.c

[PATCH] kconfig: Add NVME to s390x machines

From: Cédric Le Goater We recently had issues with nvme devices on big endian platforms. Include their compilation on s390x to ease tests. Signed-off-by: Cédric Le Goater --- hw/nvme/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/nvme/Kconfig b/hw/nvme/Kconfig i

[PATCH v3 1/4] docs/qcow2: add the zoned format feature

Add the specs for the zoned format feature of the qcow2 driver. The qcow2 file can be taken as zoned device and passed through by virtio-blk device or NVMe ZNS device to the guest given zoned information. Signed-off-by: Sam Li --- docs/system/qemu-block-drivers.rst.inc | 39 +

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