Re: [PATCH v4 05/15] target/loongarch: Truncate high 32 bits of address in VA32 mode

On 22/8/23 05:27, Song Gao wrote: From: Jiajie Chen When running in VA32 mode(!LA64 or VA32L[1-3] matching PLV), virtual address is truncated to 32 bits before address mapping. Signed-off-by: Jiajie Chen Co-authored-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Song Ga

Re: [PATCH v4 06/15] target/loongarch: Sign extend results in VA32 mode

On 22/8/23 05:27, Song Gao wrote: From: Jiajie Chen In VA32 mode, BL, JIRL and PC* instructions should sign-extend the low 32 bit result to 64 bits. Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao --- target/loongarch/translate.c | 8 +++

[PATCH v5 00/19] Based-on: https://patchew.org/QEMU/20230821125959.28666-1-phi...@linaro.org/

(all series reviewed, for Song Gao to pick whichever v4/v5 is preferred) Hi, This series adds some checks before translating instructions This includes: CPUCFG[1].IOCSR CPUCFG[2].FP CPUCFG[2].FP_SP CPUCFG[2].FP_DP CPUCFG[2].LSPW CPUCFG[2].LAM CPUCFG[2].LSX V5: - Split 2 patches, extracting he

[PATCH v5 03/19] target/loongarch: Support LoongArch32 VPPN

From: Jiajie Chen VPPN of TLBEHI/TLBREHI is limited to 19 bits in LA32. Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-ID: <20230822032724.1353391-4-gaos...@loongson.cn> --- target/loongarch/cpu-csr.h| 6 -- target/loongarch/tlb_helper.c |

[PATCH v5 01/19] target/loongarch: Support LoongArch32 TLB entry

From: Jiajie Chen The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to zero in LoongArch32. Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-ID: <20230822032724.1353391-2-gaos...@loongson.cn> --- target/loongarch/cpu-csr.h| 9 +++

[PATCH v5 05/19] target/loongarch: Extract make_address_x() helper

From: Jiajie Chen Signed-off-by: Jiajie Chen Co-authored-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230822032724.1353391-6-gaos...@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe

[PATCH v5 07/19] target/loongarch: Extract make_address_pc() helper

From: Jiajie Chen Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230822032724.1353391-7-gaos...@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe Mathieu-Daudé --- target/loongar

[PATCH v5 04/19] target/loongarch: Add LA64 & VA32 to DisasContext

From: Jiajie Chen Add LA64 and VA32(32-bit Virtual Address) to DisasContext to allow the translator to reject doubleword instructions in LA32 mode for example. Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-ID: <20230822032724.1353391-5-gaos...@loong

[PATCH v5 02/19] target/loongarch: Support LoongArch32 DMW

From: Jiajie Chen LA32 uses a different encoding for CSR.DMW and a new direct mapping mechanism. Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-ID: <20230822032724.1353391-3-gaos...@loongson.cn> --- target/loongarch/cpu-csr.h| 7 +++ target

[PATCH v5 09/19] target/loongarch: Truncate high 32 bits of address in VA32 mode

From: Jiajie Chen When running in VA32 mode(!LA64 or VA32L[1-3] matching PLV), virtual address is truncated to 32 bits before address mapping. Signed-off-by: Jiajie Chen Co-authored-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Dau

[PATCH v5 08/19] target/loongarch: Extract set_pc() helper

From: Jiajie Chen Signed-off-by: Jiajie Chen Co-authored-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230822032724.1353391-6-gaos...@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe

[PATCH v5 06/19] target/loongarch: Extract make_address_i() helper

From: Jiajie Chen Signed-off-by: Jiajie Chen Co-authored-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230822032724.1353391-6-gaos...@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe

[PATCH RESEND v5 00/19] Add some checks before translating instructions

Based-on: https://patchew.org/QEMU/20230821125959.28666-1-phi...@linaro.org/ (all series reviewed, for Song Gao to pick whichever v4/v5 is preferred) Hi, This series adds some checks before translating instructions This includes: CPUCFG[1].IOCSR CPUCFG[2].FP CPUCFG[2].FP_SP CPUCFG[2].FP_DP CP

[PATCH RESEND v5 02/19] target/loongarch: Support LoongArch32 DMW

From: Jiajie Chen LA32 uses a different encoding for CSR.DMW and a new direct mapping mechanism. Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-ID: <20230822032724.1353391-3-gaos...@loongson.cn> --- target/loongarch/cpu-csr.h| 7 +++ target

[PATCH RESEND v5 04/19] target/loongarch: Add LA64 & VA32 to DisasContext

From: Jiajie Chen Add LA64 and VA32(32-bit Virtual Address) to DisasContext to allow the translator to reject doubleword instructions in LA32 mode for example. Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-ID: <20230822032724.1353391-5-gaos...@loong

[PATCH RESEND v5 01/19] target/loongarch: Support LoongArch32 TLB entry

From: Jiajie Chen The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to zero in LoongArch32. Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-ID: <20230822032724.1353391-2-gaos...@loongson.cn> --- target/loongarch/cpu-csr.h| 9 +++

[PATCH RESEND v5 05/19] target/loongarch: Extract make_address_x() helper

From: Jiajie Chen Signed-off-by: Jiajie Chen Co-authored-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230822032724.1353391-6-gaos...@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe

[PATCH RESEND v5 06/19] target/loongarch: Extract make_address_i() helper

From: Jiajie Chen Signed-off-by: Jiajie Chen Co-authored-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230822032724.1353391-6-gaos...@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe

[PATCH RESEND v5 03/19] target/loongarch: Support LoongArch32 VPPN

From: Jiajie Chen VPPN of TLBEHI/TLBREHI is limited to 19 bits in LA32. Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-ID: <20230822032724.1353391-4-gaos...@loongson.cn> --- target/loongarch/cpu-csr.h| 6 -- target/loongarch/tlb_helper.c |

[PATCH RESEND v5 08/19] target/loongarch: Extract set_pc() helper

From: Jiajie Chen Signed-off-by: Jiajie Chen Co-authored-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230822032724.1353391-6-gaos...@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe

[PATCH RESEND v5 09/19] target/loongarch: Truncate high 32 bits of address in VA32 mode

From: Jiajie Chen When running in VA32 mode(!LA64 or VA32L[1-3] matching PLV), virtual address is truncated to 32 bits before address mapping. Signed-off-by: Jiajie Chen Co-authored-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Dau

[PATCH RESEND v5 07/19] target/loongarch: Extract make_address_pc() helper

From: Jiajie Chen Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230822032724.1353391-7-gaos...@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe Mathieu-Daudé --- target/loongar

Re: [PATCH v5 00/19] Based-on: https://patchew.org/QEMU/20230821125959.28666-1-phi...@linaro.org/

On 22/8/23 09:09, Philippe Mathieu-Daudé wrote: (all series reviewed, for Song Gao to pick whichever v4/v5 is preferred) Incorrect subject, and SMTP failure, so disregard (will resend).

[PATCH RESEND v5 10/19] target/loongarch: Sign extend results in VA32 mode

From: Jiajie Chen In VA32 mode, BL, JIRL and PC* instructions should sign-extend the low 32 bit result to 64 bits. Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230822032724.1353391-7-gaos...@loongson.cn>

[PATCH RESEND v5 13/19] target/loongarch: Add LoongArch32 cpu la132

From: Jiajie Chen Add LoongArch32 cpu la132. Due to lack of public documentation of la132, it is currently a synthetic LoongArch32 cpu model. Details need to be added in the future. Signed-off-by: Jiajie Chen Signed-off-by: Song Gao Acked-by: Richard Henderson Reviewed-by: Philippe Mathieu-D

[PATCH RESEND v5 15/19] target/loongarch: Add avail_FP/FP_SP/FP_DP to check fpu instructions

From: Song Gao Signed-off-by: Song Gao Acked-by: Richard Henderson Message-ID: <20230822032724.1353391-12-gaos...@loongson.cn> --- target/loongarch/translate.h | 4 + target/loongarch/translate.c | 1 + .../loongarch/insn_trans/trans_farith.c.inc | 96

[PATCH RESEND v5 11/19] target/loongarch: Add a check parameter to the TRANS macro

From: Song Gao The default check parmeter is ALL. Suggested-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-ID: <20230822032724.1353391-8-gaos...@loongson.cn> --- target/loongarch/translate.h |6 +-

[PATCH RESEND v5 14/19] hw/loongarch: Remove restriction of la464 cores in the virt machine

From: Song Gao Allow virt machine to be used with la132 instead of la464. Co-authored-by: Jiajie Chen Signed-off-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230822032724.1353391-11-gaos...@loongson.cn> --- hw/loongarch/virt.c | 5 - 1 f

[PATCH RESEND v5 16/19] target/loongarch: Add avail_LSPW to check LSPW instructions

From: Song Gao Signed-off-by: Song Gao Reviewed-by: Richard Henderson Message-ID: <20230822032724.1353391-13-gaos...@loongson.cn> --- target/loongarch/translate.h | 1 + target/loongarch/insn_trans/trans_privileged.c.inc | 8 2 files changed, 9 insertions(+) dif

[PATCH RESEND v5 12/19] target/loongarch: Add avail_64 to check la64-only instructions

From: Song Gao The la32 instructions listed in Table 2 at https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#overview-of-basic-integer-instructions Co-authored-by: Jiajie Chen Signed-off-by: Song Gao Reviewed-by: Richard Henderson Message-ID: <20230822032724.1353391-9-g

[PATCH RESEND v5 17/19] target/loongarch: Add avail_LAM to check atomic instructions

From: Song Gao Signed-off-by: Song Gao Reviewed-by: Richard Henderson Message-ID: <20230822032724.1353391-14-gaos...@loongson.cn> --- target/loongarch/translate.h | 1 + .../loongarch/insn_trans/trans_atomic.c.inc | 72 +-- 2 files changed, 37 insertions(+),

[PATCH RESEND v5 19/19] target/loongarch: Add avail_IOCSR to check iocsr instructions

From: Song Gao Signed-off-by: Song Gao Reviewed-by: Richard Henderson Message-ID: <20230822032724.1353391-16-gaos...@loongson.cn> --- target/loongarch/translate.h | 2 +- .../loongarch/insn_trans/trans_privileged.c.inc | 16 2 files changed, 9 insertions(

Re: [PATCH] target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0

On Thu, Aug 17, 2023 at 12:29:03PM -0300, Daniel Henrique Barboza wrote: > In the same emulated RISC-V host, the 'host' KVM CPU takes 4 times > longer to boot than the 'rv64' KVM CPU. > > The reason is an unintended behavior of riscv_cpu_satp_mode_finalize() > when satp_mode.supported = 0, i.e. wh

[PATCH v1 1/4] vfio/pci: detect the support of dynamic MSI-X allocation

Kernel provides the guidance of dynamic MSI-X allocation support of passthrough device, by clearing the VFIO_IRQ_INFO_NORESIZE flag to guide user space. Fetch the flags from host to determine if dynamic MSI-X allocation is supported. Originally-by: Reinette Chatre Signed-off-by: Jing Liu --- Ch

[PATCH v1 2/4] vfio/pci: enable vector on dynamic MSI-X allocation

The vector_use callback is used to enable vector that is unmasked in guest. The kernel used to only support static MSI-X allocation. When allocating a new interrupt using "static MSI-X allocation" kernels, Qemu first disables all previously allocated vectors and then re-allocates all including the

[PATCH v1 4/4] vfio/pci: enable MSI-X in interrupt restoring on dynamic allocation

During migration restoring, vfio_enable_vectors() is called to restore enabling MSI-X interrupts for assigned devices. It sets the range from 0 to nr_vectors to kernel to enable MSI-X and the vectors unmasked in guest. During the MSI-X enabling, all the vectors within the range are allocated accord

[PATCH RESEND v5 18/19] target/loongarch: Add avail_LSX to check LSX instructions

From: Song Gao Signed-off-by: Song Gao Reviewed-by: Richard Henderson Message-ID: <20230822032724.1353391-15-gaos...@loongson.cn> --- target/loongarch/translate.h|2 + target/loongarch/insn_trans/trans_lsx.c.inc | 1396 +++ 2 files changed, 780 insertions(+)

[PATCH v1 0/4] Support dynamic MSI-X allocation

Changes since RFC v1: - RFC v1: https://www.mail-archive.com/qemu-devel@nongnu.org/msg978637.html - Revise the comments. (Alex) - Report error of getting irq info and remove the trace of failure case. (Alex, Cédric) - Only store dynamic allocation flag as a bool type and test accordingly. (Alex

[PATCH v1 3/4] vfio/pci: use an invalid fd to enable MSI-X

Guests typically enable MSI-X with all of the vectors masked in the MSI-X vector table. To match the guest state of device, Qemu enables MSI-X by enabling vector 0 with userspace triggering and immediately release. However the release function actually does not release it due to already using users

Re: [PATCH v2 06/58] i386/tdx: Get tdx_capabilities via KVM_TDX_CAPABILITIES

On 8/21/2023 4:46 PM, Daniel P. Berrangé wrote: On Fri, Aug 18, 2023 at 05:49:49AM -0400, Xiaoyao Li wrote: KVM provides TDX capabilities via sub command KVM_TDX_CAPABILITIES of IOCTL(KVM_MEMORY_ENCRYPT_OP). Get the capabilities when initializing TDX context. It will be used to validate user's s

Re: [PATCH v10 6/9] gfxstream + rutabaga: add initial support for gfxstream

Hi, On 22/8/23 02:00, Gurchetan Singh wrote: This adds initial support for gfxstream and cross-domain. Both features rely on virtio-gpu blob resources and context types, which are also implemented in this patch. [...] hw/display/virtio-gpu-pci-rutabaga.c | 48 ++ hw/display/virtio-gpu-r

Re: [PATCH v10 9/9] docs/system: add basic virtio-gpu documentation

On 22/8/23 02:00, Gurchetan Singh wrote: This adds basic documentation for virtio-gpu. Suggested-by: Akihiko Odaki Signed-off-by: Gurchetan Singh Tested-by: Alyssa Ross Tested-by: Emmanouil Pitsidianakis Reviewed-by: Emmanouil Pitsidianakis --- docs/system/device-emulation.rst | 1

Re: [PATCH v2 07/58] i386/tdx: Introduce is_tdx_vm() helper and cache tdx_guest object

On 8/21/2023 4:48 PM, Daniel P. Berrangé wrote: On Fri, Aug 18, 2023 at 05:49:50AM -0400, Xiaoyao Li wrote: It will need special handling for TDX VMs all around the QEMU. Introduce is_tdx_vm() helper to query if it's a TDX VM. Cache tdx_guest object thus no need to cast from ms->cgs every time.

[PATCH] docs/about/license: Update LICENSE URL

In early 2021 (see commit 2ad784339e "docs: update README to use GitLab repo URLs") almost all of the code base was converted to point to GitLab instead of git.qemu.org. During 2023, git.qemu.org switched from a git mirror to a http redirect to GitLab (see [*]). Update the LICENSE URL to match its

Re: [PATCH v3 0/2] Fix overflow of the max number of IDs for logic processor and core

On 8/18/2023 3:33 AM, Isaku Yamahata wrote: > On Wed, Aug 16, 2023 at 04:06:56PM +0800, > Qian Wen wrote: > >> CPUID.1.EBX[23:16]: Maximum number of addressable IDs for logical >> processors in this physical package. >> CPUID.4:EAX[31:26]: Maximum number of addressable IDs for processor cores >> i

Re: [PATCH v2 4/5] vdpa: move vhost_vdpa_set_vrings_ready to the caller

On Mon, Aug 14, 2023 at 8:57 AM Jason Wang wrote: > > On Thu, Aug 10, 2023 at 11:36 PM Eugenio Pérez wrote: > > > > Doing that way allows CVQ to be enabled before the dataplane vqs, > > restoring the state as MQ or MAC addresses properly in the case of a > > migration. > > > > A typo in the subje

Re: [PATCH v2 06/58] i386/tdx: Get tdx_capabilities via KVM_TDX_CAPABILITIES

On Tue, Aug 22, 2023 at 03:31:44PM +0800, Xiaoyao Li wrote: > On 8/21/2023 4:46 PM, Daniel P. Berrangé wrote: > > On Fri, Aug 18, 2023 at 05:49:49AM -0400, Xiaoyao Li wrote: > > > KVM provides TDX capabilities via sub command KVM_TDX_CAPABILITIES of > > > IOCTL(KVM_MEMORY_ENCRYPT_OP). Get the capab

Re: [PATCH RESEND v5 00/19] Add some checks before translating instructions

在 2023/8/22 下午3:13, Philippe Mathieu-Daudé 写道: Based-on: https://patchew.org/QEMU/20230821125959.28666-1-phi...@linaro.org/ (all series reviewed, for Song Gao to pick whichever v4/v5 is preferred) Hi, This series adds some checks before translating instructions This includes: CPUCFG[1].IOCSR

Re: [PATCH v2 41/58] i386/tdx: handle TDG.VP.VMCALL

On Tue, Aug 22, 2023 at 08:52:30AM +0200, Markus Armbruster wrote: > Xiaoyao Li writes: > > > From: Isaku Yamahata > > > > For GetQuote, delegate a request to Quote Generation Service. Add property > > of address of quote generation server and On request, connect to the > > server, read request

Re: [PATCH] docs/about/license: Update LICENSE URL

On Tue, Aug 22, 2023 at 09:56:12AM +0200, Philippe Mathieu-Daudé wrote: > In early 2021 (see commit 2ad784339e "docs: update README to use > GitLab repo URLs") almost all of the code base was converted to > point to GitLab instead of git.qemu.org. During 2023, git.qemu.org > switched from a git mir

Re: [PATCH v2 4/5] vdpa: move vhost_vdpa_set_vrings_ready to the caller

On Tue, Aug 22, 2023 at 4:09 PM Eugenio Perez Martin wrote: > > On Mon, Aug 14, 2023 at 8:57 AM Jason Wang wrote: > > > > On Thu, Aug 10, 2023 at 11:36 PM Eugenio Pérez wrote: > > > > > > Doing that way allows CVQ to be enabled before the dataplane vqs, > > > restoring the state as MQ or MAC add

Re: [PATCH v2 15/58] i386/tdx: Add property sept-ve-disable for tdx-guest object

On 8/22/2023 2:27 PM, Markus Armbruster wrote: Daniel P. Berrangé writes: On Fri, Aug 18, 2023 at 05:49:58AM -0400, Xiaoyao Li wrote: Bit 28 of TD attribute, named SEPT_VE_DISABLE. When set to 1, it disables EPT violation conversion to #VE on guest TD access of PENDING pages. Some guest OS (

[PATCH v3 4/5] vdpa: move vhost_vdpa_set_vring_ready to the caller

Doing that way allows CVQ to be enabled before the dataplane vqs, restoring the state as MQ or MAC addresses properly in the case of a migration. The patch does it by defining a ->load NetClientInfo callback also for dataplane. Ideally, this should be done by an independent patch, but the functio

[PATCH v3 3/5] vdpa: rename vhost_vdpa_net_load to vhost_vdpa_net_cvq_load

Next patches will add the corresponding data load. Signed-off-by: Eugenio Pérez Acked-by: Jason Wang --- net/vhost-vdpa.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c index a772540250..9251351b4b 100644 --- a/net/vhost-vdpa.c +++ b/

[PATCH v3 0/5] Enable vdpa net migration with features depending on CVQ

At this moment the migration of net features that depends on CVQ is not possible, as there is no reliable way to restore the device state like mac address, number of enabled queues, etc to the destination. This is mainly caused because the device must only read CVQ, and process all the commands be

Re: [PATCH v6 01/12] Add virtio-sound device stub

Volker Rümelin writes: > Am 21.08.23 um 08:06 schrieb Manos Pitsidianakis: > > Hello Volker! > > On Sun, 20 Aug 2023 12:33, Volker Rümelin wrote: > > I think the virtio-snd.c code, the trace events and the Kconfig VIRTIO_SND > should be moved to hw/audio. The > code for nearly all audio

[PATCH v3 5/5] vdpa: remove net cvq migration blocker

Now that we have add migration blockers if the device does not support all the needed features, remove the general blocker applied to all net devices with CVQ. Signed-off-by: Eugenio Pérez Acked-by: Jason Wang --- net/vhost-vdpa.c | 12 1 file changed, 12 deletions(-) diff --git a

[PATCH v3 2/5] vdpa: export vhost_vdpa_set_vring_ready

The vhost-vdpa net backend needs to enable vrings in a different order than default, so export it. No functional change intended except for tracing, that now includes the (virtio) index being enabled and the return value of the ioctl. Still ignoring return value of this function if called from vh

[PATCH v3 1/5] vdpa: use first queue SVQ state for CVQ default

Previous to this patch the only way CVQ would be shadowed is if it does support to isolate CVQ group or if all vqs were shadowed from the beginning. The second condition was checked at the beginning, and no more configuration was done. After this series we need to check if data queues are shadowe

Re: [PATCH v3 4/5] vdpa: move vhost_vdpa_set_vring_ready to the caller

On Tue, Aug 22, 2023 at 4:53 PM Eugenio Pérez wrote: > > Doing that way allows CVQ to be enabled before the dataplane vqs, > restoring the state as MQ or MAC addresses properly in the case of a > migration. > > The patch does it by defining a ->load NetClientInfo callback also for > dataplane. Id

Re: trace_exec_tb(tb, pc) does not have cpu index

Igor Lesik writes: > Hi. > > I am wondering why trace events like trace_exec_tb(tb, pc) do not have > cpu index, how to make sense of the trace in case of multiple vCPUs? > I have changed it to trace_exec_tb(tb, pc, cpu->cpu_index) to read my > trace, and now wondering should not it be there by

[PATCH 0/7] tcg: Document *swap/deposit helpers

While reviewing a recent patch from Richard optimizing deposit() [*] I ended looking at the *swap friends, taking some notes, which then evolved to proper documentation. [*] https://lore.kernel.org/qemu-devel/20230816145547.477974-3-richard.hender...@linaro.org/ Philippe Mathieu-Daudé (7): tcg

[PATCH 2/7] tcg/tcg-op: Document bswap32() byte pattern

Signed-off-by: Philippe Mathieu-Daudé --- tcg/tcg-op.c | 12 1 file changed, 12 insertions(+) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index f164ddc95e..e6b0d74a46 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1061,6 +1061,11 @@ void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg

[PATCH 4/7] tcg/tcg-op: Document hswap() byte pattern

Document hswap_i32() and hswap_i64(), added in commit 46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}"). Signed-off-by: Philippe Mathieu-Daudé --- docs/devel/tcg-ops.rst | 4 tcg/tcg-op.c | 26 +++--- 2 files changed, 23 insertions(+), 7 deletions(-)

[PATCH 6/7] tcg/tcg-op: Document deposit_z()

Document deposit_z_i32() and deposit_z_i64(), added in commit 07cc68d528 ("tcg: Add deposit_z expander"). Signed-off-by: Philippe Mathieu-Daudé --- docs/devel/tcg-ops.rst | 4 1 file changed, 4 insertions(+) diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst index 306025ece7..7ea

[PATCH 3/7] tcg/tcg-op: Document bswap64() byte pattern

Signed-off-by: Philippe Mathieu-Daudé --- tcg/tcg-op.c | 5 + 1 file changed, 5 insertions(+) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index e6b0d74a46..f4fe13e040 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1828,6 +1828,11 @@ void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, int fl

[PATCH 5/7] tcg/tcg-op: Document wswap() byte pattern

Document wswap_i64(), added in commit 46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}"). Signed-off-by: Philippe Mathieu-Daudé --- docs/devel/tcg-ops.rst | 4 tcg/tcg-op.c | 5 + 2 files changed, 9 insertions(+) diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops

[PATCH 1/7] tcg/tcg-op: Document bswap16() byte pattern

Signed-off-by: Philippe Mathieu-Daudé --- tcg/tcg-op.c | 48 1 file changed, 32 insertions(+), 16 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 7aadb37756..f164ddc95e 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1021,6 +1021,13 @

[PATCH 7/7] target/cris: Fix a typo in gen_swapr()

Signed-off-by: Philippe Mathieu-Daudé --- target/cris/translate.c | 20 +++- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/target/cris/translate.c b/target/cris/translate.c index 0b3d724281..42103b5558 100644 --- a/target/cris/translate.c +++ b/target/cris/transla

Re: [PATCH v4 0/9] Implement Most ARMv8.3 Pointer Authentication Features

On Tue, 22 Aug 2023 at 05:25, Richard Henderson wrote: > > This is an update of Aaron's v3 [1]. > There are a fair number of changes beyond a mere rebase: > > * Updates to the test cases which fail with the new features. > * Updates to the documentation. > * Preserve pauth feature set when c

Re: trace_exec_tb(tb, pc) does not have cpu index

On Tue, 22 Aug 2023 at 10:01, Alex Bennée wrote: > > > Igor Lesik writes: > > > Hi. > > > > I am wondering why trace events like trace_exec_tb(tb, pc) do not have > > cpu index, how to make sense of the trace in case of multiple vCPUs? > > I have changed it to trace_exec_tb(tb, pc, cpu->cpu_index

[PATCH] target/arm: Use deposit_z() in BCF opcode

When clearing a bitfield we don't need to lead the source register. Use deposit_z_i32() with the BFC opcode to save a load_reg() call. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/tcg/translate.c | 9 - 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/target/arm/tcg/

Re: [PATCH 1/2] vhost-user: fix lost reconnect

> On Aug 22, 2023, at 12:49 AM, Li Feng wrote: > > > >> On 22 Aug 2023, at 8:38 AM, Raphael Norwitz >> wrote: >> >>> >>> On Aug 17, 2023, at 2:40 AM, Li Feng wrote: >>> >>> 2023年8月14日 下午8:11，Raphael Norwitz 写道： Why can’t we rather fix this by adding a “event_cb” param

[PATCH 0/6] target: Use TCG generic gen_hswap_i32/i64()

Some targets open-code gen_hswap(); replace by the generic helper. Philippe Mathieu-Daudé (6): target/arm: Use hswap_i32() in VREV/SMLAD opcodes target/cris: Use hswap_i32() in SWAPW opcode target/microblaze: Use hswap_i32() in SWAPH opcode target/sh4: Use hswap_i32() in SWAP.W opcode ta

[PATCH 2/6] target/cris: Use hswap_i32() in SWAPW opcode

Commit 46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}") introduced the generic hswap_i32(). Use it instead of open-coding it as t_gen_swapw(). Signed-off-by: Philippe Mathieu-Daudé --- target/cris/translate.c | 14 +- target/cris/translate_v10.c.inc | 2 +- 2 files

[PATCH 1/6] target/arm: Use hswap_i32() in VREV/SMLAD opcodes

Commit 46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}") introduced the generic hswap_i32(). Use it instead of open-coding it as gen_swap_half(). Signed-off-by: Philippe Mathieu-Daudé --- target/arm/tcg/translate-a32.h | 6 -- target/arm/tcg/translate-neon.c | 4 ++-- target/arm/tcg

[PATCH 5/6] target/mips: Use hswap_i64() in DSHD opcode

Commit 46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}") introduced the generic hswap_i32(). Use it instead of open-coding it in gen_bshfl(). Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.c | 14 +- 1 file changed, 1 insertion(+), 13 deletions(-) diff -

[PATCH 6/6] target/loongarch: Use hswap_i64() in REVH.D opcode

Commit 46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}") introduced the generic hswap_i32(). Use it instead of open-coding it as gen_revh_d(). Signed-off-by: Philippe Mathieu-Daudé --- target/loongarch/insn_trans/trans_bit.c.inc | 16 +--- 1 file changed, 1 insertion(+), 15 d

[PATCH 3/6] target/microblaze: Use hswap_i32() in SWAPH opcode

Commit 46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}") introduced the generic hswap_i32(). Use it instead of open-coding it as gen_swaph(). Signed-off-by: Philippe Mathieu-Daudé --- target/microblaze/translate.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/

[PATCH 4/6] target/sh4: Use hswap_i32() in SWAP.W opcode

Commit 46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}") introduced the generic hswap_i32(). Use it. Signed-off-by: Philippe Mathieu-Daudé --- target/sh4/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index

Re: [PATCH 2/6] target/cris: Use hswap_i32() in SWAPW opcode

On Tue, 22 Aug 2023 at 12:01, Philippe Mathieu-Daudé wrote: > > Commit 46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}") > introduced the generic hswap_i32(). Use it instead of open-coding > it as t_gen_swapw(). > > Signed-off-by: Philippe Mathieu-Daudé > --- > target/cris/translate.c

[PATCH v2 1/9] nvdimm: Reject writing label data to ROM instead of crashing QEMU

Currently, when using a true R/O NVDIMM (ROM memory backend) with a label area, the VM can easily crash QEMU by trying to write to the label area, because the ROM memory is mmap'ed without PROT_WRITE. [root@vm-0 ~]# ndctl disable-region region0 disabled 1 region [root@vm-0 ~]# ndctl ze

[PATCH v2 2/9] softmmu/physmem: Distinguish between file access mode and mmap protection

There is a difference between how we open a file and how we mmap it, and we want to support writable private mappings of readonly files. Let's define RAM_READONLY and RAM_READONLY_FD flags, to replace the single "readonly" parameter for file-related functions. In memory_region_init_ram_from_fd() a

[PATCH v2 0/9] memory-backend-file related improvements and VM templating support

This is the result of the previous discussion of: * "[PATCH v2] softmmu/physmem: try opening file readonly before failure in file_ram_open" [1] * "[PATCH v1 0/3] softmmu/physmem: file_ram_open() readonly improvements" [2] After looking into various ways to avoid a new parameter for memory-ba

[PATCH v2 4/9] softmmu/physmem: Remap with proper protection in qemu_ram_remap()

Let's remap with the proper protection that we can derive from RAM_READONLY. Signed-off-by: David Hildenbrand --- softmmu/physmem.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/softmmu/physmem.c b/softmmu/physmem.c index 16d7a16aa8..2ed83fcefe 100644 --- a/softm

[PATCH v2 3/9] backends/hostmem-file: Add "rom" property to support VM templating with R/O files

For now, "share=off,readonly=on" would always result in us opening the file R/O and mmap'ing the opened file MAP_PRIVATE R/O -- effectively turning it into ROM. Especially for VM templating, "share=off" is a common use case. However, that use case is impossible with files that lack write permissio

[PATCH v2 6/9] softmmu/physmem: Fail creation of new files in file_ram_open() with readonly=true

Currently, if a file does not exist yet, file_ram_open() will create new empty file and open it writable. However, it even does that when readonly=true was specified. Specifying O_RDONLY instead to create a new readonly file would theoretically work, however, ftruncate() will refuse to resize the

[PATCH v2 7/9] softmmu/physmem: Never return directories from file_ram_open()

open() does not fail on directories when opening them readonly (O_RDONLY). Currently, we succeed opening such directories and fail later during mmap(), resulting in a misleading error message. $ ./qemu-system-x86_64 \ -object memory-backend-file,id=ram0,mem-path=tmp,readonly=true,size=1g qem

[PATCH v2 5/9] softmmu/physmem: Bail out early in ram_block_discard_range() with readonly files

fallocate() will fail, let's print a nicer error message. Suggested-by: Peter Xu Signed-off-by: David Hildenbrand --- softmmu/physmem.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/softmmu/physmem.c b/softmmu/physmem.c index 2ed83fcefe..817a7811ee 100644 --- a/softmmu/physmem

[PATCH v2 9/9] docs: Start documenting VM templating

Let's add some details about VM templating, focusing on the VM memory configuration only. There is much more to VM templating (VM state? block devices?), but I leave that as future work. Signed-off-by: David Hildenbrand --- docs/vm-templating.txt | 109 +

[PATCH v2 8/9] docs: Don't mention "-mem-path" in multi-process.rst

"-mem-path" corresponds to "memory-backend-file,share=off" and, therefore, creates a private COW mapping of the file. For multi-proces QEMU, we need proper shared file-backed memory. Let's make that clearer. Signed-off-by: David Hildenbrand --- docs/devel/multi-process.rst | 5 +++-- 1 file cha

Re: [PATCH v2 00/10] block: Make raw_co_get_allocated_file_size asynchronous

Hi all, we currently have to maintain something downstream for this, since the current behavior can compound problems on top of existing bad NFS latency, could someone continue to help reviewing this work? Thanks, Claudio On 6/9/23 22:19, Fabiano Rosas wrote: > Hi, > > The major change from

Re: [PATCH 5/6] target/mips: Use hswap_i64() in DSHD opcode

On Tue, 22 Aug 2023 at 12:02, Philippe Mathieu-Daudé wrote: > > Commit 46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}") > introduced the generic hswap_i32(). Use it instead of open-coding > it in gen_bshfl(). > > Signed-off-by: Philippe Mathieu-Daudé > --- > target/mips/tcg/translate.c

Re: [PATCH V4 0/2] migration file URI

Hello, this series is all reviewed, and is needed as a precondition for further work to improve dramatically the performance of virsh save, virsh restore when migrating to disk, can it be merged? Thanks, Claudio On 6/30/23 16:25, Steve Sistare wrote: > Add the migration URI "file:filename[,of

Re: [PATCH v5 0/6] migration: Test the new "file:" migration

Hello, this series is all reviewed, and is needed as a precondition for further work to improve dramatically the performance of virsh save, virsh restore when migrating to disk, can it be merged? Thanks, Claudio On 7/12/23 21:07, Fabiano Rosas wrote: > Based-on: > [PATCH V4 0/2] migration fil

Re: [PATCH] migration/ram: Refactor precopy ram loading code

Hello, this patch is reviewed, and is needed as a precondition for further work to improve dramatically the performance of virsh save, virsh restore when migrating to disk, can it be merged? Thanks, Claudio On 7/25/23 15:26, Fabiano Rosas wrote: > From: Nikolay Borisov > > Extract the rambl

Re: [PATCH v2 4/4] migration/ram: Merge save_zero_page functions

Hello, this patch would still need a review, and is needed as a precondition for further work to improve dramatically the performance of virsh save, virsh restore when migrating to disk, since Peter Xu already reviewed PATCH 1, 2, 3, maybe it makes sense to look at 4 too? Thanks, Claudio On

Re: [PATCH v2 4/4] migration/ram: Merge save_zero_page functions

Apologies, already reviewed, will ping for the merge of the series momentarily, Claudio On 8/22/23 14:18, Claudio Fontana wrote: > Hello, > > this patch would still need a review, > > and is needed as a precondition for further work to improve dramatically the > performance of virsh save, virs

Re: [PATCH v2 0/4] migration/ram: Merge zero page handling

Hello, this series is all reviewed, and is needed as a precondition for further work to improve dramatically the performance of virsh save, virsh restore when migrating to disk, can it be merged? Thanks, Claudio On 8/16/23 20:28, Fabiano Rosas wrote: > For v2 I fixed patch 3 which had a hunk

[PATCH] target/loongarch: cpu: Implement get_arch_id callback

Implement the callback for getting the architecture-dependent CPU ID, the cpu ID is physical id described in ACPI MADT table, this will be used for cpu hotplug. Signed-off-by: Bibo Mao Change-Id: I53bcfb9f4279e491f33e8b99a9102534ad53409e --- hw/loongarch/virt.c| 2 ++ target/loongarch/cpu.c

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