On 8/1/2023 6:35 PM, Zhao Liu wrote:
From: Zhuocheng Ding
From CPUState.nr_cores' comment, it represents "number of cores within
this CPU package".
After 003f230e37d7 ("machine: Tweak the order of topology members in
struct CpuTopology"), the meaning of smp.cores changed to "the number of
cor
> -Original Message-
> From: Gavin Shan [mailto:gs...@redhat.com]
> Sent: 07 August 2023 06:53
> To: Shameerali Kolothum Thodi ;
> qemu-devel@nongnu.org; qemu-...@nongnu.org
> Cc: peter.mayd...@linaro.org; ricar...@google.com; k...@vger.kernel.org;
> Jonathan Cameron ; Linuxarm
>
> Subje
On Mon Aug 7, 2023 at 12:13 AM AEST, Richard Henderson wrote:
> On 8/6/23 05:55, Nicholas Piggin wrote:
> > On Sat Aug 5, 2023 at 7:33 AM AEST, Richard Henderson wrote:
> >> When a direct branch is out of range, we can load the destination for
> >> the indirect branch using PLA (for 16GB worth of b
(cc riscv maintainers)
On Mon, 31 Jul 2023 at 11:39, Ard Biesheuvel wrote:
>
> Use the accelerated SubBytes/ShiftRows/AddRoundKey AES helper to
> implement the first half of the key schedule derivation. This does not
> actually involve shifting rows, so clone the same uint32_t 4 times into
> the
On 7/28/2023 4:01 PM, Qian Wen wrote:
The legacy topology enumerated by CPUID.1.EBX[23:16] is defined in SDM
Vol2:
Bits 23-16: Maximum number of addressable IDs for logical processors in
this physical package.
To avoid data overflow, limit the max value written to EBX[23:16] to
255.
It's bett
Hi Xiaoyao,
On Mon, Aug 07, 2023 at 03:03:13PM +0800, Xiaoyao Li wrote:
> Date: Mon, 7 Aug 2023 15:03:13 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH v3 03/17] softmmu: Fix CPUSTATE.nr_cores' calculation
>
> On 8/1/2023 6:35 PM, Zhao Liu wrote:
> > From: Zhuocheng Ding
> >
> > From CPUState
On Fri, Jul 28, 2023 at 04:01:50PM +0800, Qian Wen wrote:
> Date: Fri, 28 Jul 2023 16:01:50 +0800
> From: Qian Wen
> Subject: [PATCH] target/i386: Avoid cpu number overflow in legacy topology
> X-Mailer: git-send-email 2.25.1
>
> The legacy topology enumerated by CPUID.1.EBX[23:16] is defined in
On Sun, 2023-08-06 at 13:05 +0200, Claudio Fontana wrote:
> On 8/5/23 01:03, Ilya Leoshkevich wrote:
> > Add a small test to prevent regressions.
> >
> > Signed-off-by: Ilya Leoshkevich
> > ---
> > tests/tcg/s390x/Makefile.target | 1 +
> > tests/tcg/s390x/vxeh2_vstrs.c | 88
> > +
On Sat, 2023-08-05 at 10:02 +0200, David Hildenbrand wrote:
> On 05.08.23 01:03, Ilya Leoshkevich wrote:
> > Currently the emulation of VSTRS recognizes partial matches in
> > presence
> > of \0 in the haystack, which, according to PoP, is not correct:
> >
> > If the ZS flag is one and a zero
On 8/1/2023 6:35 PM, Zhao Liu wrote:
From: Zhao Liu
Refer to the fixes of cache_info_passthrough ([1], [2]) and SDM, the
CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] should use the
nearest power-of-2 integer.
I doubt it. Especially for [1].
SDM doesn't state it should be the neare
On 2023/8/7 14:55, gaosong wrote:
Hi, Jiajie
在 2023/8/7 下午1:17, Jiajie Chen 写道:
On 2023/8/7 11:18, Jiajie Chen wrote:
The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
zero in LoongArch32.
Signed-off-by: Jiajie Chen
---
target/loongarch/cpu-csr.h | 9 +
On Sat, 5 Aug 2023 at 18:02, Richard Henderson
wrote:
>
> Mirror the host_arch variable from meson.build, so that we
> probe for the correct linux-user/include/host/ directory.
This broke all of the linux-user targets for me on a ppc64le host.
None show up when running configure --help, and tryin
Revert the changes in the recent "Fix linux-user host detection for
riscv64" patch as it broke ppc64le. Instead add riscv to the switch
statement that performs normalisation of the host cpu name.
Fixes: 89e5b7935e92 ("configure: Fix linux-user host detection for riscv64")
Signed-off-by: Joel Stanl
On 8/7/2023 3:53 PM, Zhao Liu wrote:
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 97ad229d8ba3..50613cd04612 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6011,7 +6011,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
X86CPUTopoInfo topo_in
On 8/7/23 10:08, Ilya Leoshkevich wrote:
> On Sun, 2023-08-06 at 13:05 +0200, Claudio Fontana wrote:
>> On 8/5/23 01:03, Ilya Leoshkevich wrote:
>>> Add a small test to prevent regressions.
>>>
>>> Signed-off-by: Ilya Leoshkevich
>>> ---
>>> tests/tcg/s390x/Makefile.target | 1 +
>>> tests/tcg/s
On Tue, 25 Jul 2023 18:39:56 +
Fan Ni wrote:
> From: Fan Ni
>
> Not all dpa range in the dc regions is valid to access until an extent
> covering the range has been added. Add a bitmap for each region to
> record whether a dc block in the region has been backed by dc extent.
> For the bitma
On 8/7/23 10:39, Joel Stanley wrote:
-case "$cpu" in
- riscv*)
-host_arch=riscv ;;
- *)
-host_arch="$cpu" ;;
-esac
-
# Normalise host CPU name and set multilib cflags. The canonicalization
# isn't really necessary, because the architectures that we check for
# should not hit t
Hi Xiaoyao,
On Mon, Aug 07, 2023 at 04:13:36PM +0800, Xiaoyao Li wrote:
> Date: Mon, 7 Aug 2023 16:13:36 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH v3 05/17] i386/cpu: Use APIC ID offset to encode cache
> topo in CPUID[4]
>
> On 8/1/2023 6:35 PM, Zhao Liu wrote:
> > From: Zhao Liu
> >
> >
container_hosts is matched against $cpu, so it must contain QEMU
canonical architecture names, not Debian architecture names.
Also do not set $container_hosts inside the loop, since it is
already set before.
Signed-off-by: Paolo Bonzini
---
configure | 3 +--
1 file changed, 1 insertion(+), 2 de
On Sat, 5 Aug 2023 at 17:44, Michael Tokarev wrote:
>
> 05.08.2023 15:51, Nathan Egge пишет:
> > From: "Nathan Egge"
> >
> > Signed-off-by: Nathan Egge
>
> This needs at least some meaningful subject prefix.
> With the subject like it is now, it feels like the
> patch is about fixing checkpatch.
The upstream kernel had added vector extensions support
See:
commit 616500232e632dba8b03981eeccadacf2fbf1c30
Author: Huacai Chen
Date: Thu Jun 29 20:58:43 2023
LoongArch: Add vector extensions support
Add LoongArch's vector extensions support, which including 128bit LSX
Current QEMU can expose waitpkg to guests when it is available. However,
VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE is still not recognized and
masked by QEMU. This can lead to an unexpected situation when a L1
hypervisor wants to expose waitpkg to a L2 guest. The L1 hypervisor can
assume that VMX_S
On Mon, 7 Aug 2023 09:53:42 +0100
Jonathan Cameron via wrote:
> On Tue, 25 Jul 2023 18:39:56 +
> Fan Ni wrote:
>
> > From: Fan Ni
> >
> > Not all dpa range in the dc regions is valid to access until an extent
> > covering the range has been added. Add a bitmap for each region to
> > recor
On Mon Aug 7, 2023 at 5:29 PM AEST, Nicholas Piggin wrote:
> On Mon Aug 7, 2023 at 12:13 AM AEST, Richard Henderson wrote:
> > On 8/6/23 05:55, Nicholas Piggin wrote:
> > > On Sat Aug 5, 2023 at 7:33 AM AEST, Richard Henderson wrote:
> > >> When a direct branch is out of range, we can load the dest
The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
zero in LoongArch32.
Signed-off-by: Jiajie Chen
---
target/loongarch/cpu-csr.h| 9 +
target/loongarch/tlb_helper.c | 17 -
2 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/target/loo
This commit adds loongarch32 mode to loongarch64-softmmu.
Signed-off-by: Jiajie Chen
---
target/loongarch/cpu.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index fa371ca8ba..43c73e6363 100644
--- a/target/loongarch/cpu.h
+++ b/target
Add la132 as a loongarch32 cpu type and allow virt machine to be used
with la132 instead of la464.
Signed-off-by: Jiajie Chen
---
hw/loongarch/virt.c| 5 -
target/loongarch/cpu.c | 41 +
target/loongarch/cpu.h | 11 +++
3 files changed, 52
GPRs and PC are 32-bit wide in loongarch32 mode.
Signed-off-by: Jiajie Chen
---
configs/targets/loongarch64-softmmu.mak | 2 +-
gdb-xml/loongarch-base32.xml| 45 +
target/loongarch/cpu.c | 10 +-
target/loongarch/gdbstub.c |
VPPN of TLBEHI/TLBREHI is limited to 19 bits in LA32.
Signed-off-by: Jiajie Chen
---
target/loongarch/cpu-csr.h| 6 --
target/loongarch/tlb_helper.c | 23 ++-
2 files changed, 22 insertions(+), 7 deletions(-)
diff --git a/target/loongarch/cpu-csr.h b/target/loongarc
This patch series allow qemu-system-loongarch64 to emulate a LoongArch32
machine. A mode enum is added to CPUArchState to select LA32 or LA64 at
runtime. A new CPU model is added for loongarch32. Initial GDB support
is added.
Changes since v2:
- Fix typo in previous commit
- Fix VPPN width in TLB
LA32 uses a different encoding for CSR.DMW and a new direct mapping
mechanism.
Signed-off-by: Jiajie Chen
---
target/loongarch/cpu-csr.h| 7 +++
target/loongarch/tlb_helper.c | 31 ---
2 files changed, 31 insertions(+), 7 deletions(-)
diff --git a/target/loo
Alpha and 31-bit s390 lack the assembly fragment to handle signals
occurring at the same time as system calls, so they cannot run
linux-user emulation anymore. Drop the host-signal.h files for
them.
Signed-off-by: Paolo Bonzini
---
linux-user/include/host/alpha/host-signal.h | 55
lin
x32 uses the same signal handling fragments as x86_64, since host_arch
is set to x86_64 when Meson runs. Remove the unnecessary forwarder and
set the host_arch variable properly in configure.
Signed-off-by: Paolo Bonzini
---
configure | 2 ++
linux-user/include/h
The CPU model has to be canonicalized to what Meson wants in the cross
file, to what Linux uses for its asm-$ARCH directories, and to what
QEMU uses for its user-mode emulation host/$ARCH directories. Do
all three in a single case statement, and check that the Linux and
QEMU directories actually e
The CPU model has to be canonicalized to what Meson wants in the cross
file, to what Linux uses for its asm-$ARCH directories, and to what
QEMU uses for its user-mode emulation host/$ARCH directories. Do
all three in a single case statement, and check that the Linux and
QEMU directories actually e
On 2023/8/7 17:45, Jiajie Chen wrote:
VPPN of TLBEHI/TLBREHI is limited to 19 bits in LA32.
Signed-off-by: Jiajie Chen
---
target/loongarch/cpu-csr.h| 6 --
target/loongarch/tlb_helper.c | 23 ++-
2 files changed, 22 insertions(+), 7 deletions(-)
diff --git a
Hi Xiaoyao,
On Mon, Aug 07, 2023 at 04:43:32PM +0800, Xiaoyao Li wrote:
> Date: Mon, 7 Aug 2023 16:43:32 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH v3 03/17] softmmu: Fix CPUSTATE.nr_cores' calculation
>
> On 8/7/2023 3:53 PM, Zhao Liu wrote:
> > > > diff --git a/target/i386/cpu.c b/target/i
On Fri, 4 Aug 2023 at 19:08, Peter Maydell wrote:
>
> On Wed, 2 Aug 2023 at 18:02, Jean-Philippe Brucker
> wrote:
> >
> > The AT instruction is UNDEFINED if the {NSE,NS} configuration is
> > invalid. Add a function to check this on all AT instructions that apply
> > to an EL lower than 3.
> >
> >
Hi,
On 2023/8/7 17:45, Jiajie Chen wrote:
Add la132 as a loongarch32 cpu type and allow virt machine to be used
with la132 instead of la464.
Signed-off-by: Jiajie Chen
---
hw/loongarch/virt.c| 5 -
target/loongarch/cpu.c | 41 +
target/loong
On 2023/8/7 17:54, WANG Xuerui wrote:
Hi,
On 2023/8/7 17:45, Jiajie Chen wrote:
Add la132 as a loongarch32 cpu type and allow virt machine to be used
with la132 instead of la464.
Signed-off-by: Jiajie Chen
---
hw/loongarch/virt.c | 5 -
target/loongarch/cpu.c | 41 +++
On Sat, 5 Aug 2023 09:00:41 +0300
Michael Tokarev wrote:
> 05.08.2023 08:58, Michael Tokarev wrote:
>
> > 196ea60a73 hw/smbios: Fix core count in type4
> > 7298fd7de5 hw/smbios: Fix thread count in type4
> > d79a284a44 hw/smbios: Fix smbios_smp_sockets caculation
>
> plus this one:
>
> a1d02
07.08.2023 12:56, Igor Mammedov wrote:
On Sat, 5 Aug 2023 09:00:41 +0300
Michael Tokarev wrote:
05.08.2023 08:58, Michael Tokarev wrote:
196ea60a73 hw/smbios: Fix core count in type4
7298fd7de5 hw/smbios: Fix thread count in type4
d79a284a44 hw/smbios: Fix smbios_smp_sockets caculation
plu
On 8/7/2023 3:36 PM, Xiaoyao Li wrote:
> On 7/28/2023 4:01 PM, Qian Wen wrote:
>> The legacy topology enumerated by CPUID.1.EBX[23:16] is defined in SDM
>> Vol2:
>>
>> Bits 23-16: Maximum number of addressable IDs for logical processors in
>> this physical package.
>>
>> To avoid data overflow, lim
On Mon, 7 Aug 2023 13:06:47 +0300
Michael Tokarev wrote:
> 07.08.2023 12:56, Igor Mammedov wrote:
> > On Sat, 5 Aug 2023 09:00:41 +0300
> > Michael Tokarev wrote:
[...]
> The whole thing - provided the preparational patch a1d027be95
> "machine: Add helpers to get cores/threads per socket" is als
On 8/7/2023 4:08 PM, Zhao Liu wrote:
> On Fri, Jul 28, 2023 at 04:01:50PM +0800, Qian Wen wrote:
>> Date: Fri, 28 Jul 2023 16:01:50 +0800
>> From: Qian Wen
>> Subject: [PATCH] target/i386: Avoid cpu number overflow in legacy topology
>> X-Mailer: git-send-email 2.25.1
>>
>> The legacy topology enu
On Tue, 1 Aug 2023 15:38:32 -0400
Stefan Berger wrote:
> On 7/31/23 23:02, Joelle van Dyne wrote:
> > On Mon, Jul 17, 2023 at 6:42 AM Igor Mammedov wrote:
> >>
> >> On Fri, 14 Jul 2023 13:21:33 -0400
> >> Stefan Berger wrote:
> >>
> >>> On 7/14/23 03:09, Joelle van Dyne wrote:
> This
On Tue, Jul 25, 2023 at 03:00:56PM -0400, John Snow wrote:
> On Tue, Jul 25, 2023 at 9:04 AM Philippe Mathieu-Daudé
> wrote:
> >
> > Hi Niklas, John, Paolo, Kevin,
> >
> > On 19/7/23 12:47, Niklas Cassel wrote:
> >
> > >> Niklas Cassel (8):
> > >>hw/ide/ahci: remove stray backslash
> > >>h
On Tue, 25 Jul 2023 18:39:56 +
Fan Ni wrote:
> From: Fan Ni
>
> Since fabric manager emulation is not supported yet, the change implements
> the functions to add/release dynamic capacity extents as QMP interfaces.
>
> 1. Add dynamic capacity extents:
>
> For example, the command to add tw
The following changes since commit 9400601a689a128c25fa9c21e932562e0eeb7a26:
Merge tag 'pull-tcg-20230806-3' of https://gitlab.com/rth7680/qemu into
staging (2023-08-06 16:47:48 -0700)
are available in the Git repository at:
https://gitlab.com/mjt0k/qemu.git tags/trivial-patches-pull
for y
From: Luca Bonissi
OpenRISC (or1k) has long long alignment to 4 bytes, but currently not
defined in abitypes.h. This lead to incorrect packing of /epoll_event/
structure and eventually infinite loop while waiting for file
descriptor[s] event[s].
Fixed also CRIS alignments (1 byte for all types).
Signed-off-by: Michael Tokarev
---
stubs/colo.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/stubs/colo.c b/stubs/colo.c
index f33379d0fd..08c9f982d5 100644
--- a/stubs/colo.c
+++ b/stubs/colo.c
@@ -21,7 +21,7 @@ void colo_checkpoint_delay_set(void)
void migrate_start_co
From: BALATON Zoltan
The clock and data values were logged swapped. Correct the trace event
text to match what is logged. Also fix a typo in a comment nearby.
Signed-off-by: BALATON Zoltan
Signed-off-by: Michael Tokarev
---
hw/i2c/bitbang_i2c.c | 2 +-
hw/i2c/trace-events | 2 +-
2 files cha
Queued, thanks.
Paolo
On Tue, 25 Jul 2023 18:39:56 +
Fan Ni wrote:
> From: Fan Ni
>
> Per CXL spec 3.0, two mailbox commands are implemented:
> Add Dynamic Capacity Response (Opcode 4802h) 8.2.9.8.9.3, and
> Release Dynamic Capacity (Opcode 4803h) 8.2.9.8.9.4.
>
> Signed-off-by: Fan Ni
I'm reviewing these bac
Add small softmmu and user tests to prevent regressions.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.softmmu-target | 1 +
tests/tcg/s390x/Makefile.target | 1 +
tests/tcg/s390x/precise-smc-softmmu.S | 63 +
tests/tcg/s390x/precise-smc-user.c
PoP (Sequence of Storage References -> Instruction Fetching) says:
... if a store that is conceptually earlier is
made by the same CPU using the same effective
address as that by which the instruction is subse-
quently fetched, the updated information is obtained ...
QEMU already
From: Klaus Jensen
As reported by Trend Micro's Zero Day Initiative, an oob memory read
vulnerability exists in nvme_fdp_events(). The host-provided offset is
not verified.
Fix this.
This is only exploitable when Flexible Data Placement mode (fdp=on) is
enabled.
Fixes: CVE-2023-4135
Fixes: 730
在 2023/8/7 下午5:45, Jiajie Chen 写道:
VPPN of TLBEHI/TLBREHI is limited to 19 bits in LA32.
Signed-off-by: Jiajie Chen
---
target/loongarch/cpu-csr.h| 6 --
target/loongarch/tlb_helper.c | 23 ++-
2 files changed, 22 insertions(+), 7 deletions(-)
diff --git a/targ
Hi
On Tue, Jul 25, 2023 at 4:35 AM Dongwon Kim wrote:
>
> Fixing a regression (black screen) caused by a commit 92b58156e7
> ("ui/gtk: set scanout-mode right before scheduling draw").
>
> The commit 92b58156e7 was made with an assumption that the scanout
> mode needs to be set only if the guest s
From: Klaus Jensen
As of prior to this patch, the controller checks the value of CC.IOCQES
and CC.IOSQES prior to enabling the controller. As reported by Ben in
GitLab issue #1691, this is not spec compliant. The controller should
only check these values when queues are created.
This patch moves
From: Klaus Jensen
Hi,
The following changes since commit 9400601a689a128c25fa9c21e932562e0eeb7a26:
Merge tag 'pull-tcg-20230806-3' of https://gitlab.com/rth7680/qemu into
staging (2023-08-06 16:47:48 -0700)
are available in the Git repository at:
https://gitlab.com/birkelund/qemu.git ta
On Tue, 25 Jul 2023 18:39:56 +
Fan Ni wrote:
> From: Fan Ni
>
> Add dynamic capacity extent list representative to the definition of
> CXLType3Dev and add get DC extent list mailbox command per
> CXL.spec.3.0:.8.2.9.8.9.2.
>
> Signed-off-by: Fan Ni
A couple of general name format changes
On 2023/8/7 19:53, gaosong wrote:
在 2023/8/7 下午5:45, Jiajie Chen 写道:
VPPN of TLBEHI/TLBREHI is limited to 19 bits in LA32.
Signed-off-by: Jiajie Chen
---
target/loongarch/cpu-csr.h | 6 --
target/loongarch/tlb_helper.c | 23 ++-
2 files changed, 22 insertions(
On Fri, 4 Aug 2023 14:07:55 -0400
Gregory Price wrote:
> On Fri, Aug 04, 2023 at 05:36:23PM +0100, Jonathan Cameron wrote:
> > On Tue, 25 Jul 2023 18:39:56 +
> > Fan Ni wrote:
> >
> > > From: Fan Ni
> > >
> > > Add (file/memory backed) host backend, all the dynamic capacity regions
> >
Core dumps produced by gdb's gcore when connected to qemu's gdbstub
lack stack. The reason is that gdb includes only anonymous memory in
core dumps, which is distinguished by a non-0 Anonymous: value.
Consider the mappings with PAGE_ANON fully anonymous, and the mappings
without it fully non-anony
Hi, Richard
Richard Henderson wrote:
>
> On 5/18/23 13:04, Taylor Simpson wrote:
> > From: Matheus Tavares Bernardino
> >
> > In the previous commit, we modified gdbstub.c to only send stop-reply
> > packets as a response to GDB commands that accept it. Now, let's add a
> > test for this intend
On 8/7/23 11:48, Paolo Bonzini wrote:
armv*b|armv*l|arm)
cpu="arm" ;;
Oops, sent a stale patchset. The only difference is this extra ;;
Paolo
On Mon, 7 Aug 2023 at 10:49, Paolo Bonzini wrote:
>
> The CPU model has to be canonicalized to what Meson wants in the cross
> file, to what Linux uses for its asm-$ARCH directories, and to what
> QEMU uses for its user-mode emulation host/$ARCH directories. Do
> all three in a single case statem
On Mon, Aug 07, 2023 at 10:54:05AM +0100, Peter Maydell wrote:
> On Fri, 4 Aug 2023 at 19:08, Peter Maydell wrote:
> >
> > On Wed, 2 Aug 2023 at 18:02, Jean-Philippe Brucker
> > wrote:
> > >
> > > The AT instruction is UNDEFINED if the {NSE,NS} configuration is
> > > invalid. Add a function to ch
For an Unsupported Atomic Update fault where the stage 1 translation
table descriptor update can't be done because it's to an unsupported
memory type, this is a stage 1 abort (per the Arm ARM R_VSXXT). This
means we should not set fi->s1ptw, because this will cause the code
in the get_phys_addr_lp
While I was fixing a ptw bug recently, I noticed that we had a
somewhat confusing mix of ptw->in_space and ptw->in_secure, where in
theory the two are supposed to be in sync and you can figure out the
in_secure state from the in_space. This patch series' principal aim
is to clean that up by removi
In S1_ptw_translate() we set up the ARMMMUFaultInfo if the attempt to
translate the page descriptor address into a physical address fails.
This used to only be possible if we are doing a stage 2 ptw for that
descriptor address, and so the code always sets fi->stage2 and
fi->s1ptw to true. However,
Plumb the ARMSecurityState through to regime_translation_disabled()
rather than just a bool is_secure.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/ptw.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/arm/ptw.c b/target/a
When we do a translation in Secure state, the NSTable bits in table
descriptors may downgrade us to NonSecure; we update ptw->in_secure
and ptw->in_space accordingly. We guard that check correctly with a
conditional that means it's only applied for Secure stage 1
translations. However, later on i
When we report faults due to stage 2 faults during a stage 1
page table walk, the 'level' parameter should be the level
of the walk in stage 2 that faulted, not the level of the
walk in stage 1. Correct the reporting of these faults.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
--
The PAR_EL1.SH field documents that for the cases of:
* Device memory
* Normal memory with both Inner and Outer Non-Cacheable
the field should be 0b10 rather than whatever was in the
translation table descriptor field. (In the pseudocode this
is handled by PAREncodeShareability().) Perform this
a
Pass an ARMSecuritySpace instead of a bool secure to
arm_is_el2_enabled_secstate(). This doesn't change behaviour.
Signed-off-by: Peter Maydell
---
target/arm/cpu.h| 13 -
target/arm/helper.c | 2 +-
2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/target/arm/cpu.h
The s1ns bit in ARMMMUFaultInfo is documented as "true if
we faulted on a non-secure IPA while in secure state". Both the
places which look at this bit only do so after having confirmed
that this is a stage 2 fault and we're dealing with Secure EL2,
which leaves the ptw.c code free to set the bit t
In commit 6d2654ffacea813916176 we created the S1Translate struct and
used it to plumb through various arguments that we were previously
passing one-at-a-time to get_phys_addr_v5(), get_phys_addr_v6(), and
get_phys_addr_lpae(). Extend that pattern to get_phys_addr_pmsav5(),
get_phys_addr_pmsav7(),
Replace the last uses of ptw->in_secure with appropriate
checks on ptw->in_space.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/ptw.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 6e736bacd7
We no longer look at the in_secure field of the S1Translate struct
anyway, so we can remove it and all the code which sets it.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/ptw.c | 13 -
1 file changed, 13 deletions(-)
diff --git a/target/arm/ptw.c b/ta
The architecture doesn't permit block descriptors at any arbitrary
level of the page table walk; it depends on the granule size which
levels are permitted. We implemented only a partial version of this
check which assumes that block descriptors are valid at all levels
except level 3, which meant t
We only use S1Translate::out_secure in two places, where we are
setting up MemTxAttrs for a page table load. We can use
arm_space_is_secure(ptw->out_space) instead, which guarantees
that we're setting the MemTxAttrs secure and space fields
consistently, and allows us to drop the out_secure field in
arm_hcr_el2_eff_secstate() takes a bool secure, which it uses to
determine whether EL2 is enabled in the current security state.
With the advent of FEAT_RME this is no longer sufficient, because
EL2 can be enabled for Secure state but not for Root, and both
of those will pass 'secure == true' in th
When the MMU is disabled, data accesses should be Device nGnRnE,
Outer Shareable, Untagged. We handle the other cases from
AArch64.S1DisabledOutput() correctly but missed this one.
Device nGnRnE is memattr == 0, so the only part we were missing
was that shareability should be set to 2 for both ins
One of notdirty_write()'s responsibilities is detecting self-modifying
code. Some functions pass the full size of a write to it, some pass 1.
When a write to a code section begins before a TB start, but then
overlaps the TB, the paths that pass 1 don't flush a TB and don't
return to the translator
Hi,
this is the fix for an issue I complained about a few days back on the
IRC. Unfortunately my reproducer [1] does not work anymore, so I'm
sending this separately and as an RFC.
The user-visible effect was that:
- If a TB writes to itself;
- The address of the write is before the TB start;
-
On 8/7/2023 6:00 PM, Zhao Liu wrote:
Hi Xiaoyao,
On Mon, Aug 07, 2023 at 04:43:32PM +0800, Xiaoyao Li wrote:
Date: Mon, 7 Aug 2023 16:43:32 +0800
From: Xiaoyao Li
Subject: Re: [PATCH v3 03/17] softmmu: Fix CPUSTATE.nr_cores' calculation
On 8/7/2023 3:53 PM, Zhao Liu wrote:
diff --git a/targe
Hi Igor,
On Mon, Aug 07, 2023 at 12:11:29PM +0200, Igor Mammedov wrote:
> Date: Mon, 7 Aug 2023 12:11:29 +0200
> From: Igor Mammedov
> Subject: Re: [PATCH v2 2/3] hw/smbios: Fix thread count in type4
> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; x86_64-redhat-linux-gnu)
>
> On Mon, 7 Aug 2023 13:06
Hello,
On 04/08/2023 01:54, Gurchetan Singh wrote:
> Prior versions:
>
> https://lists.gnu.org/archive/html/qemu-devel/2023-07/msg05801.html
>
> https://lists.gnu.org/archive/html/qemu-devel/2023-07/msg02341.html
>
> https://patchew.org/QEMU/20230421011223.718-1-gurchetansi...@chromium.org/
>
On Fri, 28 Jul 2023 10:20:05 +0800
zhenwei pi wrote:
> 'bool is_write' style is obsolete from throttle framework, adapt
> fsdev to the new style.
>
> Cc: Greg Kurz
> Reviewed-by: Hanna Czenczek
> Signed-off-by: zhenwei pi
Reviewed-by: Greg Kurz
> ---
> fsdev/qemu-fsdev-throttle.c | 14 +++
The tcg uses tgen_arithi(ARITH_AND) during fast CPU TLB lookups,
which e.g. translates to:
0x7ff5b011556a: 48 81 e6 00 f0 ff ff andq $0xf000, %rsi
In case the upper 48 bits are all set, the shorter sequence to operate
on the lower 16 bits of the target reg (si) can be used, w
On Fri, 4 Aug 2023 12:41:26 -0400
Gregory Price wrote:
> On Fri, Aug 04, 2023 at 04:14:14PM +0100, Jonathan Cameron wrote:
> > On Fri, 21 Jul 2023 12:35:06 -0400
> > Gregory Price wrote:
> >
> > > This enables wrapper devices to customize the base device's CCI
> > > (for example, with custom
Hi Xiaoyao,
[snip]
>
> I see.
>
> Can we pull the patch into this series (define a common CPUTopoInfo in
> CPUState and drop env->nr_dies, cs->nr_cores and cs->nr_threads) and let the
> hybrid series later to rename it to X86ApicidTopoInfo?
>
Yes, we can spilt these from hybrid series.
But if
Il lun 7 ago 2023, 15:45 Peter Maydell ha
scritto:
> Can we be consistent within this case statement about whether
> the ';;' is on its own line or at the end of the last line of
> the case ? We are not fully consistent within the entire
> configure script, but mostly we put it on a line of its
>
Hi,
It's been a while since review was done and nothing happened with those patches
since then.
As I understand from guide:
https://www.qemu.org/docs/master/devel/submitting-a-patch.html#is-my-patch-in I
should wait. Is that correct?
-Original Message-
From: Akihiko Odaki
Sent: wtor
On Fri, 21 Jul 2023 12:35:08 -0400
Gregory Price wrote:
> Implement the MHD GET_INFO cci command and add a shared memory
> region to the type3 device to host the information.
>
> Add a helper program to initialize this shared memory region.
>
> Add a function pointer to type3 devices for future
The architecture requires (R_TYTWB) that an attempt to return from EL3
when SCR_EL3.{NSE,NS} are {1,0} is an illegal exception return. (This
enforces that the CPU can't ever be executing below EL3 with the
NSE,NS bits indicating an invalid security state.)
We were missing this check; add it.
Sign
On Mon, 7 Aug 2023 at 15:03, Jean-Philippe Brucker
wrote:
>
> On Mon, Aug 07, 2023 at 10:54:05AM +0100, Peter Maydell wrote:
> > On Fri, 4 Aug 2023 at 19:08, Peter Maydell wrote:
> > >
> > > On Wed, 2 Aug 2023 at 18:02, Jean-Philippe Brucker
> > > wrote:
> > > >
> > > > The AT instruction is UND
On 8/7/23 02:45, Jiajie Chen wrote:
This commit adds loongarch32 mode to loongarch64-softmmu.
Signed-off-by: Jiajie Chen
---
target/loongarch/cpu.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index fa371ca8ba..43c73e6363 100644
-
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