PoP (Sequence of Storage References -> Instruction Fetching) says:
... if a store that is conceptually earlier is
made by the same CPU using the same effective
address as that by which the instruction is subse-
quently fetched, the updated information is obtained ...
QEMU already has support for this in the common code; enable it for
s390x.
Signed-off-by: Ilya Leoshkevich <i...@linux.ibm.com>
---
target/s390x/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index eb5b65b7d3a..304029e57cf 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -36,6 +36,8 @@
/* The z/Architecture has a strong memory model with some store-after-load
re-ordering */
#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
+#define TARGET_HAS_PRECISE_SMC
+
#define TARGET_INSN_START_EXTRA_WORDS 2
#define MMU_USER_IDX 0
--
2.41.0
