When CR0.TS=1, execution of x87 FPU, MMX, and some SSE instructions will
cause a Device Not Available (DNA) exception (#NM). System software uses
this exception event to lazily context switch FPU state.
Before this patch, enter_mmx helpers may be generated just before #NM
generation, prematurely r
On 12/07/23 6:25 pm, Markus Armbruster wrote:
The subject
migration: introduced 'MigrateAddress' in QAPI for migration wire protocol.
is rather long. Try to limit subjects to about 60 characters. Easily
done here:
migration: New QAPI type 'MigrateAddress'
Ack. Thanks for the sug
We check the in-kernel irqchip support when using KVM acceleration.
Signed-off-by: Yong-Xuan Wang
Reviewed-by: Jim Shu
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/kvm.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/target/riscv/kvm.c b/target/riscv/kvm
This series adds support for KVM AIA in RISC-V architecture.
In order to test these patches, we require Linux with KVM AIA support which can
be found in the riscv_kvm_aia_hwaccel_v1 branch at
https://github.com/avpatel/linux.git
---
v5:
- remove the linux-header update patch since the riscv-to-ap
Select KVM AIA when the host kernel has in-kernel AIA chip support.
Since KVM AIA only has one APLIC instance, we map the QEMU APLIC
devices to KVM APLIC.
We also extend virt machine to specify the KVM AIA mode. The "kvm-aia"
parameter is passed along with machine name in QEMU command-line.
1) "kvm
KVM AIA can't emulate APLIC only. When "aia=aplic" parameter is passed,
APLIC devices is emulated by QEMU. For "aia=aplic-imsic", remove the
mmio operations of APLIC when using KVM AIA and send wired interrupt
signal via KVM_IRQ_LINE API.
After KVM AIA enabled, MSI messages are delivered by KVM_SIG
We create a vAIA chip by using the KVM_DEV_TYPE_RISCV_AIA and then set up
the chip with the KVM_DEV_RISCV_AIA_GRP_* APIs.
Signed-off-by: Yong-Xuan Wang
Reviewed-by: Jim Shu
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/kvm.c | 160 +++
target/r
In this patch, we create the APLIC and IMSIC FDT helper functions and
remove M mode AIA devices when using KVM acceleration.
Signed-off-by: Yong-Xuan Wang
Reviewed-by: Jim Shu
Reviewed-by: Daniel Henrique Barboza
---
hw/riscv/virt.c | 264 ++--
1 fil
On 21/06/2023 09.41, Thomas Huth wrote:
It's possible to compile QEMU without the USB devices (e.g. when using
"--without-default-devices" as option for the "configure" script).
To be still able to run the loongson3-virt machine in default mode with
such a QEMU binary, we have to check here for t
On Thu, Jul 13, 2023 at 08:43:53AM +, Yong-Xuan Wang wrote:
> In this patch, we create the APLIC and IMSIC FDT helper functions and
> remove M mode AIA devices when using KVM acceleration.
>
> Signed-off-by: Yong-Xuan Wang
> Reviewed-by: Jim Shu
> Reviewed-by: Daniel Henrique Barboza
> ---
On Thu, Jul 13, 2023 at 08:43:54AM +, Yong-Xuan Wang wrote:
> We check the in-kernel irqchip support when using KVM acceleration.
>
> Signed-off-by: Yong-Xuan Wang
> Reviewed-by: Jim Shu
> Reviewed-by: Daniel Henrique Barboza
> ---
> target/riscv/kvm.c | 10 +-
> 1 file changed, 9
On Thu, Jul 13, 2023 at 08:43:55AM +, Yong-Xuan Wang wrote:
> We create a vAIA chip by using the KVM_DEV_TYPE_RISCV_AIA and then set up
> the chip with the KVM_DEV_RISCV_AIA_GRP_* APIs.
>
> Signed-off-by: Yong-Xuan Wang
> Reviewed-by: Jim Shu
> Reviewed-by: Daniel Henrique Barboza
> ---
>
Cc'ing the qemu-block@ list.
On 13/7/23 04:03, Ross Vandegrift wrote:
Hi folks,
I'm trying to qemu-img convert a source that's hoted on s3, via a
presigned url. When qemu-img hits it, s3 returns a 403. But curl works
fine with the same url.
I didn't see any debugging or verbose output option
On Thu, Jul 13, 2023 at 08:43:57AM +, Yong-Xuan Wang wrote:
> Select KVM AIA when the host kernel has in-kernel AIA chip support.
> Since KVM AIA only has one APLIC instance, we map the QEMU APLIC
> devices to KVM APLIC.
> We also extend virt machine to specify the KVM AIA mode. The "kvm-aia"
>
Hi Thomas,
On 21/6/23 09:41, Thomas Huth wrote:
It's possible to compile QEMU without the USB devices (e.g. when using
"--without-default-devices" as option for the "configure" script).
To be still able to run the loongson3-virt machine in default mode with
such a QEMU binary, we have to check h
This patch introduces well defined MigrateAddress struct
and its related child objects.
The existing argument of 'migrate' and 'migrate-incoming' QAPI
- 'uri' is of type string. The current implementation follows
double encoding scheme for fetching migration parameters like
'uri' and this is not a
Exec transport backend for 'migrate'/'migrate-incoming' QAPIs accept
new wire protocol of MigrateAddress struct.
It is achived by parsing 'uri' string and storing migration parameters
required for exec connection into strList struct.
Suggested-by: Aravind Retnakaran
Signed-off-by: Het Gala
---
migration_channels_and_uri_compatible() check for transport mechanism
suitable for multifd migration gets executed when the caller calls old
uri syntax. It needs it to be run when using the modern MigrateChannel
QAPI syntax too.
After URI -> 'MigrateChannel' :
migration_channels_and_uri_compatible
This patch parses 'migrate' and 'migrate-incoming' QAPI's 'uri'
string containing migration connection related information
and stores them inside well defined 'MigrateAddress' struct.
Misc: limit line width in exec.c to 80 char recommended by Qemu.
Suggested-by: Aravind Retnakaran
Signed-off-by:
Add multifd tcp common test case for new QAPI syntax defined.
Suggested-by: Aravind Retnakaran
Signed-off-by: Het Gala
---
tests/qtest/migration-test.c | 45
1 file changed, 45 insertions(+)
diff --git a/tests/qtest/migration-test.c b/tests/qtest/migration-
Integrate MigrateChannelList with all transport backends
(socket, exec and rdma) for both src and dest migration
endpoints.
Suggested-by: Aravind Retnakaran
Signed-off-by: Het Gala
---
migration/migration.c | 77 ---
migration/socket.c| 5 ++-
2 file
RDMA based transport backend for 'migrate'/'migrate-incoming' QAPIs
accept new wire protocol of MigrateAddress struct.
It is achived by parsing 'uri' string and storing migration parameters
required for RDMA connection into well defined InetSocketAddress struct.
Suggested-by: Aravind Retnakaran
This is v8 patchset of modified 'migrate' and 'migrate-incoming' QAPI design
for upstream review.
Would like to thank all the maintainers that actively participated in the v7
patchset discussion and gave insightful suggestions to improve the patches.
Link to previous upstream community patchset
MigrateChannelList allows to connect accross multiple interfaces.
Add MigrateChannelList struct as argument to migration QAPIs.
We plan to include multiple channels in future, to connnect
multiple interfaces. Hence, we choose 'MigrateChannelList'
as the new argument over 'MigrateChannel' to make m
Socket transport backend for 'migrate'/'migrate-incoming' QAPIs accept
new wire protocol of MigrateAddress struct.
It is achived by parsing 'uri' string and storing migration parameters
required for socket connection into well defined SocketAddress struct.
Suggested-by: Aravind Retnakaran
Signed
Ping
Patch series on patchew:
https://patchew.org/QEMU/cover.1686238728.git.manos.pitsidiana...@linaro.org/
Patch series on lore:
https://lore.kernel.org/qemu-devel/cover.1686238728.git.manos.pitsidiana...@linaro.org/
On Thu, 08 Jun 2023 18:56, Manos Pitsidianakis
wrote:
This patch series
On Thu, 6 Jul 2023 at 20:52, Fabiano Rosas wrote:
>
> The convention in qemu-file.c is to return a negative value on
> error.
>
> The only place that could use qemu_file_set_error() to store a
> positive value to f->last_error was vmstate_save() which has been
> fixed in the previous patch.
>
> bd
On Fri, 7 Jul 2023 at 11:30, Richard Henderson
wrote:
>
> Read the left and right trees once, so that the gating
> tests are meaningful. This was only a problem at -O0,
> where the compiler didn't CSE the two reads.
>
> Cc: qemu-sta...@nongnu.org
> Signed-off-by: Richard Henderson
Reviewed-by:
On Mon, 10 Jul 2023 at 07:38, Yuquan Wang wrote:
>
> As the default xhci_sysbus just supports only one usb slot, it can not
> meet the working requirement of this bord. Therefore, we extend the
> slots of xhci to 64.
>
> Yuquan Wang (1):
> hw/arm/sbsa-ref: set 'slots' property of xhci
>
> hw/ar
On Wed, Jul 12, 2023 at 06:38:14PM +0200, Paolo Bonzini wrote:
On 7/12/23 15:43, Stefano Garzarella wrote:
Commit 1880ad4f4e ("virtio-scsi: Batched prepare for cmd reqs") split
calls to scsi_req_new() and scsi_req_enqueue() in the virtio-scsi device.
This had no drawback, until commit 8cc5583abe
On Thu, 13 Jul 2023 at 06:45, Gavin Shan wrote:
>
> There is a generic CPU type invalidation in machine_run_board_init()
> and we needn't a same and private invalidation for hw/arm/virt machines.
> This series intends to use the generic CPU type invalidation on the
> hw/arm/virt machines.
>
> PATC
13.07.2023 13:09, Philippe Mathieu-Daudé wrote:
Hi Thomas,
On 21/6/23 09:41, Thomas Huth wrote:
It's possible to compile QEMU without the USB devices (e.g. when using
"--without-default-devices" as option for the "configure" script).
To be still able to run the loongson3-virt machine in default
On 13/07/2023 13.47, Michael Tokarev wrote:
13.07.2023 13:09, Philippe Mathieu-Daudé wrote:
Hi Thomas,
On 21/6/23 09:41, Thomas Huth wrote:
It's possible to compile QEMU without the USB devices (e.g. when using
"--without-default-devices" as option for the "configure" script).
To be still able
W dniu 13.07.2023 o 13:44, Peter Maydell pisze:
I see this isn't a change in this patch, but given that
what the user specifies is not "cortex-a8-arm-cpu" but
"cortex-a8", why do we include the "-arm-cpu" suffix in
the error messages? It's not valid syntax to say
"-cpu cortex-a8-arm-cpu", so it'
On Thu, 13 Jul 2023 at 12:52, Marcin Juszkiewicz
wrote:
>
> W dniu 13.07.2023 o 13:44, Peter Maydell pisze:
>
> > I see this isn't a change in this patch, but given that
> > what the user specifies is not "cortex-a8-arm-cpu" but
> > "cortex-a8", why do we include the "-arm-cpu" suffix in
> > the e
In replacing target_ulong with vaddr and TARGET_FMT_lx with VADDR_PRIx,
the zero-padding of TARGET_FMT_lx got lost. Readd 16-wide zero-padding
for logging consistency.
Suggested-by: Peter Maydell
Signed-off-by: Anton Johansson
---
accel/tcg/cputlb.c | 20 ++--
1 file changed, 1
The self assignment is clearly useless, and @1.last_column does not have
to be set for an expression with only a single token, so remove it.
Reported-by: Peter Maydell
Signed-off-by: Anton Johansson
---
target/hexagon/idef-parser/idef-parser.y | 1 -
1 file changed, 1 deletion(-)
diff --git a/
~hyman writes:
> From: Hyman Huang(黄勇)
>
> Introduce "x-vcpu-dirty-limit-period" migration experimental
> parameter, which is in the range of 1 to 1000ms and used to
> make dirtyrate calculation period configurable.
dirty rate
>
> Currently with the "x-vcpu-dirty-limit-period" varies, the
Cur
Hi Peter and Marcin,
On 7/13/23 21:52, Marcin Juszkiewicz wrote:
W dniu 13.07.2023 o 13:44, Peter Maydell pisze:
I see this isn't a change in this patch, but given that
what the user specifies is not "cortex-a8-arm-cpu" but
"cortex-a8", why do we include the "-arm-cpu" suffix in
the error mess
Hi Steve,
On 2023/7/10 23:43, Steven Sistare wrote:
On 7/5/2023 4:56 AM, Kunkun Jiang wrote:
Hi Steve,
I have a few questions about the msi part of the vfio device.
In the reboot mode, you mentioned "The guest drivers' suspend methods
flush outstanding requests and re-initialize the devices".
On Fri, 7 Jul 2023 at 11:29, Richard Henderson
wrote:
>
> Off by one error, failing to take into account that layout_arg_1
> already incremeneted info_in_idx for the first piece. We only
> need care for the n-1 TCG_CALL_ARG_BY_REF_N pieces here.
>
> Cc: qemu-sta...@nongnu.org
> Fixes: 313bdea84d2
On Thu, 13 Jul 2023 13:35:57 +0100,
Kunkun Jiang wrote:
>
> For ARM, it will first send a DISCARD command to ITS and then
> establish the interrupt reporting channel for GICv3. The DISCARD
> will remove the pending interrupt. Interrupts that come before
> channel re-establishment are silently dis
Hi Peter,
On 7/13/23 21:44, Peter Maydell wrote:
On Thu, 13 Jul 2023 at 06:45, Gavin Shan wrote:
There is a generic CPU type invalidation in machine_run_board_init()
and we needn't a same and private invalidation for hw/arm/virt machines.
This series intends to use the generic CPU type invali
W dniu 13.07.2023 o 14:34, Gavin Shan pisze:
On 7/13/23 21:52, Marcin Juszkiewicz wrote:
W dniu 13.07.2023 o 13:44, Peter Maydell pisze:
I see this isn't a change in this patch, but given that what the
user specifies is not "cortex-a8-arm-cpu" but "cortex-a8", why
do we include the "-arm-cpu"
~hyman writes:
> From: Hyman Huang(黄勇)
>
> Introduce migration dirty-limit capability, which can
> be turned on before live migration and limit dirty
> page rate durty live migration.
>
> Introduce migrate_dirty_limit function to help check
> if dirty-limit capability enabled during live migrati
~hyman writes:
> From: Hyman Huang(黄勇)
>
> Extend query-migrate to provide throttle time and estimated
> ring full time with dirty-limit capability enabled, through which
> we can observe if dirty limit take effect during live migration.
>
> Signed-off-by: Hyman Huang(黄勇)
> Reviewed-by: Markus
On Thu, Jul 13 2023, Gavin Shan wrote:
> The CPU type 'host-arm-cpu' class won't be registered until KVM or
> HVF is configured in target/arm/cpu64.c. Support the corresponding
> CPU type only when KVM or HVF is configured.
>
> Signed-off-by: Gavin Shan
> ---
> hw/arm/virt.c | 2 ++
> 1 file ch
Hi Marcin,
On 7/13/23 22:44, Marcin Juszkiewicz wrote:
W dniu 13.07.2023 o 14:34, Gavin Shan pisze:
On 7/13/23 21:52, Marcin Juszkiewicz wrote:
W dniu 13.07.2023 o 13:44, Peter Maydell pisze:
I see this isn't a change in this patch, but given that what the user specifies is not
"cortex-a8-a
On 7/12/23 23:51, Joelle van Dyne wrote:
The impetus for this patch set is to get TPM 2.0 working on Windows 11 ARM64.
Windows' tpm.sys does not seem to work on a TPM TIS device (as verified with
VMWare's implementation). However, the current TPM CRB device uses a fixed
system bus address that
I'll take this via target-arm.next unless there are any
objections...
thanks
-- PMM
On Tue, 4 Jul 2023 at 14:26, Peter Maydell wrote:
>
> Laurent, ping? This patch has been reviewed.
>
> thanks
> -- PMM
>
> On Fri, 23 Jun 2023 at 15:44, Peter Maydell wrote:
> >
> > In the code for TARGET_NR_clo
On 7/12/23 23:51, Joelle van Dyne wrote:
TPM needs to know its own base address in order to generate its DSDT
device entry.
This and the loongarch patch seem to have largely identical virt_tpm_plug
functions.
Could they be consolidated in hw/tpm/virt.c ?
Stefan
Signed-off-by: Joelle
Hi Connie,
On 7/13/23 22:46, Cornelia Huck wrote:
On Thu, Jul 13 2023, Gavin Shan wrote:
The CPU type 'host-arm-cpu' class won't be registered until KVM or
HVF is configured in target/arm/cpu64.c. Support the corresponding
CPU type only when KVM or HVF is configured.
Signed-off-by: Gavin Sha
Peter Maydell writes:
> On Thu, 6 Jul 2023 at 20:52, Fabiano Rosas wrote:
>>
>> The convention in qemu-file.c is to return a negative value on
>> error.
>>
>> The only place that could use qemu_file_set_error() to store a
>> positive value to f->last_error was vmstate_save() which has been
>> fi
QEMU Summit Minutes 2023
As usual, we held a QEMU Summit meeting at KVM Forum. This is an
invite-only meeting for the most active maintainers and submaintainers
in the project, and we discuss various project-wide issues, usually
process stuff. We then post the minutes of
On 7/12/23 23:51, Joelle van Dyne wrote:
In preparation for the SysBus variant, we move common code styled
after the TPM TIS devices.
To maintain compatibility, we do not rename the existing tpm-crb
device.
Signed-off-by: Joelle van Dyne
---
docs/specs/tpm.rst | 1 +
hw/tpm/tpm_cr
On 2023/07/12 21:06, Michael S. Tsirkin wrote:
On Wed, Jul 12, 2023 at 08:50:32PM +0900, Akihiko Odaki wrote:
On 2023/07/12 20:46, Michael S. Tsirkin wrote:
On Wed, Jul 12, 2023 at 08:27:32PM +0900, Akihiko Odaki wrote:
Current SR/IOV implementations assume that hardcoded Function numbers
are
On 7/12/23 23:51, Joelle van Dyne wrote:
On Apple Silicon, when Windows performs a LDP on the CRB MMIO space,
the exception is not decoded by hardware and we cannot trap the MMIO
read. This led to the idea from @agraf to use the same mapping type as
ROM devices: namely that reads should be see
On Thu, 13 Jul 2023 at 15:18, Stefan Berger wrote:
>
>
>
> On 7/12/23 23:51, Joelle van Dyne wrote:
> > On Apple Silicon, when Windows performs a LDP on the CRB MMIO space,
> > the exception is not decoded by hardware and we cannot trap the MMIO
> > read. This led to the idea from @agraf to use th
On 7/13/23 10:50, Peter Maydell wrote:
On Thu, 13 Jul 2023 at 15:18, Stefan Berger wrote:
On 7/12/23 23:51, Joelle van Dyne wrote:
On Apple Silicon, when Windows performs a LDP on the CRB MMIO space,
the exception is not decoded by hardware and we cannot trap the MMIO
read. This led to t
On Thu, 13 Jul 2023 at 04:52, Joelle van Dyne wrote:
>
> TPM needs to know its own base address in order to generate its DSDT
> device entry.
>
> Signed-off-by: Joelle van Dyne
> ---
> hw/arm/virt.c | 37 +
> 1 file changed, 37 insertions(+)
>
> diff --git a/h
On Thu, 13 Jul 2023 at 16:28, Stefan Berger wrote:
>
>
>
> On 7/13/23 10:50, Peter Maydell wrote:
> > On Thu, 13 Jul 2023 at 15:18, Stefan Berger wrote:
> >>
> >>
> >>
> >> On 7/12/23 23:51, Joelle van Dyne wrote:
> >>> On Apple Silicon, when Windows performs a LDP on the CRB MMIO space,
> >>> th
On 7/12/23 23:51, Joelle van Dyne wrote:
The register is actually 64-bits but in order to make this more clear
than the specification, we define two 32-bit registers:
CTRL_RSP_LADDR and CTRL_RSP_HADDR to match the CTRL_CMD_* naming. This
deviates from the specs but is way more clear.
Previous
On 7/13/23 12:32, Peter Maydell wrote:
On Fri, 7 Jul 2023 at 11:30, Richard Henderson
wrote:
Read the left and right trees once, so that the gating
tests are meaningful. This was only a problem at -O0,
where the compiler didn't CSE the two reads.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Ric
On 7/13/23 11:34, Peter Maydell wrote:
On Thu, 13 Jul 2023 at 16:28, Stefan Berger wrote:
On 7/13/23 10:50, Peter Maydell wrote:
On Thu, 13 Jul 2023 at 15:18, Stefan Berger wrote:
On 7/12/23 23:51, Joelle van Dyne wrote:
On Apple Silicon, when Windows performs a LDP on the CRB MMIO
Good morning,
On 7/10/23 10:10, Steven Sistare wrote:
On 6/12/2023 10:59 AM, Michael Galaxy wrote:
Hi Steve,
On 6/7/23 12:37, Steven Sistare wrote:
On 6/7/2023 11:55 AM, Michael Galaxy wrote:
Another option could be to expose "-migrate-mode-disable" (instead of enable)
and just enable all 3
On Thu, 13 Jul 2023 at 16:46, Stefan Berger wrote:
> On 7/13/23 11:34, Peter Maydell wrote:
> > On Thu, 13 Jul 2023 at 16:28, Stefan Berger wrote:
> >> On 7/13/23 10:50, Peter Maydell wrote:
> >>> I'm not a super-fan of hacking around the fact that LDP
> >>> to hardware registers isn't supported
On 7/12/23 23:51, Joelle van Dyne wrote:
Instead of calling `memory_region_add_subregion` directly, we defer to
the caller to do it. This allows us to re-use the code for a SysBus
device.
Signed-off-by: Joelle van Dyne
Reviewed-by: Stefan Berger
---
hw/tpm/tpm_ppi.h| 10 +++---
On 7/12/23 23:51, Joelle van Dyne wrote:
This logic is similar to TPM TIS ISA device.
Signed-off-by: Joelle van Dyne
---
hw/i386/acpi-build.c | 23 ---
hw/tpm/tpm_crb.c | 28
2 files changed, 28 insertions(+), 23 deletions(-)
diff --g
On 13/7/23 14:08, Anton Johansson via wrote:
The self assignment is clearly useless, and @1.last_column does not have
to be set for an expression with only a single token, so remove it.
Reported-by: Peter Maydell
Signed-off-by: Anton Johansson
---
target/hexagon/idef-parser/idef-parser.y | 1
> -Original Message-
> From: Anton Johansson
> Sent: Thursday, July 13, 2023 7:09 AM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; peter.mayd...@linaro.org
> Subject: [PATCH] target/hexagon/idef-parser: Remove self-assignment
>
> WARNING: This email originated from outside of Qualcomm
On 13/7/23 14:34, Gavin Shan wrote:
Hi Peter and Marcin,
On 7/13/23 21:52, Marcin Juszkiewicz wrote:
W dniu 13.07.2023 o 13:44, Peter Maydell pisze:
I see this isn't a change in this patch, but given that
what the user specifies is not "cortex-a8-arm-cpu" but
"cortex-a8", why do we include th
On 7/12/23 23:51, Joelle van Dyne wrote:
If 'ppi' property is set, then `tpm_ppi_reset` is called on reset
which SEGFAULTs because `tpmppi->buf` is not allocated.
Signed-off-by: Joelle van Dyne
---
hw/tpm/tpm_tis_sysbus.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/tpm/tpm_
On 7/13/23 11:55, Peter Maydell wrote:
On Thu, 13 Jul 2023 at 16:46, Stefan Berger wrote:
On 7/13/23 11:34, Peter Maydell wrote:
On Thu, 13 Jul 2023 at 16:28, Stefan Berger wrote:
On 7/13/23 10:50, Peter Maydell wrote:
I'm not a super-fan of hacking around the fact that LDP
to hardware r
On Thu, 13 Jul 2023 at 17:54, Stefan Berger wrote:
>
>
>
> On 7/13/23 11:55, Peter Maydell wrote:
> > On Thu, 13 Jul 2023 at 16:46, Stefan Berger wrote:
> >> On 7/13/23 11:34, Peter Maydell wrote:
> >>> On Thu, 13 Jul 2023 at 16:28, Stefan Berger wrote:
> On 7/13/23 10:50, Peter Maydell wro
On 7/13/23 13:07, Peter Maydell wrote:
On Thu, 13 Jul 2023 at 17:54, Stefan Berger wrote:
On 7/13/23 11:55, Peter Maydell wrote:
On Thu, 13 Jul 2023 at 16:46, Stefan Berger wrote:
On 7/13/23 11:34, Peter Maydell wrote:
On Thu, 13 Jul 2023 at 16:28, Stefan Berger wrote:
On 7/13/23 10
On Thu, 13 Jul 2023 at 18:16, Stefan Berger wrote:
> I guess the first point would be to decide whether to support an i2c bus on
> the virt board and then whether we can use the aspeed bus that we know that
> the tpm_tis_i2c device model works with but we don't know how Windows may
> react to i
The ppi command line option for the TIS device on sysbus never worked
and caused an immediate segfault. Remove support for it since it also
needs support in the firmware and needs testing inside the VM.
Reproducer with the ppi=on option passed:
qemu-system-aarch64 \
-machine virt,gic-version=3
On Thu, Jul 13, 2023 at 6:07 AM Stefan Berger wrote:
>
>
>
> On 7/12/23 23:51, Joelle van Dyne wrote:
> > The impetus for this patch set is to get TPM 2.0 working on Windows 11
> > ARM64.
> > Windows' tpm.sys does not seem to work on a TPM TIS device (as verified with
> > VMWare's implementation)
On 7/10/23 16:21, Peter Maydell wrote:
Add comments to the in_* fields in the S1Translate struct
that explain what they're doing.
Signed-off-by: Peter Maydell
---
I figured some of this out when writing commit fcc0b0418fff,
and then I found I'd forgotten it all when I was trying
to fix this new
Hi Stefan,
On 7/13/23 19:19, Stefan Berger wrote:
> The ppi command line option for the TIS device on sysbus never worked
> and caused an immediate segfault. Remove support for it since it also
> needs support in the firmware and needs testing inside the VM.
>
> Reproducer with the ppi=on option p
On Thu, Jul 13, 2023 at 8:31 AM Peter Maydell wrote:
>
> On Thu, 13 Jul 2023 at 04:52, Joelle van Dyne wrote:
> >
> > TPM needs to know its own base address in order to generate its DSDT
> > device entry.
> >
> > Signed-off-by: Joelle van Dyne
> > ---
> > hw/arm/virt.c | 37
In that case, do you think we should have a check in "realize" to make
sure the backend is 2.0?
On Thu, Jul 13, 2023 at 9:08 AM Stefan Berger wrote:
>
>
>
> On 7/12/23 23:51, Joelle van Dyne wrote:
> > This logic is similar to TPM TIS ISA device.
> >
> > Signed-off-by: Joelle van Dyne
> > ---
>
On Thu, Jul 13, 2023 at 9:49 AM Stefan Berger wrote:
>
>
> The tpm-tis-device doesn't work for x86_64 but for aarch64.
>
>
> We have this here in this file:
>
> DEFINE_PROP_BOOL("ppi", TPMStateSysBus, state.ppi_enabled, false),
>
> I don't know whether ppi would work on aarch64. It needs firm
On 7/10/23 16:21, Peter Maydell wrote:
In commit XXX we rearranged the logic in S1_ptw_translate() so that
the debug-access "call get_phys_addr_*" codepath is used both when S1
is doing ptw reads from stage 2 and when it is doing ptw reads from
physical memory. However, we didn't update the calc
On 7/13/23 14:10, Joelle van Dyne wrote:
In that case, do you think we should have a check in "realize" to make
sure the backend is 2.0?
Maybe. I think at the moment it would simply not work (with existing drivers)
without terminating QEMU on it due to the misconfiguration. On libvirt level
On 7/10/23 16:21, Peter Maydell wrote:
In get_phys_addr_twostage() the code that applies the effects of
VSTCR.{SA,SW} and VTCR.{NSA,NSW} only updates result->f.attrs.secure.
Now we also have f.attrs.space for FEAT_RME, we need to keep the two
in sync.
These bits only have an effect for Secure sp
On 7/13/23 14:15, Joelle van Dyne wrote:
On Thu, Jul 13, 2023 at 9:49 AM Stefan Berger wrote:
The tpm-tis-device doesn't work for x86_64 but for aarch64.
We have this here in this file:
DEFINE_PROP_BOOL("ppi", TPMStateSysBus, state.ppi_enabled, false),
I don't know whether ppi wo
On 7/12/23 23:51, Joelle van Dyne wrote:
Since this device is gated to only build for targets with the PC
configuration, we should use the ISA bus like with TPM TIS.
Signed-off-by: Joelle van Dyne
I think this patch is good but I'd like to try it with resuming and old VM
snapshot and for
On 7/13/23 13:18, Peter Maydell wrote:
On Thu, 13 Jul 2023 at 18:16, Stefan Berger wrote:
I guess the first point would be to decide whether to support an i2c bus on the
virt board and then whether we can use the aspeed bus that we know that the
tpm_tis_i2c device model works with but we d
I got annoyed enough by various misspellings, and tried to clean up this
a bit. And got this in the result, for now:
https://gitlab.com/mjt0k/qemu/-/commit/eb5a376c7282e63d9e11eb952046b01f1a5ae7d4
Below is a diffstat plus a few actual changes as a sample.
It fixes misspellings in comments and i
On 7/13/23 13:34, Gavin Shan wrote:
Hi Peter and Marcin,
On 7/13/23 21:52, Marcin Juszkiewicz wrote:
W dniu 13.07.2023 o 13:44, Peter Maydell pisze:
I see this isn't a change in this patch, but given that
what the user specifies is not "cortex-a8-arm-cpu" but
"cortex-a8", why do we include th
Hi,
I've encountered a bug where two vcpu threads enter a device's MMIO
emulation callback at the same time. This is never supposed to happen
thanks to the Big QEMU Lock (BQL), but drain_call_rcu() and nested event
loops make it possible:
1. A device's MMIO emulation callback invokes AIO_WAIT_WHIL
On 16.06.2023 11:26, David Hildenbrand wrote:
Having large virtio-mem devices that only expose little memory to a VM
is currently a problem: we map the whole sparse memory region into the
guest using a single memslot, resulting in one gigantic memslot in KVM.
KVM allocates metadata for the whole
..
include/standard-headers/drm/drm_fourcc.h | 8 +++---
include/standard-headers/linux/ethtool.h | 2 +-
.../standard-headers/linux/virtio_console.h | 2 +-
include/standard-headers/linux/virtio_i2c.h | 2 +-
include/standard-headers/linux/virtio_net.h | 4 +--
It look
We adjust CONFIG_ATOMIC128 and CONFIG_CMPXCHG128 with
CONFIG_ATOMIC128_OPT in atomic128.h. It is difficult
to tell when those changes have been applied with the
ifdef we must use with CONFIG_CMPXCHG128. So instead
use HAVE_CMPXCHG128, which triggers -Werror-undef when
the proper header has not be
On 7/12/23 21:57, Daniel Henrique Barboza wrote:
+#define ADD_CPU_PROPERTIES_ARRAY(_dev, _array) \
+for (prop = _array; prop && prop->name; prop++) { \
+qdev_property_add_static(_dev, prop); \
+} \
do { } while(0)
Watch the \ on the last line of the macro.
Declare the iterator
Use generic routines for 32-bit carry-less multiply.
Remove our local version of pmull_d.
Signed-off-by: Richard Henderson
---
target/arm/tcg/vec_helper.c | 14 +-
1 file changed, 1 insertion(+), 13 deletions(-)
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
Use generic routines for 8-bit carry-less multiply.
Remove our local version of galois_multiply8.
Signed-off-by: Richard Henderson
---
target/s390x/tcg/vec_int_helper.c | 27 ---
1 file changed, 24 insertions(+), 3 deletions(-)
diff --git a/target/s390x/tcg/vec_int_helpe
Use generic routine for 64-bit carry-less multiply.
Signed-off-by: Richard Henderson
---
target/ppc/int_helper.c | 17 +++--
1 file changed, 3 insertions(+), 14 deletions(-)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 828f04bce7..4e1fa2fd68 100644
--- a/targ
Inspired by Ard Biesheuvel's RFC patches [1] for accelerating
carry-less multiply under emulation.
This is less polished than the AES patch set:
(1) Should I split HAVE_CLMUL_ACCEL into per-width HAVE_CLMUL{N}_ACCEL?
The "_generic" and "_accel" split is different from aes-round.h
because
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