Re: [PATCH] ppc/pnv: Add QME region for P10

On Fri, 7 Jul 2023 at 05:04, Cédric Le Goater wrote: > pnv_quad_realize realizes power9 and power10 quad objects but ... > > > } > > > > static Property pnv_quad_properties[] = { > > @@ -528,6 +581,9 @@ static void pnv_quad_power10_class_init(ObjectClass > > *oc, void *data) > > > > pq

[PATCH v2] ppc/pnv: Add QME region for P10

The Quad Management Engine (QME) manages power related settings for its quad. The xscom region is separate from the quad xscoms, therefore a new region is added. The xscoms in a QME select a given core by selecting the forth nibble. Implement dummy reads for the stop state history (SSH) and specia

Re: [PATCH] target/riscv KVM_RISCV_SET_TIMER macro is not configured correctly

On 7/7/23 00:23, yang.zhang wrote: From: "yang.zhang" Should set/get riscv all reg timer,i.e, time/compare/frequency/state. Nice catch. The reason why this went under the radar for 18 months is because kvm.c is using an external 'time' variable. Signed-off-by:Yang Zhang Resolves: http

Re: [PATCH] ppc/pnv: Log all unimp warnings with similar message

Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel On 7/5/23 23:45, Joel Stanley wrote: Add the function name so there's an indication as to where the message is coming from. Change all prints to use the offset instead of the address. Signed-off-by: Joel Stanley --- Happy to us

Re: [RESEND PATCH v3 0/4] PPC440 devices misc clean up

Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel On 7/6/23 08:16, BALATON Zoltan wrote: These are some small misc clean ups to PPC440 related device models which is all I have ready for now. v3: - rebased on ppc-next moving already reviewed patch to front v2: - Added R-b tags

Re: [PATCH v2 0/2] ppc/pnv: Set P10 core xscom region size to match hardware

Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel On 7/6/23 02:39, Nicholas Piggin wrote: Sorry about the paper bag bug in the first version of the patch - I broke powernv8 and 9. This adds a xsom_size core class field to change the P10 size without changing the others. Also a

Re: [PATCH v3] target/ppc: Machine check on invalid real address access on POWER9/10

Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel On 7/3/23 09:03, Nicholas Piggin wrote: ppc currently silently accepts invalid real address access. Catch these and turn them into machine checks on POWER9/10 machines. Signed-off-by: Nicholas Piggin --- Since v1: - Only implem

Re: [PATCH v3 0/6] target/ppc: Few cleanups in kvm_ppc.h

Phil, I queued all patches to ppc-next. I fixed up patch 3 to not move the cpu_list macro as Greg suggested. If you're strongly attached to it let me know and I'll remove it from the queue. Greg, feel free to send your R-b in patch 3 if patch 3 with this change pleases you. Daniel On 6/27/23

Re: [PATCH v2] ppc/pnv: Add QME region for P10

On 7/7/23 09:12, Joel Stanley wrote: The Quad Management Engine (QME) manages power related settings for its quad. The xscom region is separate from the quad xscoms, therefore a new region is added. The xscoms in a QME select a given core by selecting the forth nibble. Implement dummy reads for

Re: [PATCH v2 0/5] Migration deprecated parts

Doesn't apply to master, and has no Based-on: tags telling me what to apply first. Please advise :)

Re: [PULL 07/11] tests/tcg/aarch64: Add testcases for IC IVAU and dual-mapped code

Alright, thanks. Where should I go from here? Should I send in another patch that tries to debug this? /John -Original Message- From: Peter Maydell To: John Högberg Cc: phi...@linaro.org , richard.hender...@linaro.org , qemu-devel@nongnu.org Subject: Re: [PULL 07/11] tests/tcg/aarch64:

Re: [PATCH v2] ppc/pnv: Add QME region for P10

On Fri, 7 Jul 2023 at 07:30, Cédric Le Goater wrote: > > On 7/7/23 09:12, Joel Stanley wrote: > > The Quad Management Engine (QME) manages power related settings for its > > quad. The xscom region is separate from the quad xscoms, therefore a new > > region is added. The xscoms in a QME select a g

Re: Addition of qtest_irq_intercept_out_named, or modify qtest_irq_interrupt_out?

Hi Chris, On 7/7/23 00:10, Chris Laplante wrote: Hello all, I have a test case that needs to intercept a named GPIO out interrupt. qtest_irq_intercept_out doesn't support this currently. I would like to send a patch to add this functionality. Does anyone have a preference if I implement it i

Re: [PATCH 2/2] accel/tcg: Always lock pages before translation

On 7/6/23 18:05, Richard Henderson wrote: +++ b/accel/tcg/cpu-exec.c @@ -531,6 +531,10 @@ static void cpu_exec_longjmp_cleanup(CPUState *cpu) /* Non-buggy compilers preserve this; assert the correct value. */ g_assert(cpu == current_cpu); +if (tcg_ctx->gen_tb) { +tb_un

Re: [PATCH 1/2] accel/tcg: Split out cpu_exec_longjmp_cleanup

On 6/7/23 19:05, Richard Henderson wrote: Share the setjmp cleanup between cpu_exec_step_atomic and cpu_exec_setjmp. Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 43 +++ 1 file changed, 19 insertions(+), 24 deletions(-) Reviewed-by: Ph

Re: [RFC PATCH] docs/interop: define STANDALONE protocol feature for vhost-user

"Michael S. Tsirkin" writes: > On Tue, Jul 04, 2023 at 01:36:00PM +0100, Alex Bennée wrote: >> Currently QEMU has to know some details about the back-end to be able >> to setup the guest. While various parts of the setup can be delegated >> to the backend (for example config handling) this is a

Re: [PATCH v3 0/6] target/ppc: Few cleanups in kvm_ppc.h

On 7/7/23 09:24, Daniel Henrique Barboza wrote: Phil, I queued all patches to ppc-next. I fixed up patch 3 to not move the cpu_list macro as Greg suggested. If you're strongly attached to it let me know and I'll remove it from the queue. Sorry for missing that earlier, sure, no problem! Gre

Re: [PATCH 02/21] q800: add djMEMC memory controller

On 2/7/23 17:48, Mark Cave-Ayland wrote: The djMEMC controller is used to store information related to the physical memory configuration. Co-developed-by: Laurent Vivier Signed-off-by: Mark Cave-Ayland --- MAINTAINERS | 2 + hw/m68k/Kconfig | 1 + hw/m68k/q800.c

Re: [PATCH 04/21] q800: implement additional machine id bits on VIA1 port A

On 2/7/23 17:48, Mark Cave-Ayland wrote: Co-developed-by: Laurent Vivier Signed-off-by: Mark Cave-Ayland --- hw/misc/mac_via.c | 14 +- 1 file changed, 13 insertions(+), 1 deletion(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH 05/21] q800: add IOSB subsystem

On 2/7/23 17:48, Mark Cave-Ayland wrote: It is needed because it defines the BIOSConfig area. Co-developed-by: Laurent Vivier Signed-off-by: Mark Cave-Ayland --- MAINTAINERS| 2 + hw/m68k/Kconfig| 1 + hw/m68k/q800.c | 9 +++ hw/misc/Kconfig| 3

Re: [PATCH 10/21] q800: add easc bool machine class property to switch between ASC and EASC

On 2/7/23 17:48, Mark Cave-Ayland wrote: This determines whether the Apple Sound Chip (ASC) is set to enhanced mode (default) or to original mode. The real Q800 hardware used an EASC chip however a lot of older software only works with the older ASC chip. Adding this as a machine parameter allow

[PATCH v2 0/4] QGA VSS Logging

Print all VSS error and trace to debugger and stderr. Konstantin Kostiuk (4): QGA VSS: Add wrapper to send log to debugger and stderr QGA VSS: Replace 'fprintf(stderr' with PRINT_DEBUG QGA VSS: Print error in err_set QGA VSS: Add log in functions begin/end qga/vss-win32/install.cpp | 4

[PATCH v2 2/4] QGA VSS: Replace 'fprintf(stderr' with PRINT_DEBUG

Signed-off-by: Konstantin Kostiuk --- qga/vss-win32/install.cpp | 13 +++-- qga/vss-win32/requester.cpp | 9 + 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/qga/vss-win32/install.cpp b/qga/vss-win32/install.cpp index ff93b08a9e..c84c40106e 100644 --- a/qga/vs

[PATCH v2 4/4] QGA VSS: Add log in functions begin/end

Signed-off-by: Konstantin Kostiuk --- qga/vss-win32/install.cpp | 33 + qga/vss-win32/provider.cpp | 3 +++ qga/vss-win32/requester.cpp | 34 ++ 3 files changed, 70 insertions(+) diff --git a/qga/vss-win32/install.cpp b/qga/vss-

[PATCH v2 1/4] QGA VSS: Add wrapper to send log to debugger and stderr

Signed-off-by: Konstantin Kostiuk --- qga/vss-win32/meson.build | 2 +- qga/vss-win32/vss-debug.cpp | 31 +++ qga/vss-win32/vss-debug.h | 24 3 files changed, 56 insertions(+), 1 deletion(-) create mode 100644 qga/vss-win32/vss-debug.cpp

[PATCH v2 3/4] QGA VSS: Print error in err_set

Signed-off-by: Konstantin Kostiuk --- qga/vss-win32/requester.cpp | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/qga/vss-win32/requester.cpp b/qga/vss-win32/requester.cpp index e85b9bc633..f3eafacfc1 100644 --- a/qga/vss-win32/requester.cpp +++ b/qga/vss-win32/request

Re: [PATCH v2 1/4] QGA VSS: Add wrapper to send log to debugger and stderr

On 7/7/23 10:31, Konstantin Kostiuk wrote: Signed-off-by: Konstantin Kostiuk --- qga/vss-win32/meson.build | 2 +- qga/vss-win32/vss-debug.cpp | 31 +++ qga/vss-win32/vss-debug.h | 24 3 files changed, 56 insertions(+), 1 deletion(-)

Re: [PATCH v2 2/4] QGA VSS: Replace 'fprintf(stderr' with PRINT_DEBUG

On 7/7/23 10:31, Konstantin Kostiuk wrote: Signed-off-by: Konstantin Kostiuk --- qga/vss-win32/install.cpp | 13 +++-- qga/vss-win32/requester.cpp | 9 + 2 files changed, 12 insertions(+), 10 deletions(-) @@ -304,9 +305,9 @@ STDAPI COMRegister(void) } strcp

Re: [PATCH v2 3/4] QGA VSS: Print error in err_set

On 7/7/23 10:31, Konstantin Kostiuk wrote: Signed-off-by: Konstantin Kostiuk --- qga/vss-win32/requester.cpp | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH 2/2] tests/tcg/s390x: Test single-stepping SVC

On 11/05/2023 01.02, Ilya Leoshkevich wrote: Add a small test to prevent regressions. Signed-off-by: Ilya Leoshkevich --- ... diff --git a/tests/tcg/s390x/hello-s390x-asm.S b/tests/tcg/s390x/hello-s390x-asm.S new file mode 100644 index 000..2e9faa16047 --- /dev/null +++ b/tests/tcg/s

Re: [PATCH v5 3/3] ppc: Enable 2nd DAWR support on p10

Hi David, All, I am revisiting/reviving this patch. On 5/5/21 11:20, David Gibson wrote: On Wed, Apr 21, 2021 at 11:50:40AM +0530, Ravi Bangoria wrote: Hi David, On 4/19/21 10:23 AM, David Gibson wrote: On Mon, Apr 12, 2021 at 05:14:33PM +0530, Ravi Bangoria wrote: Since we have released

[PATCH v6] ppc: Enable 2nd DAWR support on p10

From: Ravi Bangoria As per the PAPR, bit 0 of byte 64 in pa-features property indicates availability of 2nd DAWR registers. i.e. If this bit is set, 2nd DAWR is present, otherwise not. Use KVM_CAP_PPC_DAWR1 capability to find whether kvm supports 2nd DAWR or not. If it's supported, allow user to

[PULL 04/15] hw/net: i82596: Remove the logic of padding short frames in the receive path

From: Bin Meng Now that we have implemented unified short frames padding in the QEMU networking codes, remove the same logic in the NIC codes. Signed-off-by: Bin Meng Signed-off-by: Jason Wang --- hw/net/i82596.c | 18 -- 1 file changed, 18 deletions(-) diff --git a/hw/net/i8

[PULL 03/15] hw/net: vmxnet3: Remove the logic of padding short frames in the receive path

From: Bin Meng Now that we have implemented unified short frames padding in the QEMU networking codes, remove the same logic in the NIC codes. This actually reverts commit 40a87c6c9b11ef9c14e0301f76abf0eb2582f08e. Signed-off-by: Bin Meng Signed-off-by: Jason Wang --- hw/net/vmxnet3.c | 10 --

[PULL 12/15] net: socket: move fd type checking to its own function

From: Laurent Vivier Reviewed-by: David Gibson Signed-off-by: Laurent Vivier Signed-off-by: Jason Wang --- net/socket.c | 28 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/net/socket.c b/net/socket.c index 24dcaa5..6b1f0fe 100644 --- a/net/socket.

[PULL 02/15] hw/net: e1000: Remove the logic of padding short frames in the receive path

From: Bin Meng Now that we have implemented unified short frames padding in the QEMU networking codes, remove the same logic in the NIC codes. This actually reverts commit 78aeb23eded2d0b765bf9145c71f80025b568acd. Signed-off-by: Bin Meng Signed-off-by: Jason Wang --- hw/net/e1000.c | 11 +---

[PULL 06/15] hw/net: pcnet: Remove the logic of padding short frames in the receive path

From: Bin Meng Now that we have implemented unified short frames padding in the QEMU networking codes, remove the same logic in the NIC codes. Signed-off-by: Bin Meng Signed-off-by: Jason Wang --- hw/net/pcnet.c | 9 - 1 file changed, 9 deletions(-) diff --git a/hw/net/pcnet.c b/hw/n

[PULL 11/15] net: socket: prepare to cleanup net_init_socket()

From: Laurent Vivier Use directly net_socket_fd_init_stream() and net_socket_fd_init_dgram() when the socket type is already known. Reviewed-by: David Gibson Signed-off-by: Laurent Vivier Signed-off-by: Jason Wang --- net/socket.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

[PULL 13/15] net: socket: remove net_init_socket()

From: Laurent Vivier Move the file descriptor type checking before doing anything with it. If it's not usable, don't close it as it could be in use by another part of QEMU, only fail and report an error. Reviewed-by: David Gibson Signed-off-by: Laurent Vivier Signed-off-by: Jason Wang --- ne

[PULL 09/15] hw/net: sunhme: Remove the logic of padding short frames in the receive path

From: Bin Meng Now that we have implemented unified short frames padding in the QEMU networking codes, remove the same logic in the NIC codes. Signed-off-by: Bin Meng Signed-off-by: Jason Wang --- hw/net/sunhme.c | 11 --- 1 file changed, 11 deletions(-) diff --git a/hw/net/sunhme.c

[PULL 07/15] hw/net: rtl8139: Remove the logic of padding short frames in the receive path

From: Bin Meng Now that we have implemented unified short frames padding in the QEMU networking codes, remove the same logic in the NIC codes. Signed-off-by: Bin Meng Signed-off-by: Jason Wang --- hw/net/rtl8139.c | 12 1 file changed, 12 deletions(-) diff --git a/hw/net/rtl8139

[PULL 14/15] e1000e: Add ICR clearing by corresponding IMS bit

From: Akihiko Odaki The datasheet does not say what happens when interrupt was asserted (ICR.INT_ASSERT=1) and auto mask is *not* active. However, section of 13.3.27 the PCIe* GbE Controllers Open Source Software Developer’s Manual, which were written for older devices, namely 631xESB/632xESB, 82

[PULL 10/15] hw/net: ftgmac100: Drop the small packet check in the receive path

From: Bin Meng Now that we have implemented unified short frames padding in the QEMU networking codes, the small packet check logic in the receive path is no longer needed. Suggested-by: Cédric Le Goater Reviewed-by: Cédric Le Goater Signed-off-by: Bin Meng Signed-off-by: Jason Wang --- hw/

[PULL 08/15] hw/net: sungem: Remove the logic of padding short frames in the receive path

From: Bin Meng Now that we have implemented unified short frames padding in the QEMU networking codes, remove the same logic in the NIC codes. Signed-off-by: Bin Meng Signed-off-by: Jason Wang --- hw/net/sungem.c | 14 -- 1 file changed, 14 deletions(-) diff --git a/hw/net/sungem

[PULL 01/15] virtio-net: correctly report maximum tx_queue_size value

From: Laurent Vivier Maximum value for tx_queue_size depends on the backend type. 1024 for vDPA/vhost-user, 256 for all the others. The value is returned by virtio_net_max_tx_queue_size() to set the parameter: n->net_conf.tx_queue_size = MIN(virtio_net_max_tx_queue_size(n),

[PULL 05/15] hw/net: ne2000: Remove the logic of padding short frames in the receive path

From: Bin Meng Now that we have implemented unified short frames padding in the QEMU networking codes, remove the same logic in the NIC codes. Signed-off-by: Bin Meng Signed-off-by: Jason Wang --- hw/net/ne2000.c | 12 1 file changed, 12 deletions(-) diff --git a/hw/net/ne2000.c

[PULL 15/15] igb: Remove obsolete workaround for Windows

From: Akihiko Odaki I confirmed it works with Windows even without this workaround. It is likely to be a mistake so remove it. Fixes: 3a977deebe ("Intrdocue igb device emulation") Signed-off-by: Akihiko Odaki Signed-off-by: Jason Wang --- hw/net/igb_core.c | 7 +-- 1 file changed, 1 inser

[PULL 00/15] Net patches

The following changes since commit 97c81ef4b8e203d9620fd46e7eb77004563e3675: Merge tag 'pull-9p-20230706' of https://github.com/cschoenebeck/qemu into staging (2023-07-06 18:19:42 +0100) are available in the git repository at: https://github.com/jasowang/qemu.git tags/net-pull-request for

[PATCH] hw/intc/loongarch_pch: fix edge triggered irq handling

For edge triggered irq, qemu_irq_pulse is used to inject irq. It will set irq with high level and low level soon to simluate pulse irq. For edge triggered irq, irq is injected and set as pending at rising level, do not clear irq at lowering level. LoongArch pch interrupt will clear irq for lowerin

[PATCH v3 0/4] QGA VSS Logging

Print all VSS error and trace to debugger and stderr. v3 -> v2: Reformat few log lines Move G_GNUC_PRINTF attribute to the declaration v2: https://patchew.org/QEMU/20230707083105.746811-1-kkost...@redhat.com/ v2 -> v1: Rename debug macro Move log code to function v1: https://patchew.org

Re: [PATCH 1/7] target/ppc: Fix CPU reservation migration for record-replay

Nick, On 6/23/23 09:57, Nicholas Piggin wrote: ppc only migrates reserve_addr, so the destination machine can get a valid reservation with an incorrect reservation value of 0. Prior to commit 392d328abe753 ("target/ppc: Ensure stcx size matches larx"), this could permit a stcx. to incorrectly su

[PATCH v3 2/4] QGA VSS: Replace 'fprintf(stderr' with PRINT_DEBUG

Signed-off-by: Konstantin Kostiuk --- qga/vss-win32/install.cpp | 12 ++-- qga/vss-win32/requester.cpp | 9 + 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/qga/vss-win32/install.cpp b/qga/vss-win32/install.cpp index ff93b08a9e..9bd2c52b70 100644 --- a/qga/vss

[PATCH v3 1/4] QGA VSS: Add wrapper to send log to debugger and stderr

Signed-off-by: Konstantin Kostiuk --- qga/vss-win32/meson.build | 2 +- qga/vss-win32/vss-debug.cpp | 31 +++ qga/vss-win32/vss-debug.h | 25 + 3 files changed, 57 insertions(+), 1 deletion(-) create mode 100644 qga/vss-win32/vss-debug.cpp

[PATCH v3 4/4] QGA VSS: Add log in functions begin/end

Signed-off-by: Konstantin Kostiuk --- qga/vss-win32/install.cpp | 33 + qga/vss-win32/provider.cpp | 3 +++ qga/vss-win32/requester.cpp | 34 ++ 3 files changed, 70 insertions(+) diff --git a/qga/vss-win32/install.cpp b/qga/vss-

[PATCH v3 3/4] QGA VSS: Print error in err_set

Signed-off-by: Konstantin Kostiuk Reviewed-by: Philippe Mathieu-Daudé --- qga/vss-win32/requester.cpp | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/qga/vss-win32/requester.cpp b/qga/vss-win32/requester.cpp index e85b9bc633..f3eafacfc1 100644 --- a/qga/vss-win32/requ

Re: [PATCH] io: remove io watch if TLS channel is closed during handshake

On Wed, Jul 5, 2023 at 10:20 PM Daniel P. Berrangé wrote: > The TLS handshake make take some time to complete, during which time an > I/O watch might be registered with the main loop. If the owner of the > I/O channel invokes qio_channel_close() while the handshake is waiting > to continue the I/

Re: [PATCH] io: remove io watch if TLS channel is closed during handshake

On Fri, Jul 07, 2023 at 01:30:16PM +0400, Marc-André Lureau wrote: > On Wed, Jul 5, 2023 at 10:20 PM Daniel P. Berrangé > wrote: > > > The TLS handshake make take some time to complete, during which time an > > I/O watch might be registered with the main loop. If the owner of the > > I/O channel

Re: [RFC PATCH] docs/interop: define STANDALONE protocol feature for vhost-user

On Fri, Jul 07, 2023 at 08:58:00AM +0100, Alex Bennée wrote: > > "Michael S. Tsirkin" writes: > > > On Tue, Jul 04, 2023 at 01:36:00PM +0100, Alex Bennée wrote: > >> Currently QEMU has to know some details about the back-end to be able > >> to setup the guest. While various parts of the setup ca

[PATCH qemu v3 1/1] fdt_load_addr is getting assigned as the result of riscv_compute_fdt_addr(), which is an uint64_t.

From: Lakshmi Bai Raja Subramanian fdt_load_addr is declared as uint32_t which is not matching with the return data type of riscv_compute_fdt_addr. Modified fdt_load_addr data type to uint64_t to match the riscv_compute_fdt_addr() return data type. This fix also helps in calculating the right fd

[PATCH qemu v3 0/1] [Ping] [PATCH qemu v3] fdt_load_addr is getting assigned as the result of riscv_compute_fdt_addr(), which is an uint64_t.

Ping for the patch https://patchew.org/QEMU/168753067876.24231.1158476330586280652...@git.sr.ht/ Lakshmi Bai Raja Subramanian (1): fdt_load_addr is getting assigned as the result of riscv_compute_fdt_addr(), which is an uint64_t. hw/riscv/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 de

[PATCH] vhost_vdpa: no need to fetch vring base when poweroff

In the poweroff routine, no need to fetch last available index. This commit also provides a better debug message in the vhost caller vhost_virtqueue_stop, because if vhost does not fetch the last avail idx successfully, maybe the device does not suspend, vhost will sync last avail idx to vring use

Re: [virtio-dev] [RFC PATCH] docs/interop: define STANDALONE protocol feature for vhost-user

On Tue, Jul 04, 2023 at 04:02:42PM +0100, Alex Bennée wrote: Stefano Garzarella writes: On Tue, Jul 04, 2023 at 01:36:00PM +0100, Alex Bennée wrote: Currently QEMU has to know some details about the back-end to be able to setup the guest. While various parts of the setup can be delegated to

[PATCH] tcg: Fix info_in_idx increment in layout_arg_by_ref

Off by one error, failing to take into account that layout_arg_1 already incremeneted info_in_idx for the first piece. We only need care for the n-1 TCG_CALL_ARG_BY_REF_N pieces here. Cc: qemu-sta...@nongnu.org Fixes: 313bdea84d2 ("tcg: Add TCG_CALL_{RET,ARG}_BY_REF") Resolves: https://gitlab.com

[PATCH] util/interval-tree: Avoid race conditions without optimization

Read the left and right trees once, so that the gating tests are meaningful. This was only a problem at -O0, where the compiler didn't CSE the two reads. Cc: qemu-sta...@nongnu.org Signed-off-by: Richard Henderson --- util/interval-tree.c | 13 + 1 file changed, 9 insertions(+), 4 d

Re: [PATCH v3 1/4] QGA VSS: Add wrapper to send log to debugger and stderr

On 7/7/23 11:22, Konstantin Kostiuk wrote: Signed-off-by: Konstantin Kostiuk --- qga/vss-win32/meson.build | 2 +- qga/vss-win32/vss-debug.cpp | 31 +++ qga/vss-win32/vss-debug.h | 25 + 3 files changed, 57 insertions(+), 1 deletion(-

Re: [PATCH v3 2/4] QGA VSS: Replace 'fprintf(stderr' with PRINT_DEBUG

On 7/7/23 11:22, Konstantin Kostiuk wrote: Signed-off-by: Konstantin Kostiuk --- qga/vss-win32/install.cpp | 12 ++-- qga/vss-win32/requester.cpp | 9 + 2 files changed, 11 insertions(+), 10 deletions(-) @@ -304,9 +305,8 @@ STDAPI COMRegister(void) } strcpy

[PATCH v2 2/2] accel/tcg: Always lock pages before translation

We had done this for user-mode by invoking page_protect within the translator loop. Extend this to handle system mode as well. Move page locking out of tb_link_page. Reported-by: Liren Wei Reported-by: Richard W.M. Jones Signed-off-by: Richard Henderson Tested-by: Richard W.M. Jones --- acc

[PATCH v2 0/2] accel/tcg: Fix race condition in tb create/invalidate

Changes for v2: Adjust the change to cpu_exec_longjmp_cleanup, which should now survive user-only testing. I'm not really happy with it. I suggested two alternatives in the block comment, but neither of them are trivial. Please re-review, if you gave it a glance before. And if you have any bri

[PATCH v2 1/2] accel/tcg: Split out cpu_exec_longjmp_cleanup

Share the setjmp cleanup between cpu_exec_step_atomic and cpu_exec_setjmp. Reviewed-by: Richard W.M. Jones Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 43 +++ 1 file changed, 19 insertions(+), 24 deletions(-) diff --git a/accel/tcg/cpu-ex

Re: [RFC PATCH] docs/interop: define STANDALONE protocol feature for vhost-user

On Thu, Jul 06, 2023 at 05:31:15PM +0100, Alex Bennée wrote: Alex Bennée writes: Currently QEMU has to know some details about the back-end to be able to setup the guest. While various parts of the setup can be delegated to the backend (for example config handling) this is a very piecemeal ap

Re: [PATCH 1/2] accel/tcg: Split out cpu_exec_longjmp_cleanup

On 7/7/23 09:09, Philippe Mathieu-Daudé wrote: On 6/7/23 19:05, Richard Henderson wrote: Share the setjmp cleanup between cpu_exec_step_atomic and cpu_exec_setjmp. Signed-off-by: Richard Henderson ---   accel/tcg/cpu-exec.c | 43 +++   1 file changed, 19

Re: [PATCH v2 0/6] Add new CPU model GraniteRapids

Queued, thanks. Paolo

Re: [PATCH] vhost_vdpa: no need to fetch vring base when poweroff

On Fri, Jul 7, 2023 at 12:18 PM Zhu Lingshan wrote: > > In the poweroff routine, no need to fetch last available index. > > This commit also provides a better debug message in the vhost > caller vhost_virtqueue_stop, because if vhost does not fetch > the last avail idx successfully, maybe the devi

Re: [PATCH v2 16/46] target/loongarch: Implement xvmadd/xvmsub/xvmaddw{ev/od}

On 6/30/23 08:58, Song Gao wrote: +#define XVMADD_Q(NAME, FN, idx1, idx2)\ +static bool trans_## NAME(DisasContext *ctx, arg_vvv * a) \ +{ \ +TCGv_i64 rh, rl, arg1, arg2, th, tl; \ +int i;

Re: [PATCH v2 17/46] target/loongarch; Implement xvdiv/xvmod

On 6/30/23 08:58, Song Gao wrote: +len = (oprsz == 16) ? LSX_LEN : LASX_LEN; \ +for (i = 0; i < len / BIT; i++) { \ Similarly. r~

Re: [PATCH v2] ppc/pnv: Add QME region for P10

Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel On 7/7/23 04:12, Joel Stanley wrote: The Quad Management Engine (QME) manages power related settings for its quad. The xscom region is separate from the quad xscoms, therefore a new region is added. The xscoms in a QME select a g

Re: [PATCH v6] ppc: Enable 2nd DAWR support on p10

This one was a buzzer shot. Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel On 7/7/23 05:47, Shivaprasad G Bhat wrote: From: Ravi Bangoria As per the PAPR, bit 0 of byte 64 in pa-features property indicates availability of 2nd DAWR registers. i.e. If this bit is set, 2nd

Re: [PATCH v2 18/46] target/loongarch: Implement xvsat

On 6/30/23 08:58, Song Gao wrote: +len = (simd_oprsz(v) == 16) ? LSX_LEN : LASX_LEN; \ +for (i = 0; i < len / BIT; i++) { \ Similarly. r~

Re: [PATCH] net: add initial support for AF_XDP network backend

On 7/7/23 03:43, Jason Wang wrote: > On Fri, Jul 7, 2023 at 3:08 AM Stefan Hajnoczi wrote: >> >> On Wed, 5 Jul 2023 at 02:02, Jason Wang wrote: >>> >>> On Mon, Jul 3, 2023 at 5:03 PM Stefan Hajnoczi wrote: On Fri, 30 Jun 2023 at 09:41, Jason Wang wrote: > > On Thu, Jun 29, 202

[PULL 16/60] target/ppd: Remove unused define

From: BALATON Zoltan Commit 7a3fe174b12d removed usage of POWERPC_SYSCALL_VECTORED, drop the unused define as well. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Nicholas Piggin Message-ID: <50adc24f9d408882128e896d8a81a1a059c41836.1686868895.git.bala...@eik.

[PULL 29/60] pnv/xive: Print CPU target in all TIMA traces

From: Frederic Barrat Add the CPU target in the trace when reading/writing the TIMA space. It was already done for other TIMA ops (notify, accept, ...), only missing for those 2. Useful for debug and even more now that we experiment with SMT. Signed-off-by: Frederic Barrat Reviewed-by: Cédric L

[PULL 05/60] mv64361: Add dummy gigabit ethernet PHY access registers

From: BALATON Zoltan We don't emulate the gigabit ethernet part of the chip but the MorphOS driver accesses these and expects to get some valid looking result otherwise it hangs. Add some minimal dummy implementation to avoid rhis. Signed-off-by: BALATON Zoltan Acked-by: Cédric Le Goater Messa

[PULL 33/60] ppc/pnv: SMT support for powernv

From: Nicholas Piggin Set the TIR default value with the SMT thread index, and place some standard limits on SMT configurations. Now powernv is able to boot skiboot and Linux with a SMT topology, including booting a KVM guest. There are several SPRs and other features (e.g., broadcast msgsnd) th

[PULL 04/60] target/ppc: Only generate decodetree files when TCG is enabled

From: Philippe Mathieu-Daudé No need to generate TCG-specific decodetree files when TCG is disabled. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Greg Kurz Reviewed-by: Richard Henderson Message-ID: <20230626140100.67941-1-phi...@linaro.org> Signed-off-by: Daniel Henrique Barboza ---

[PULL 15/60] target/ppc: Remove some more local CPUState variables only used once

From: BALATON Zoltan Some helpers only have a CPUState local to call cpu_interrupt_exittb() but we can use env_cpu for that and remove the local. Signed-off-by: BALATON Zoltan Acked-by: Nicholas Piggin Message-ID: Signed-off-by: Daniel Henrique Barboza --- target/ppc/excp_helper.c | 7 ++--

[PULL 35/60] ppc440: Change ppc460ex_pcie_init() parameter type

From: BALATON Zoltan Change parameter of ppc460ex_pcie_init() from env to cpu to allow further refactoring. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Message-ID: <1695d7cc1a9f1070ab498c078916e2389d6e9469.1688586835.git.bala...@eik.bme.hu> Signed-off-by: Daniel Henrique

[PULL 32/60] target/ppc: SMT support for the HID SPR

From: Nicholas Piggin HID is a per-core shared register, skiboot sets this (e.g., setting HILE) on one thread and that must affect all threads of the core. Reviewed-by: Cédric Le Goater Tested-by: Cédric Le Goater Signed-off-by: Nicholas Piggin Message-ID: <20230705120631.27670-3-npig...@gmai

[PULL 17/60] target/ppc: Get CPUState in one step

From: BALATON Zoltan We can get CPUState from env with env_cpu without going through PowerPCCPU and casting that. Signed-off-by: BALATON Zoltan Acked-by: Nicholas Piggin Message-ID: <28424220f37f51ce97f24cadc7538a9c0d16cb45.1686868895.git.bala...@eik.bme.hu> Signed-off-by: Daniel Henrique Bar

[PULL 42/60] ppc440: Remove ppc460ex_pcie_init legacy init function

From: BALATON Zoltan After previous changes we can now remove the legacy init function and move the device creation to board code. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Message-ID: <29aafeea9f1c871c739600a7b093c5456e8a1dc8.1688586835.git.bala...@eik.bme.hu> Signed-

[PULL 28/60] ppc/pegasos2: Add support for -initrd command line option

From: BALATON Zoltan This also changes type of sz local variable to ssize_t because it is used to store return value of load_elf() and load_image_targphys() that return ssize_t. Signed-off-by: BALATON Zoltan Reviewed-by: Daniel Henrique Barboza Message-ID: <20230704181920.27b58746...@zero.eik.

[PULL 48/60] ppc440_pcix: Rename QOM type define abd move it to common header

From: BALATON Zoltan Rename TYPE_PPC440_PCIX_HOST_BRIDGE to better match its string value, move it to common header and use it also in sam460ex to replace hard coded type name. Signed-off-by: BALATON Zoltan Reviewed-by: Daniel Henrique Barboza Message-ID: <1a1c3fe4b120f345d1005ad7ceca45007836

[PULL 10/60] tests/avocado: record_replay test for ppc powernv machine

From: Nicholas Piggin The powernv machine can boot Linux to VFS mount with icount enabled. Add a test case for it. Signed-off-by: Nicholas Piggin Reviewed-by: Cédric Le Goater Message-ID: <20230625103700.8992-2-npig...@gmail.com> Signed-off-by: Daniel Henrique Barboza --- tests/avocado/repla

[PULL 60/60] ppc: Enable 2nd DAWR support on p10

From: Ravi Bangoria As per the PAPR, bit 0 of byte 64 in pa-features property indicates availability of 2nd DAWR registers. i.e. If this bit is set, 2nd DAWR is present, otherwise not. Use KVM_CAP_PPC_DAWR1 capability to find whether kvm supports 2nd DAWR or not. If it's supported, allow user to

[PULL 06/60] target/ppc: Tidy POWER book4 SPR registration

From: Nicholas Piggin POWER book4 (implementation-specific) SPRs are sometimes in their own functions, but in other cases are mixed with architected SPRs. Do some spring cleaning on these. Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin Message-ID: <20230625120317.13877-2-npig...@

[PULL 44/60] ppc440_pcix: Don't use iomem for regs

From: BALATON Zoltan The iomem memory region is better used for the PCI IO space but currently used for registers. Stop using it for that to allow this to be cleaned up in the next patch. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Message-ID: <3def68f200edd4540393d6b3b0

[PULL 54/60] target/ppc: Reorder #ifdef'ry in kvm_ppc.h

From: Philippe Mathieu-Daudé Keep a single if/else/endif block checking CONFIG_KVM. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Message-ID: <20230627115124.19632-3-phi...@linaro.org> Signed-off-by: Daniel Henrique Barboza --- target/ppc/kvm_ppc.h | 62

Re: [PATCH 0/6] qemu-img: rebase: add compression support

On 6/30/23 13:54, Denis V. Lunev wrote: > On 6/1/23 21:28, Andrey Drobyshev wrote: >> This series is adding [-c | --compress] option to "qemu-img rebase" >> command, which might prove useful for saving some disk space when, for >> instance, manipulating chains of backup images.  Along the way I had

[PULL 57/60] target/ppc: Restrict 'kvm_ppc.h' to sysemu in cpu_init.c

From: Philippe Mathieu-Daudé User emulation shouldn't need any of the KVM prototypes declared in "kvm_ppc.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Reviewed-by: Greg Kurz Message-ID: <20230627115124.19632-6-phi...@linaro.org> Signed-off-by: Daniel Henrique Barboz

[PULL 53/60] target/ppc: Have 'kvm_ppc.h' include 'sysemu/kvm.h'

From: Philippe Mathieu-Daudé "kvm_ppc.h" declares: int kvm_handle_nmi(PowerPCCPU *cpu, struct kvm_run *run); 'struct kvm_run' is declared in "sysemu/kvm.h", include it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Greg Kurz Reviewed-by: Cédric Le Goater Message-ID: <20230627115124.1

[PULL 34/60] tests/avocado: Add powernv machine test script

From: Nicholas Piggin This copies ppc_pseries.py to start a set of powernv tests, including a Linux boot test for the newly added SMT mode. Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin Message-ID: <20230705120631.27670-5-npig...@gmail.com> Signed-off-by: Daniel Henrique Barboza

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