Test that we can successfully parse the docs/config/q35-emulated.cfg,
docs/config/q35-virtio-graphical.cfg and docs/config/q35-virtio-serial.cfg
config files (the "...-serial.cfg" file is a subset of the graphical
config file, so we skip that in quick mode).
These config files use two hard-coded i
With some tweaking (e.g. by creating temporary image files), we
can check whether the docs/config/q35-*.cfg files can be loaded
by QEMU successfully, so we can avoid that these files bitrot
and avoid that our config file parser gets regressions.
Thomas Huth (3):
tests/qtest/readconfig-test: Allo
These two functions can be useful for other qtests beside the
qos-test, too, so move them to libqtest instead.
Signed-off-by: Thomas Huth
---
tests/qtest/libqos/libqos.h | 2 --
tests/qtest/libqtest.h | 20 ++
tests/qtest/libqos/libqos.c | 49 +-
Make test_x86_memdev_resp() more flexible by allowing arbitrary
memory sizes as parameter here.
Signed-off-by: Thomas Huth
---
tests/qtest/readconfig-test.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/tests/qtest/readconfig-test.c b/tests/qtest/readconfig-test.c
i
With TPM CRM device, vhost-vdpa reports an error when it tries
to register a listener for a non aligned memory region:
qemu-system-x86_64: vhost_vdpa_listener_region_add received unaligned region
qemu-system-x86_64: vhost_vdpa_listener_region_del received unaligned region
This error can be co
An error is reported for vhost-vdpa case:
qemu-kvm: vhost_vdpa_listener_region_add received unaligned region
Marc-André has proposed a fix to this problem by skipping
the memory region owned by the TPM CRB but it seems more generic
to skip not aligned memory.
v1 of this series proposed to set the
On 04.07.23 09:19, Laurent Vivier wrote:
With TPM CRM device, vhost-vdpa reports an error when it tries
to register a listener for a non aligned memory region:
qemu-system-x86_64: vhost_vdpa_listener_region_add received unaligned region
qemu-system-x86_64: vhost_vdpa_listener_region_del re
On 03.07.23 17:50, Ilya Leoshkevich wrote:
Make the PSW look more similar to the real s390x userspace PSW.
Except for being there, the newly added bits should not affect the
userspace code execution.
What's the purpose of this then? Required for follow-up patches?
Signed-off-by: Ilya Leoshke
On 03.07.23 17:50, Ilya Leoshkevich wrote:
EPSW should explicitly calculate and insert CC, like IPM does.
Fixes: e30a9d3fea58 ("target-s390: Implement EPSW")
Cc: qemu-sta...@nongnu.org
Signed-off-by: Ilya Leoshkevich
---
Reviewed-by: David Hildenbrand
--
Cheers,
David / dhildenb
On 03.07.23 17:50, Ilya Leoshkevich wrote:
These instructions multiply 32 bits by 32 bits, not 32 bits by 64 bits.
Fixes: 83b00736f3d8 ("target-s390: Convert FP MULTIPLY")
Cc: qemu-sta...@nongnu.org
Signed-off-by: Ilya Leoshkevich
---
Reviewed-by: David Hildenbrand
--
Cheers,
David / dhild
On Tue, 2023-07-04 at 09:32 +0200, David Hildenbrand wrote:
> On 03.07.23 17:50, Ilya Leoshkevich wrote:
> > Make the PSW look more similar to the real s390x userspace PSW.
> > Except for being there, the newly added bits should not affect the
> > userspace code execution.
>
> What's the purpose o
On 03.07.23 17:50, Ilya Leoshkevich wrote:
Using a large R0 causes an assertion error:
qemu-s390x: target/s390x/tcg/mem_helper.c:183: access_prepare_nf: Assertion `size > 0
&& size <= 4096' failed.
Even though PoP explicitly advises against using more than 8 bits for the
size, an emulator
On 03.07.23 17:50, Ilya Leoshkevich wrote:
When a DAT error occurs, LRA is supposed to write the error information
to the bottom 32 bits of R1, and leave the top 32 bits of R1 alone.
Fix by passing the original value of R1 into helper and copying the
top 32 bits to the return value.
Fixes: d8fe
On 04.07.23 09:40, Ilya Leoshkevich wrote:
On Tue, 2023-07-04 at 09:32 +0200, David Hildenbrand wrote:
On 03.07.23 17:50, Ilya Leoshkevich wrote:
Make the PSW look more similar to the real s390x userspace PSW.
Except for being there, the newly added bits should not affect the
userspace code exe
Thanks for fixing this Narayana,
Narayana Murty N writes:
> Currently on PPC64 qemu always dumps the guest memory in
> Big Endian (BE) format even though the guest running in Little Endian
> (LE) mode. So crash tool fails to load the dump as illustrated below:
>
> Log :
> $ virsh dump DOMAIN -
On 7/4/23 09:25, David Hildenbrand wrote:
On 04.07.23 09:19, Laurent Vivier wrote:
With TPM CRM device, vhost-vdpa reports an error when it tries
to register a listener for a non aligned memory region:
qemu-system-x86_64: vhost_vdpa_listener_region_add received unaligned region
qemu-syste
On 03.07.23 17:50, Ilya Leoshkevich wrote:
LRA should perform DAT regardless of whether it's on or off.
Disable DAT check for MMU_S390_LRA.
Fixes: defb0e3157af ("s390x: Implement opcode helpers")
Cc: qemu-sta...@nongnu.org
Signed-off-by: Ilya Leoshkevich
---
target/s390x/mmu_helper.c | 2 +-
On 03.07.23 17:50, Ilya Leoshkevich wrote:
The expression "imm * 2" in gen_ri2() can wrap around if imm is large
enough.
Fix by casting imm to int64_t, like it's done in disas_jdest().
Fixes: e8ecdfeb30f0 ("Fix EXECUTE of relative branches")
Signed-off-by: Ilya Leoshkevich
---
target/s390x/t
On 03.07.23 17:50, Ilya Leoshkevich wrote:
Add a small test to prevent regressions.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.target | 1 +
tests/tcg/s390x/epsw.c | 23 +++
2 files changed, 24 insertions(+)
create mode 100644 tests/tcg/s390
On 03.07.23 17:50, Ilya Leoshkevich wrote:
Add a small test to prevent regressions.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.target | 1 +
tests/tcg/s390x/larl.c | 17 +
2 files changed, 18 insertions(+)
create mode 100644 tests/tcg/s390x/larl
On 03.07.23 17:50, Ilya Leoshkevich wrote:
Add a small test to prevent regressions.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.target | 1 +
tests/tcg/s390x/mdeb.c | 30 ++
2 files changed, 31 insertions(+)
create mode 100644 tests/t
On Tue, 2023-07-04 at 09:56 +0200, David Hildenbrand wrote:
> On 03.07.23 17:50, Ilya Leoshkevich wrote:
> > Add a small test to prevent regressions.
> >
> > Signed-off-by: Ilya Leoshkevich
> > ---
> > tests/tcg/s390x/Makefile.target | 1 +
> > tests/tcg/s390x/larl.c | 17 +++
On 03.07.23 17:50, Ilya Leoshkevich wrote:
Add a small test to prevent regressions.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/mie3-mvcrl.c | 46
1 file changed, 36 insertions(+), 10 deletions(-)
diff --git a/tests/tcg/s390x/mie3-mvcrl.c b/tests
On Tue, 2023-07-04 at 09:47 +0200, David Hildenbrand wrote:
> On 03.07.23 17:50, Ilya Leoshkevich wrote:
> > When a DAT error occurs, LRA is supposed to write the error
> > information
> > to the bottom 32 bits of R1, and leave the top 32 bits of R1 alone.
> >
> > Fix by passing the original value
On 7/4/23 10:05, Ilya Leoshkevich wrote:
+ ret = (r1 & 0x) | exc | 0x8000;
ull missing for large constant?
Will do.
Just for my understanding, why is this necessary?
32-bit host; you'll get a warning for the large constant.
r~
It is not uncommon for device models to request mapping of several DMA
regions at the same time. An example is igb (and probably other net
devices as well) when a packet is spread across multiple descriptors.
In order to support this when indirect DMA is used, as is the case when
running the devic
Wire up support for DMA for the case where the vfio-user client does not
provide mmap()-able file descriptors, but DMA requests must be performed
via the VFIO-user protocol. This installs an indirect memory region,
which already works for pci_dma_{read,write}, and pci_dma_map works
thanks to the ex
This series adds basic support for message-based DMA in qemu's vfio-user
server. This is useful for cases where the client does not provide file
descriptors for accessing system memory via memory mappings. My motivating use
case is to hook up device models as PCIe endpoints to a hardware design. Th
According to old commit messages, this was introduced to retry a DMA
operation at a later point in case the single bounce buffer is found to
be busy. This was never used widely - only the dma-helpers code made use
of it, but there are other device models that use multiple DMA mappings
(concurrently
} else {
cc = 0;
ret |= addr & ~TARGET_PAGE_MASK;
diff --git a/target/s390x/tcg/translate.c
b/target/s390x/tcg/translate.c
index 0cef6efbef4..a6079ab7b4f 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -2932,7 +2932,7 @@ static DisasJu
v1: https://lists.gnu.org/archive/html/qemu-devel/2023-07/msg00454.html
v1 -> v2: Add ULL for a large constant (David).
Add a comment explaining the usage of ALGFI in the LARL test.
Hi,
Randomized testing found a number of issues in the s390x emulation.
This series fixes 6 of them (patc
These instructions multiply 32 bits by 32 bits, not 32 bits by 64 bits.
Fixes: 83b00736f3d8 ("target-s390: Convert FP MULTIPLY")
Cc: qemu-sta...@nongnu.org
Reviewed-by: David Hildenbrand
Signed-off-by: Ilya Leoshkevich
---
target/s390x/tcg/fpu_helper.c| 3 ++-
target/s390x/tcg/insn-data.h.i
Add a small test to prevent regressions.
Acked-by: David Hildenbrand
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.target | 1 +
tests/tcg/s390x/larl.c | 21 +
2 files changed, 22 insertions(+)
create mode 100644 tests/tcg/s390x/larl.c
diff --git a
The expression "imm * 2" in gen_ri2() can wrap around if imm is large
enough.
Fix by casting imm to int64_t, like it's done in disas_jdest().
Fixes: e8ecdfeb30f0 ("Fix EXECUTE of relative branches")
Reviewed-by: David Hildenbrand
Signed-off-by: Ilya Leoshkevich
---
target/s390x/tcg/translate.c
Make the PSW look more similar to the real s390x userspace PSW.
Except for being there, the newly added bits should not affect the
userspace code execution.
Reviewed-by: David Hildenbrand
Signed-off-by: Ilya Leoshkevich
---
linux-user/elfload.c | 4 +++-
1 file changed, 3 insertions(+), 1 delet
On 04.07.23 10:12, Ilya Leoshkevich wrote:
When a DAT error occurs, LRA is supposed to write the error information
to the bottom 32 bits of R1, and leave the top 32 bits of R1 alone.
Fix by passing the original value of R1 into helper and copying the
top 32 bits to the return value.
Fixes: d8fe
Add a small test to prevent regressions.
Acked-by: David Hildenbrand
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.target | 1 +
tests/tcg/s390x/mdeb.c | 30 ++
2 files changed, 31 insertions(+)
create mode 100644 tests/tcg/s390x/mdeb.c
dif
Add a small test to prevent regressions.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.softmmu-target | 1 +
tests/tcg/s390x/lra.S | 19 +++
2 files changed, 20 insertions(+)
create mode 100644 tests/tcg/s390x/lra.S
diff --git a/tests/tcg/s390x
EPSW should explicitly calculate and insert CC, like IPM does.
Fixes: e30a9d3fea58 ("target-s390: Implement EPSW")
Cc: qemu-sta...@nongnu.org
Reviewed-by: David Hildenbrand
Signed-off-by: Ilya Leoshkevich
---
target/s390x/tcg/translate.c | 4
1 file changed, 4 insertions(+)
diff --git a/t
When a DAT error occurs, LRA is supposed to write the error information
to the bottom 32 bits of R1, and leave the top 32 bits of R1 alone.
Fix by passing the original value of R1 into helper and copying the
top 32 bits to the return value.
Fixes: d8fe4a9c284f ("target-s390: Convert LRA")
Cc: qem
LRA should perform DAT regardless of whether it's on or off.
Disable DAT check for MMU_S390_LRA.
Fixes: defb0e3157af ("s390x: Implement opcode helpers")
Cc: qemu-sta...@nongnu.org
Reviewed-by: David Hildenbrand
Signed-off-by: Ilya Leoshkevich
---
target/s390x/mmu_helper.c | 2 +-
1 file changed
Add a small test to prevent regressions.
Reviewed-by: David Hildenbrand
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/mie3-mvcrl.c | 46
1 file changed, 36 insertions(+), 10 deletions(-)
diff --git a/tests/tcg/s390x/mie3-mvcrl.c b/tests/tcg/s390x/mie3
Add a small test to prevent regressions.
Reviewed-by: David Hildenbrand
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.target | 1 +
tests/tcg/s390x/epsw.c | 23 +++
2 files changed, 24 insertions(+)
create mode 100644 tests/tcg/s390x/epsw.c
diff --
On 7/3/23 15:43, Alex Bennée wrote:
The following changes since commit d145c0da22cde391d8c6672d33146ce306e8bf75:
Merge tag 'pull-tcg-20230701' ofhttps://gitlab.com/rth7680/qemu into
staging (2023-07-01 08:55:37 +0200)
are available in the Git repository at:
https://gitlab.com/stsquad/q
On 04.07.23 10:06, Mattias Nissler wrote:
This series adds basic support for message-based DMA in qemu's vfio-user
server. This is useful for cases where the client does not provide file
descriptors for accessing system memory via memory mappings. My motivating use
case is to hook up device model
Using a large R0 causes an assertion error:
qemu-s390x: target/s390x/tcg/mem_helper.c:183: access_prepare_nf: Assertion
`size > 0 && size <= 4096' failed.
Even though PoP explicitly advises against using more than 8 bits for the
size, an emulator crash is never a good thing.
Fix by truncati
RVA23 Profiles states:
The RVA23 profiles are intended to be used for 64-bit application
processors that will run rich OS stacks from standard binary OS
distributions and with a substantial number of third-party binary user
applications that will be supported over a considerable length of time
in t
A wrong exit condition may lead to an infinite loop when inflating a
valid zlib buffer containing some extra bytes in the `inflate_buffer`
function. The bug only occurs post-authentication. Return the buffer
immediately if the end of the compressed data has been reached
(Z_STREAM_END).
Fixes: CVE-
On 6/30/23 16:16, Richard Henderson wrote:
On 6/30/23 14:25, Anton Johansson wrote:
@@ -448,6 +448,13 @@ struct CPUState {
/* track IOMMUs whose translations we've cached in the TCG
TLB */
GArray *iommu_notifiers;
+
+ /*
+ * The following fields needs to be within
CPU_M
On 4/7/23 00:02, BALATON Zoltan wrote:
The PCIe controller model uses PPC DCRs but cannot be modeled with
TYPE_PPC4xx_DCR_DEVICE as it derives from TYPE_PCIE_HOST_BRIDGE. Add a
cpu link property to it similar to other DCR devices to allow
registering DCRs from the device model.
Signed-off-by: BA
On 4/7/23 00:02, BALATON Zoltan wrote:
Change parameter of ppc460ex_pcie_init() from env to cpu to allow
further refactoring.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440.h| 2 +-
hw/ppc/ppc440_uc.c | 7 ---
hw/ppc/sam460ex.c | 2 +-
3 files changed, 6 insertions(+), 5 deletion
On 6/30/23 16:19, Richard Henderson wrote:
On 6/30/23 14:25, Anton Johansson wrote:
For reasons related to code-generation quality, the offset of
CPUTLBDescFast and IcountDecr from CPUArchState needs to fit within
11 bits of displacement (arm[32|64] and riscv addressing modes).
This commit in
On 4/7/23 00:02, BALATON Zoltan wrote:
It is more readable to wrap the complex call to ppc_dcr_register in a
macro when needed repeatedly.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 76 +-
1 file changed, 28 insertions(+), 48 deletions(
On 4/7/23 00:02, BALATON Zoltan wrote:
Rename local variable storing state struct in dcr_read_pcie() for
brevity and consistency with other functions.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 50 +++---
1 file changed, 25 insertions(+), 2
On 4/7/23 00:02, BALATON Zoltan wrote:
Add separate memory regions for the mem and io spaces of the PCIe bus
to avoid different buses using the same system io region.
"Reduce the I/O space to 64K."
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 9 ++---
1 file changed, 6 inser
On 4/7/23 00:02, BALATON Zoltan wrote:
Instead of guessing controller number from dcrn_base add a property so
the device does not need knowledge about where it is used.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 25 +++--
1 file changed, 11 insertions(+), 14 d
On 4/7/23 00:02, BALATON Zoltan wrote:
After previous changes we can now remove the legacy init function and
move the device creation to board code.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440.h | 1 -
hw/ppc/ppc440_uc.c | 21 -
hw/ppc/sam460ex.c
On 7/1/23 11:21, Paolo Bonzini wrote:
On 6/30/23 14:25, Anton Johansson via wrote:
CPUNegativeOffsetState is a struct placed immediately before
CPUArchState in the ArchCPU struct. Its purpose is to ensure that
certain fields (CPUTLBDescFast, IcountDecr) lay within a small negative
offset of C
On 4/7/23 00:02, BALATON Zoltan wrote:
Rename the TYPE_PPC4xx_PCI_HOST_BRIDGE define and its string value to
match each other and other similar types and to avoid confusion with
"ppc4xx-host-bridge" type defined in same file.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_bamboo.c | 3 +--
On 4/7/23 00:02, BALATON Zoltan wrote:
Add a QOM type name define for ppc4xx-host-bridge in the common header
and replace direct use of the string name with the constant.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_pcix.c| 3 ++-
hw/ppc/ppc4xx_pci.c | 4 ++--
include/hw/ppc/ppc4
On 4/7/23 00:02, BALATON Zoltan wrote:
Rename TYPE_PPC440_PCIX_HOST_BRIDGE to better match its string value,
move it to common header and use it also in sam460ex to replace hard
coded type name.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_pcix.c| 9 -
hw/ppc/sam460ex.c
On 4/7/23 00:02, BALATON Zoltan wrote:
The iomem memory region is better used for the PCI IO space but
currently used for registers. Stop using it for that to allow this to
be cleaned up in the next patch.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_pcix.c | 7 ---
1 file changed, 4
On 4/7/23 00:02, BALATON Zoltan wrote:
Use the iomem region for the PCI io space and map it directly from the
board without an intermediate alias that is not really needed.
"Reduce the I/O region to 64K."
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_pcix.c | 8 +---
hw/ppc/sam460ex
On Tue, Jul 4, 2023 at 10:42 AM Mauro Matteo Cascella
wrote:
> A wrong exit condition may lead to an infinite loop when inflating a
> valid zlib buffer containing some extra bytes in the `inflate_buffer`
> function. The bug only occurs post-authentication. Return the buffer
> immediately if the e
On Mon, Jun 26 2023, Shaoqin Huang wrote:
> Copy in the SMCCC definitions from the kernel, which will be used to
> implement SMCCC handling in userspace.
>
> Signed-off-by: Shaoqin Huang
> ---
> linux-headers/linux/arm-smccc.h | 240
> 1 file changed, 240 insert
On Mon, Jun 26 2023, Shaoqin Huang wrote:
> The SMCCC call filtering provide the ability to forward the SMCCC call
> to userspace, so we provide a new option `user-smccc` to enable handling
> SMCCC call in userspace, the default value is off.
>
> And add the skeleton implementation for userspace
From: Marc-André Lureau
Commit 9462ff4695aa0 ("virtio-gpu/win32: allocate shareable 2d
resources/images") introduces a division, which can lead to crashes when
"height" is 0.
Fixes: https://gitlab.com/qemu-project/qemu/-/issues/1744
Signed-off-by: Marc-André Lureau
---
hw/display/virtio-gpu.c
On 04/07/2023 11.19, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
Commit 9462ff4695aa0 ("virtio-gpu/win32: allocate shareable 2d
resources/images") introduces a division, which can lead to crashes when
"height" is 0.
Fixes: https://gitlab.com/qemu-project/qemu/-/issues/1744
Signe
On 230704 1119, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau
>
> Commit 9462ff4695aa0 ("virtio-gpu/win32: allocate shareable 2d
> resources/images") introduces a division, which can lead to crashes when
> "height" is 0.
>
> Fixes: https://gitlab.com/qemu-project/qemu/-/issues/174
On Tue, Jul 4, 2023 at 11:24 AM Thomas Huth wrote:
> On 04/07/2023 11.19, marcandre.lur...@redhat.com wrote:
> > From: Marc-André Lureau
> >
> > Commit 9462ff4695aa0 ("virtio-gpu/win32: allocate shareable 2d
> > resources/images") introduces a division, which can lead to crashes when
> > "height
> On Thu, Jun 15, 2023 at 02:13:02PM +0800, zhanghao1 wrote:
> > Each vcpu creates a corresponding timer task. The watchdog
> > is driven by a timer according to a certain period. Each time
> > the timer expires, the counter is decremented. When the counter
> > is "0", the watchdog considers the vc
It is useful to extend the number of available PCI devices to KVM guests
for passthrough scenarios and also to expose these models to a different
(big endian) architecture.
Signed-off-by: Cédric Le Goater
---
hw/s390x/Kconfig | 4
1 file changed, 4 insertions(+)
diff --git a/hw/s390x/Kconf
On Tue, 4 Jul 2023, Philippe Mathieu-Daudé wrote:
On 4/7/23 00:02, BALATON Zoltan wrote:
It is more readable to wrap the complex call to ppc_dcr_register in a
macro when needed repeatedly.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 76 +
On Tue, 4 Jul 2023, Philippe Mathieu-Daudé wrote:
On 4/7/23 00:02, BALATON Zoltan wrote:
Add a QOM type name define for ppc4xx-host-bridge in the common header
and replace direct use of the string name with the constant.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_pcix.c| 3 ++-
hw/
On Wed, Jun 28, 2023 at 02:31:39PM +0200, Roger Pau Monné wrote:
> On Fri, Jun 23, 2023 at 03:04:21PM +, osstest service owner wrote:
> > flight 181558 xen-unstable real [real]
> > http://logs.test-lab.xenproject.org/osstest/logs/181558/
> >
> > Regressions :-(
> >
> > Tests which did not suc
On Tue, 4 Jul 2023, Philippe Mathieu-Daudé wrote:
On 4/7/23 00:02, BALATON Zoltan wrote:
The iomem memory region is better used for the PCI IO space but
currently used for registers. Stop using it for that to allow this to
be cleaned up in the next patch.
Signed-off-by: BALATON Zoltan
---
hw
On Tue, Jul 4, 2023 at 11:03 AM Marc-André Lureau
wrote:
>
>
>
> On Tue, Jul 4, 2023 at 10:42 AM Mauro Matteo Cascella
> wrote:
>>
>> A wrong exit condition may lead to an infinite loop when inflating a
>> valid zlib buffer containing some extra bytes in the `inflate_buffer`
>> function. The bug
On Tue, 4 Jul 2023, Philippe Mathieu-Daudé wrote:
On 4/7/23 00:02, BALATON Zoltan wrote:
Add separate memory regions for the mem and io spaces of the PCIe bus
to avoid different buses using the same system io region.
"Reduce the I/O space to 64K."
Unlike the other similar patch this does not
On 4/7/23 11:33, BALATON Zoltan wrote:
On Tue, 4 Jul 2023, Philippe Mathieu-Daudé wrote:
On 4/7/23 00:02, BALATON Zoltan wrote:
It is more readable to wrap the complex call to ppc_dcr_register in a
macro when needed repeatedly.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 76 +
On Tue, Jul 04, 2023 at 10:37:38AM +0100, Anthony PERARD wrote:
> On Wed, Jun 28, 2023 at 02:31:39PM +0200, Roger Pau Monné wrote:
> > On Fri, Jun 23, 2023 at 03:04:21PM +, osstest service owner wrote:
> > > flight 181558 xen-unstable real [real]
> > > http://logs.test-lab.xenproject.org/osstes
On 4/7/23 11:37, BALATON Zoltan wrote:
On Tue, 4 Jul 2023, Philippe Mathieu-Daudé wrote:
On 4/7/23 00:02, BALATON Zoltan wrote:
The iomem memory region is better used for the PCI IO space but
currently used for registers. Stop using it for that to allow this to
be cleaned up in the next patch.
Hi Shaoqin,
Just saw this. Apologies. I missed to reply this earlier as I was bit
disconnected for last few days.
> From: Shaoqin Huang
> Sent: Tuesday, June 27, 2023 3:35 AM
> Hi Salil,
>
> On 6/26/23 21:42, Salil Mehta wrote:
> >> From: Shaoqin Huang
> >> Sent: Monday, June 26, 2023 7:49 AM
On 04/07/2023 07:42, Joel Stanley wrote:
Rename the functions to include P9 in the name in preparation for adding
P10 versions.
Correct the unimp read message while we're changing the function.
Reviewed-by: Cédric Le Goater
Signed-off-by: Joel Stanley
---
Reviewed-by: Frederic Barrat
On 04/07/2023 07:42, Joel Stanley wrote:
Make the existing pnv_quad_xscom_read/write be P9 specific, in
preparation for a different P10 callback.
Reviewed-by: Cédric Le Goater
Signed-off-by: Joel Stanley
---
Reviewed-by: Frederic Barrat
Fred
v2: Add scom region size to class
---
On 8/6/23 16:46, Peter Maydell wrote:
On Wed, 31 May 2023 at 21:36, Philippe Mathieu-Daudé wrote:
Extract arm_timer_reset() before converting this model to QOM/QDev
in few commits. This will become our DeviceReset handler.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/timer/arm_timer.c | 7
On 04/07/2023 11.32, Cédric Le Goater wrote:
It is useful to extend the number of available PCI devices to KVM guests
for passthrough scenarios and also to expose these models to a different
(big endian) architecture.
Maybe mention that these devices can work on s390x since they support MSI-X
On 04/07/2023 07:42, Joel Stanley wrote:
Add a PnvQuad class for the P10 powernv machine. No xscoms are
implemented yet, but this allows them to be added.
The size is reduced to avoid the quad region from overlapping with the
core region.
address-space: xscom-0
-0
On 04/07/2023 07:42, Joel Stanley wrote:
Firmware now warns if booting in LPAR per core mode (PPC bit 62). So
this warning doesn't trigger, report the core thread state is 0.
Reviewed-by: Cédric Le Goater
Signed-off-by: Joel Stanley
---
Reviewed-by: Frederic Barrat
Fred
hw/ppc/pn
On 04/07/2023 07:42, Joel Stanley wrote:
Like the quad xscoms, add a core model for P10 to allow future
differentiation from P9.
Signed-off-by: Joel Stanley
---
Reviewed-by: Frederic Barrat
Fred
hw/ppc/pnv_core.c | 44 ++--
1 file changed,
On Tue, 4 Jul 2023, Philippe Mathieu-Daudé wrote:
On 4/7/23 11:37, BALATON Zoltan wrote:
On Tue, 4 Jul 2023, Philippe Mathieu-Daudé wrote:
On 4/7/23 00:02, BALATON Zoltan wrote:
The iomem memory region is better used for the PCI IO space but
currently used for registers. Stop using it for that
On 7/3/23 15:31, Cédric Le Goater wrote:
On 7/3/23 15:06, ~ssinprem wrote:
From: Sittisak Sinprem
- I2C list follow I2C Tree v1.6 20230320
- fru eeprom data use FB FRU format version 4
Signed-off-by: Sittisak Sinprem
Super !
Reviewed-by: Cédric Le Goater
Taking that back.
I missed a
On 30/06/2023 11.17, Pierre Morel wrote:
The topology information are attributes of the CPU and are
specified during the CPU device creation.
On hot plug we:
- calculate the default values for the topology for drawers,
books and sockets in the case they are not specified.
- verify the CPU att
> On 04-Jul-2023, at 11:09 AM, Ani Sinha wrote:
>
>
>
>> On 04-Jul-2023, at 10:31 AM, Akihiko Odaki wrote:
>>
>> On 2023/07/03 15:08, Ani Sinha wrote:
On 02-Jul-2023, at 10:29 AM, Michael S. Tsirkin wrote:
On Sat, Jul 01, 2023 at 04:09:31PM +0900, Akihiko Odaki wrote:
On Tue, Jul 04, 2023 at 04:03:54PM +0530, Ani Sinha wrote:
>
>
> > On 04-Jul-2023, at 11:09 AM, Ani Sinha wrote:
> >
> >
> >
> >> On 04-Jul-2023, at 10:31 AM, Akihiko Odaki
> >> wrote:
> >>
> >> On 2023/07/03 15:08, Ani Sinha wrote:
> On 02-Jul-2023, at 10:29 AM, Michael S. Tsirkin w
On 03/07/2023 19:56, Philippe Mathieu-Daudé wrote:
External email: Use caution opening links or attachments
On 3/7/23 18:39, Avihai Horon wrote:
vfio_realize() has the following flow:
1. vfio_bars_prepare() -- sets VFIOBAR->size.
2. msix_early_setup().
3. vfio_bars_register() -- allocates VF
I think the issue is that the value returned from brk(0) is no longer
page aligned.
$ ./qemu-riscv64 -strace ../exe1
18329 brk(NULL) = 0x00303000
18329 faccessat(AT_FDCWD,"/etc/ld.so.preload",R_OK,0x3010d0) = -1 errno=2 (No
such file or directory)
18329 openat(AT_FDCWD,"/etc/ld.so.cache"
From: Sittisak Sinprem
- I2C list follow I2C Tree v1.6 20230320
- fru eeprom data use FB FRU format version 4
Signed-off-by: Sittisak Sinprem
---
docs/system/arm/aspeed.rst | 1 +
hw/arm/aspeed.c| 63 ++
hw/arm/aspeed_eeprom.c | 50 +
Hi Cédric,
Please stop this patch,
after the test, the eeprom content is incorrect,
root@bmc:~# weutil -l
bmc_eeprom/sys/bus/i2c/devices/i2c-8/8-0051/eeprom
chassis_eeprom/sys/bus/i2c/devices/i2c-6/6-0053/eeprom
dummy_eeprom/etc/weutil/meta_eeprom_v4_sample.bin
scm_eeprom/sys/bus/
> On 04-Jul-2023, at 4:06 PM, Michael S. Tsirkin wrote:
>
> On Tue, Jul 04, 2023 at 04:03:54PM +0530, Ani Sinha wrote:
>>
>>
>>> On 04-Jul-2023, at 11:09 AM, Ani Sinha wrote:
>>>
>>>
>>>
On 04-Jul-2023, at 10:31 AM, Akihiko Odaki
wrote:
On 2023/07/03 15:08, Ani Sin
From: Sittisak Sinprem
- I2C list follow I2C Tree v1.6 20230320
- fru eeprom data use FB FRU format version 4
Signed-off-by: Sittisak Sinprem
---
docs/system/arm/aspeed.rst | 1 +
hw/arm/aspeed.c| 65 ++
hw/arm/aspeed_eeprom.c | 50 +
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