On 6/21/23 18:03, Frederic Barrat wrote:
The presenters for xive on P9 and P10 are mostly similar but the
behavior can be tuned through a few CQ registers. This patch adds a
"get_config" method, which will allow to access that config from the
presenter in a later patch.
For now, just define the c
On 6/20/23 12:45, Nicholas Piggin wrote:
On Tue Jun 20, 2023 at 8:27 PM AEST, Cédric Le Goater wrote:
On 6/20/23 12:12, Nicholas Piggin wrote:
On Wed Jun 7, 2023 at 12:09 AM AEST, Cédric Le Goater wrote:
On 6/5/23 13:23, Nicholas Piggin wrote:
Previous RFC here
https://lists.gnu.org/archive/
Richard Henderson wrote:
> On 6/22/23 04:12, Juan Quintela wrote:
>> The following changes since commit 67fe6ae41da64368bc4936b196fee2bf61f8c720:
>>Merge tag 'pull-tricore-20230621-1'
>> ofhttps://github.com/bkoppelmann/qemu into staging (2023-06-21
>> 20:08:48 +0200)
>> are available in the
On 6/4/23 01:36, Nicholas Piggin wrote:
This adds support for chiptod and core timebase state machine models in
the powernv POWER9 and POWER10 models.
This does not actually change the time or the value in TB registers
(because they are alrady synced in QEMU), but it does go through the
motions.
This bug tracker here is not active anymore. If you want to report bugs,
please open a new ticket at https://gitlab.com/qemu-
project/qemu/-/issues , thanks.
** Changed in: qemu
Status: Confirmed => Invalid
--
You received this bug notification because you are a member of qemu-
devel-ml,
Le 21/06/2023 à 10:53, Mark Cave-Ayland a écrit :
[MCA: the original series has now been split into 2 separate parts based upon
Phil's comments re: QOM parenting for objects in Q800MachineState. Part 1
consists of the Q800MachineState patches along with QOM parenting fixes and
the 2 mac_via RTC p
On Wed, 21 Jun 2023 13:24:42 -0400
Joel Upham wrote:
> On Wed, Jun 21, 2023 at 7:28 AM Igor Mammedov wrote:
>
> > On Tue, 20 Jun 2023 13:24:36 -0400
> > Joel Upham wrote:
> >
> > > On Q35 we still need to assign BSEL property to bus(es) for PCI device
> > > add/hotplug to work.
> > > Extend
On 22/06/23 7:43 am, Juan Quintela wrote:
> From: Tejus GK
>
> There are places in migration.c where the migration is marked failed with
> MIGRATION_STATUS_FAILED, but the failure reason is never updated. Hence
> libvirt doesn't know why the migration failed when it queries for it.
>
> Reviewed-
21.06.2023 19:14, Bastian Koppelmann wrote:
From: Siqi Chen
When translating "imask" instruction of Tricore architecture, QEMU did not
check whether the register index was out of bounds, resulting in a global-buffer-overflow.
Reviewed-by: Bastian Koppelmann
Resolves: https://gitlab.com/qemu
On 22/06/2023 09:01, Cédric Le Goater wrote:
On 6/21/23 18:03, Frederic Barrat wrote:
The presenters for xive on P9 and P10 are mostly similar but the
behavior can be tuned through a few CQ registers. This patch adds a
"get_config" method, which will allow to access that config from the
prese
From: Mark Cave-Ayland
Also change the instantiation of the VIA2 device to use
object_initialize_child().
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
Message-Id: <20230621085353.113233-14-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: Lauren
From: Mark Cave-Ayland
This provides an overall container and owner for Machine-related objects such
as MemoryRegions.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20230621085353.113233-4-mark.cave-ayl...@ilande.co.uk>
Signed-off
From: Mark Cave-Ayland
Also change the instantiation of the VIA1 device to use
object_initialize_child().
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
Message-Id: <20230621085353.113233-13-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: Lauren
From: Mark Cave-Ayland
This will enable us later to distinguish between QOM initialisation and machine
initialisation.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20230621085353.113233-5-mark.cave-ayl...@ilande.co.uk>
Signed-off
From: Mark Cave-Ayland
This is to enable them to be used outside of dp8393x.c.
Signed-off-by: Mark Cave-Ayland
CC: Jason Wang
Reviewed-by: Laurent Vivier
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20230621085353.113233-15-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: Laurent Vivier
--
From: Mark Cave-Ayland
Also change the instantiation of the ESCC device to use
object_initialize_child().
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
Message-Id: <20230621085353.113233-17-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: Lauren
From: Mark Cave-Ayland
Move all devices from the IO region to within the container in preparation
for updating the IO aliasing mechanism.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20230621085353.113233-11-mark.cave-ayl...@ilan
From: Mark Cave-Ayland
A comparison between the rtc command table included in the comment and the code
itself shows that the decoding for PRAM addresses 0x0 to 0xf is being done on
the raw command, and not the shifted version held in value.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent V
From: Mark Cave-Ayland
Also change the instantiation of the ESP device to use
object_initialize_child().
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
Message-Id: <20230621085353.113233-19-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: Laurent
From: Mark Cave-Ayland
Also change the instantiation of the SWIM device to use
object_initialize_child().
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
Message-Id: <20230621085353.113233-20-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: Lauren
From: Mark Cave-Ayland
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
Message-Id: <20230621085353.113233-7-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: Laurent Vivier
---
include/hw/m68k/q800.h | 2 ++
hw/m68k/q800.c | 13 +--
From: Mark Cave-Ayland
The current use of aliased memory regions causes us 2 problems: firstly the
output of "info qom-tree" is absolutely huge and difficult to read, and
secondly we have already reached the internal limit for memory regions as
adding any new memory region into the mac-io region
From: Mark Cave-Ayland
Also change the instantiation of the CPU to use object_initialize_child()
followed by a separate realisation.
Restrict valid CPU types to m68040.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20230621085353.
From: Mark Cave-Ayland
Also change the instantiation of the escc_orgate device to use
object_initialize_child().
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
Message-Id: <20230621085353.113233-18-mark.cave-ayl...@ilande.co.uk>
Signed-off-by:
From: Mark Cave-Ayland
This will allow the q800-glue.h header to be included separately so that the
GLUE device can be referenced externally.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20230621085353.113233-8-mark.cave-ayl...@i
From: Mark Cave-Ayland
Also change the instantiation of the dp8393x device to use
object_initialize_child().
Signed-off-by: Mark Cave-Ayland
CC: Jason Wang
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
Message-Id: <20230621085353.113233-16-mark.cave-ayl...@ilande.co.uk>
Si
From: Mark Cave-Ayland
The use of the DEFINE_TYPES() macro will soon be recommended over the use of
calling type_init() directly.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20230621085353.113233-9-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: Laurent Vivie
From: Mark Cave-Ayland
Also change the instantiation of the mac-nubus-bridge device to use
object_initialize_child() and map the Nubus address space using
memory_region_add_subregion() instead of sysbus_mmio_map().
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
Reviewed-by: Philip
00-for-8.1-pull-request
for you to fetch changes up to 532009054b45d75a3cf7ba9c31921add669d290d:
mac_via: fix rtc command decoding for the PRAM seconds registers (2023-06-22
09:31:18 +0200)
Q800 branch pull request 20230622
From: Mark Cave-Ayland
Also change the instantiation of the GLUE device to use
object_initialize_child().
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
Message-Id: <20230621085353.113233-10-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: Lauren
From: Mark Cave-Ayland
Analysis of the MacOS toolbox ROM code shows that on startup it attempts 2
separate reads of the seconds registers with commands 0x9d...0x91 followed by
0x8d..0x81 without resetting the command to its initial value. The PRAM seconds
value is only accepted when the values of
From: Mark Cave-Ayland
Instead use the qdev_get_child_bus() function which is intended for this exact
purpose.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20230621085353.113233-22-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: La
From: Mark Cave-Ayland
Ensure there is a space before the final closing brace for all global
properties.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20230621085353.113233-2-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: Laurent V
From: Mark Cave-Ayland
This brings GLUEState in line with our current QOM guidelines.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
Message-Id: <20230621085353.113233-3-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: Laurent Vivier
---
hw/m68k
From: Mark Cave-Ayland
Also change the instantiation of the macfb device to use
object_initialize_child().
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
Message-Id: <20230621085353.113233-23-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: Laure
On 6/21/23 16:39, Nicholas Piggin wrote:
The top bits of the LEV field of the sc instruction are to be treated as
as a reserved field rather than a reserved value, meaning LEV is
effectively the bottom bit. LEV=0xF should be treated as LEV=1 and be
a hypercall, for example.
This changes the i
On 6/12/23 22:51, Juan Quintela wrote:
Shall we just leave it there? Or is deprecating it helps us in any form?
See the patches two weeks ago when people complained that lisen(.., num)
was too low. And there are other parameters that work the same way
(that I convenientely had forgotten). So
On 6/21/23 09:08, Thomas Huth wrote:
if (strcmp(incoming, "defer") != 0) {
+ warn_report("-incoming %s is deprecated, use -incoming
defer and "
+ " set the uri with migrate-incoming.",
incoming);
qmp_migrate_incoming(incoming, &local_e
On 16/06/2023 17.20, Nina Schoetterl-Glausch wrote:
On Mon, 2023-06-05 at 11:52 +0200, Paolo Bonzini wrote:
In the beginning, the network bootloader was considered experimental and
thus optional, but it is well established nowadays and configure always
checks for roms/SLOF before compiling pc-bi
On 20/06/2023 17.37, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
Hi,
Submitting again this small series from last year.
Marc-André Lureau (2):
gitlab-ci: grab msys2 meson-logs as artifacts
gitlab-ci: add msys2 meson test to junit report
.gitlab-ci.d/windows.yml | 15 ++
On 6/22/23 09:53, Frederic Barrat wrote:
On 22/06/2023 09:01, Cédric Le Goater wrote:
On 6/21/23 18:03, Frederic Barrat wrote:
The presenters for xive on P9 and P10 are mostly similar but the
behavior can be tuned through a few CQ registers. This patch adds a
"get_config" method, which will a
Paolo Bonzini wrote:
> On 6/12/23 22:51, Juan Quintela wrote:
>>> Shall we just leave it there? Or is deprecating it helps us in any form?
>> See the patches two weeks ago when people complained that lisen(.., num)
>> was too low. And there are other parameters that work the same way
>> (that I
On 21/6/23 20:06, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 21/6/23 20:06, Richard Henderson wrote:
We incorporate %asi into tb->flags so that we may generate
inline code for the many ASIs for which it is easy to do so.
Setting %asi is common for e.g. memcpy and memset performing
block copy and clear, so it is worth noticing this case.
We must end the
On 21/6/23 14:18, Richard Henderson wrote:
Move to fill a hole in the set of bits.
Reduce the total number of tlb bits by 1.
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 4 ++--
tcg/tcg-op-ldst.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: P
On 21/6/23 14:18, Richard Henderson wrote:
This frees up one bit of the primary tlb flags without
impacting the TLB_NOTDIRTY logic.
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 8
accel/tcg/cputlb.c | 18 ++
2 files changed, 18 insertions(+), 8
On 22/06/2023 10.52, Juan Quintela wrote:
Paolo Bonzini wrote:
On 6/12/23 22:51, Juan Quintela wrote:
Shall we just leave it there? Or is deprecating it helps us in any form?
See the patches two weeks ago when people complained that lisen(.., num)
was too low. And there are other parameters
On Wed, Jun 21, 2023 at 9:08 AM Paolo Bonzini wrote:
> Maybe patch 4 can use distlib.scripts as well to create the check script in
> the build directory? (Yes that's another mkvenv functionality...) On a phone
> and don't have the docs at hand, so I am not sure. If not, your solution is
> good
This series is based on some previously posted TCG fixes, in particular
the CTRL register fix is required.
Also added the Philippe's patch in the series to prevent conflict.
Since v1, main changes are just some tidying of comments and changelogs,
and addition of avocado tests to boot Linux on SMT
PPC TCG supports SMT CPU configurations for non-hypervisor state, so
permit POWER8-10 pseries machines to enable SMT.
This requires PIR and TIR be set, because that's how sibling thread
matching is done by TCG.
spapr's nested-HV capability does not currently coexist with SMT, so
that combination
Doorbells in SMT need to coordinate msgsnd/msgclr and DPDES access from
multiple threads that affect the same state.
Signed-off-by: Nicholas Piggin
---
hw/ppc/ppc.c | 6 ++
include/hw/ppc/ppc.h | 1 +
target/ppc/excp_helper.c | 30 ++-
target/ppc/mis
Add mult-thread/core/socket Linux boot tests that ensure the right
topology comes up. Of particular note is a SMT test, which is a new
capability for TCG.
Signed-off-by: Nicholas Piggin
---
tests/avocado/ppc_pseries.py | 60 +---
1 file changed, 55 insertions(+),
TGC SMT emulation needs to know whether it is running with SMT siblings,
to be able to iterate over siblings in a core, and to serialise
threads to access per-core shared SPRs. Add infrastructure to do these
things.
For now the sibling iteration and serialisation are implemented in a
simple but in
From: Philippe Mathieu-Daudé
Although the PPC target only supports the TCG and KVM
accelerators, QEMU supports more. We can not assume that
'!kvm == tcg', so test for the correct accelerator. This
also eases code review, because here we don't care about
KVM, we really want to test for TCG.
Revie
This machine can boot Linux to VFS mount, so don't stop in early boot.
Signed-off-by: Nicholas Piggin
---
tests/avocado/ppc_pseries.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/avocado/ppc_pseries.py b/tests/avocado/ppc_pseries.py
index d8b04dc3ea..a152cf222e 1006
A relatively simple case to begin with, CTRL is a SMT shared register
where reads and writes need to synchronise against state changes by
other threads in the core.
Atomic serialisation operations are used to achieve this.
Signed-off-by: Nicholas Piggin
---
target/ppc/helper.h | 2 ++
tar
Print RvV extesion register to log if VPU option is enabled.
Signed-off-by: Ivan Klokov
---
v4:
- General part of patch has been merged, rebase riscv part and resend.
---
target/riscv/cpu.c | 56 +-
1 file changed, 55 insertions(+), 1 deletion(-)
On 6/22/23 10:52, Juan Quintela wrote:
User friendliness.
The problem is that if you use more than two channels with multifd, on
the incoming side, you need to do:
You're sacrificing user-friendliness for the 99.99% that don't use
multifd, for an error (i.e. it's not even fixing the issue) f
On 6/22/23 10:42, Thomas Huth wrote:
Only if run in a git repository, not in a tree generated with
archive-source.sh
which doesn't package roms/SLOF.
So without the check below the build fails.
This is not inteded, is it?
I guess archive-source.sh needs to be changed to include the SLOF
sou
On 6/21/23 16:20, Nina Schoetterl-Glausch wrote:
On Wed, 2023-06-21 at 16:07 +0200, Nina Schoetterl-Glausch wrote:
On Tue, 2023-06-20 at 22:44 +0200, Paolo Bonzini wrote:
Il mar 20 giu 2023, 19:35 Nina Schoetterl-Glausch ha
scritto:
+ modules="$modules $m"
+ grep $m $
The call to git-submodule.sh done in configure may happen without a
previous checkout of the roms/SLOF submodule, or even without a
previous run of the script.
So, handle creating a .git-submodule-status file even in validate
mode. If git is absent, ensure that all passed directories exists
(beca
On Thu Jun 22, 2023 at 5:30 PM AEST, Cédric Le Goater wrote:
> On 6/4/23 01:36, Nicholas Piggin wrote:
> > This adds support for chiptod and core timebase state machine models in
> > the powernv POWER9 and POWER10 models.
> >
> > This does not actually change the time or the value in TB registers
On 21/6/23 14:18, Richard Henderson wrote:
We have run out of bits we can use within the CPUTLBEntry comparators,
as TLB_FLAGS_MASK cannot overlap alignment.
Store slow_flags[] in CPUTLBEntryFull, and merge with the flags from
the comparator. A new TLB_FORCE_SLOW bit is set within the comparato
On Thu, Jun 22, 2023 at 10:52:12AM +0200, Juan Quintela wrote:
> Paolo Bonzini wrote:
> > On 6/12/23 22:51, Juan Quintela wrote:
> >>> Shall we just leave it there? Or is deprecating it helps us in any form?
> >> See the patches two weeks ago when people complained that lisen(.., num)
> >> was to
On 21/6/23 14:19, Richard Henderson wrote:
This creates a per-page method for checking of alignment.
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 4 +++-
accel/tcg/cputlb.c | 27 ++-
2 files changed, 29 insertions(+), 2 deletions(-)
Reviewed-b
Paolo Bonzini wrote:
> On 6/22/23 10:52, Juan Quintela wrote:
>> User friendliness.
>> The problem is that if you use more than two channels with multifd, on
>> the incoming side, you need to do:
>
> You're sacrificing user-friendliness for the 99.99% that don't use
> multifd, for an error (i.e. i
On 21/6/23 14:18, Richard Henderson wrote:
Now that we have removed TARGET_PAGE_BITS_MIN-6 from
TLB_FLAGS_MASK, we can test for 32-byte alignment.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate.c | 8 +---
1 file changed, 1 insertion(+), 7 delet
On 21/6/23 16:06, Mark Cave-Ayland wrote:
On 21/06/2023 10:42, Philippe Mathieu-Daudé wrote:
On 21/6/23 10:53, Mark Cave-Ayland wrote:
[MCA: the original series has now been split into 2 separate parts
based upon
Phil's comments re: QOM parenting for objects in Q800MachineState.
Part 1
consis
On 6/22/23 11:33, Nicholas Piggin wrote:
PPC TCG supports SMT CPU configurations for non-hypervisor state, so
permit POWER8-10 pseries machines to enable SMT.
This requires PIR and TIR be set, because that's how sibling thread
matching is done by TCG.
spapr's nested-HV capability does not curre
On Wed, Jun 07, 2023 at 11:38:59AM -0700, Steve Sistare wrote:
> Extend the migration URI to support file:. This can be used for
> any migration scenario that does not require a reverse path. It can be used
> as an alternative to 'exec:cat > file' in minimized containers that do not
> contain /bi
Per commit 067109a11c ("docs/devel: mention the spacing requirement
for QOM"):
For a storage structure the first declaration should always be
called “parent_obj” and for a class structure the first member
should always be called “parent_class”
Adapt the QOM rST document accordingly.
Report
Some fixes were committed in bios-tables-test in the previous commit. Update
the acpi blob and clear bios-tables-test-allowed-diff.h so that the test
continues to pass with the changes in the bios-tables-test.
Following is the asl diff between the old and the newly updated blob:
@@ -1,30 +1,30 @@
PCIE ports only have one slot, slot 0. Hence, non-zero slots are not available
for PCIE devices on PCIE root ports. Fix test_acpi_q35_tcg_no_acpi_hotplug()
so that the test does not use them.
Signed-off-by: Ani Sinha
---
tests/qtest/bios-tables-test.c | 4 ++--
1 file changed, 2 insertions(+), 2
We are going to fix bio-tables-test in the next patch and hence need to
make sure the acpi tests continue to pass.
Signed-off-by: Ani Sinha
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qte
Patches 1-4:
Fix tests so that devices do not use non-zero slots on the pcie root
ports. PCIE ports only have one slot, so PCIE devices can only be
plugged into slot 0 on a PCIE port.
Patch 5:
Enforce only one slot on PCIE port.
The test fixes must be applied before the QEMU change that checks fo
PCI Express ports only have one slot, so PCI Express devices can only be
plugged into slot 0 on a PCIE port. Enforce it.
CC: jus...@redhat.com
CC: imamm...@redhat.com
Resolves: https://bugzilla.redhat.com/show_bug.cgi?id=2128929
Signed-off-by: Ani Sinha
---
hw/pci/pci.c | 6 ++
1 file change
A SCSI controller can be attached to a pcie-to-pci bridge which in turn can be
attached directly to the root bus (peie.0). There is no need to attach a
pcie-root-port on the root bus in order to attach the pcie-ro-pci bridge.
Fix it.
CC: m...@redhat.com
CC: imamm...@redhat.com
CC: Michael Labiuk
> On 21-Jun-2023, at 5:20 PM, Ani Sinha wrote:
>
>
>
>> On 21-Jun-2023, at 4:55 PM, Ani Sinha wrote:
>>
>>
>>
>>> On 21-Jun-2023, at 4:36 PM, Ani Sinha wrote:
>>>
>>>
>>>
On 20-Jun-2023, at 4:13 PM, Michael S. Tsirkin wrote:
On Tue, Jun 20, 2023 at 12:48:05PM +0530,
On 6/22/23 12:06, Cédric Le Goater wrote:
On 6/22/23 11:33, Nicholas Piggin wrote:
PPC TCG supports SMT CPU configurations for non-hypervisor state, so
permit POWER8-10 pseries machines to enable SMT.
This requires PIR and TIR be set, because that's how sibling thread
matching is done by TCG.
On Thu Jun 22, 2023 at 6:00 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 6/21/23 16:39, Nicholas Piggin wrote:
> > The top bits of the LEV field of the sc instruction are to be treated as
> > as a reserved field rather than a reserved value, meaning LEV is
> > effectively the bottom bit. LEV=0xF sho
[...]
We'd use a memory region container as device memory region (like [1]) and would
have to handle the !memdev case (I can help with that). > Into that, you can
map the RAM memory region on demand (and eventually even using multiple slots like
[1]).
(2) Use a single virtual DIMM and (un)pl
On 22.06.2023 13:01, David Hildenbrand wrote:
[...]
We'd use a memory region container as device memory region (like [1]) and would
have to handle the !memdev case (I can help with that). > Into that, you can
map the RAM memory region on demand (and eventually even using multiple slots like
On 22.06.23 13:12, Maciej S. Szmigiero wrote:
On 22.06.2023 13:01, David Hildenbrand wrote:
[...]
We'd use a memory region container as device memory region (like [1]) and would
have to handle the !memdev case (I can help with that). > Into that, you can
map the RAM memory region on demand (
On 22.06.2023 13:15, David Hildenbrand wrote:
On 22.06.23 13:12, Maciej S. Szmigiero wrote:
On 22.06.2023 13:01, David Hildenbrand wrote:
[...]
We'd use a memory region container as device memory region (like [1]) and would
have to handle the !memdev case (I can help with that). > Into that,
Like in the normal ram_load() path, put the received pages into the
colo cache and mark the pages in the bitmap so that they will be
flushed to the guest later.
Signed-off-by: Juan Quintela
Signed-off-by: Lukas Straub
---
migration/meson.build| 1 +
migration/multifd-colo.c | 53 ++
If the guest issues a discard during a block drain section, the
blk_aio_pdiscard() may not be processed, but queued instead.
And so the callback will never be called to issue the bh and decrease
the BB in-flight number again.
This causes a hang in the drain code, since it will wait forever for the
When we still have an AIOCB registered for DMA operations, we try to
settle the respective operation by draining the BlockBackend associated
with the IDE device.
However, this assumes that every DMA operation is associated with some
I/O operation on the BlockBackend, and so settling the latter wil
Legacy savevm devices only implement save_state() and load_state().
Iterable devices shouldn't implement save_state() or else they are
handled both as an iterable and legacy device in the savevm code.
Signed-off-by: Lukas Straub
---
Note: this patch is completely untested.
hw/vfio/migration.c
Signed-off-by: Lukas Straub
---
migration/savevm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/migration/savevm.c b/migration/savevm.c
index 5986f852b2..8d3cf7d675 100644
--- a/migration/savevm.c
+++ b/migration/savevm.c
@@ -774,6 +774,8 @@ int register_savevm_live(const char *idstr,
On 6/21/23 21:28, Alex Williamson wrote:
On Wed, 21 Jun 2023 14:11:53 +0300
Avihai Horon wrote:
Hello everyone,
The latest changes to migration qtest made the tests run non-live by
default. I am posting this v6 to change back the switchover-ack
migration test to run live as it used to (becaus
On Tue, 13 Jun 2023 16:57:40 +0200
Juan Quintela wrote:
> Signed-off-by: Juan Quintela
> ---
> migration/options.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/migration/options.c b/migration/options.c
> index b62ab30cd5..c6674a4753 100644
> --- a/migration/options.c
> +++ b
On Tue, 13 Jun 2023 16:57:41 +0200
Juan Quintela wrote:
> As we have disable to use both together in the previous patch, we can
> remove this check.
This commit message is off.
>
> Signed-off-by: Juan Quintela
> ---
> migration/options.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff
It's good style to clean up temporary directories when they
are not needed anymore.
Signed-off-by: Thomas Huth
---
tests/qtest/cxl-test.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c
index edcad4a0ce..a600331843 100644
--- a/tests/qtest/cx
On Tue, 13 Jun 2023 16:57:42 +0200
Juan Quintela wrote:
> So give an error instead of just ignoring the other methods.
>
> Signed-off-by: Juan Quintela
Reviewed-by: Lukas Straub
> ---
> migration/migration.c | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/migration/m
On Tue, 13 Jun 2023 16:57:44 +0200
Juan Quintela wrote:
> Signed-off-by: Juan Quintela
Reviewed-by: Lukas Straub
> ---
> migration/migration.c| 4 +---
> migration/ram-compress.c | 5 +
> migration/savevm.c | 1 -
> 3 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --g
On Tue, 13 Jun 2023 16:57:45 +0200
Juan Quintela wrote:
> So we don't have to access compression_counters from outside
> ram-compress.c.
>
> Signed-off-by: Juan Quintela
With the comment below fixed:
Reviewed-by: Lukas Straub
> ---
> migration/ram-compress.h | 3 +++
> migration/migration.
On Tue, 13 Jun 2023 16:57:46 +0200
Juan Quintela wrote:
> Signed-off-by: Juan Quintela
>
> fix ram_compress
>
> Signed-off-by: Juan Quintela
Commit message is off. Other than that:
Reviewed-by: Lukas Straub
> ---
> migration/ram-compress.h | 1 +
> migration/ram-compress.c | 6 ++
>
On Tue, 13 Jun 2023 16:57:47 +0200
Juan Quintela wrote:
> Signed-off-by: Juan Quintela
Reviewed-by: Lukas Straub
> ---
> migration/ram-compress.h | 1 +
> migration/ram-compress.c | 17 +
> migration/ram.c | 15 ---
> 3 files changed, 18 insertions(+), 1
On Tue, 13 Jun 2023 16:57:48 +0200
Juan Quintela wrote:
> Signed-off-by: Juan Quintela
Nit:
Probably makes sense to rename it to try_compress_page or similar.
And probably for zero_page and xbzrle (when factored out in it's own
function) too.
> ---
> migration/ram-compress.h | 4 ++--
> mig
On Tue, 13 Jun 2023 16:57:50 +0200
Juan Quintela wrote:
> And now we can simplify save_compress_page().
>
> Signed-off-by: Juan Quintela
Reviewed-by: Lukas Straub
> ---
> migration/ram-compress.c | 1 +
> migration/ram.c | 7 +--
> 2 files changed, 2 insertions(+), 6 deletions(
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