On Thu Jun 22, 2023 at 5:30 PM AEST, Cédric Le Goater wrote: > On 6/4/23 01:36, Nicholas Piggin wrote: > > This adds support for chiptod and core timebase state machine models in > > the powernv POWER9 and POWER10 models. > > > > This does not actually change the time or the value in TB registers > > (because they are alrady synced in QEMU), but it does go through the > > motions. It is enough to be able to run skiboot's chiptod initialisation > > code that synchronises core timebases (after a patch to prevent skiboot > > skipping chiptod for QEMU, posted to skiboot mailing list). > > > > Sorry there was some delay since the last posting. There is a bit more > > interest in this recently but feedback and comments from RFC was not > > forgotten and is much appreciated. > > > > https://lists.gnu.org/archive/html/qemu-ppc/2022-08/msg00324.html > > > > I think I accounted for everything except moving register defines to the > > .h file. I'm on the fence about that but if they are only used in the .c > > file I think it's okay to keep them there for now. I cut out a lot of > > unused ones so it's not so cluttered now. > > > > Lots of other changes and fixes since that RFC. Notably: > > - Register names changed to match the workbook names instead of skiboot. > > - TFMR moved to timebase_helper.c from misc_helper.c > > - More comprehensive model and error checking, particularly of TFMR. > > - POWER10 with multi-chip support. > > - chiptod and core timebase linked via specific state instead of TFMR. > > > > There is still a vast amount that is not modeled, but most of it related > > to error handling, injection, failover, etc that is very complicated and > > not required for normal operation. > > > > Thanks, > > Nick > > > > Nicholas Piggin (4): > > pnv/chiptod: Add POWER9/10 chiptod model > > target/ppc: Tidy POWER book4 SPR registration > > target/ppc: add TFMR SPR implementation with read and write helpers > > target/ppc: Implement core timebase state machine and TFMR > > patch 2-4 could be merged in the next PR. Could you please rebase on > ppc-next and resend ?
Good idea, I have a couple of other minor register additions that depend on patch 1 too. > Then we still have 2+ weeks to polish pnv/chiptod which would be a > nice addition to QEMU 8.1. Yeah. Been trying to get to it... Hopefully pseries SMT is close now so I will have some more time. Thanks, Nick
