On 20/06/2023 07:59, Cédric Le Goater wrote:
Fred and Nick have been hacking baremetal POWER systems (OPAL) for
many years. They use and modify the QEMU models regularly. Add them as
PowerNV reviewers.
Cc: Frédéric Barrat
Cc: Nicholas Piggin
Signed-off-by: Cédric Le Goater
---
Acked-by:
On 20/06/2023 07:59, Cédric Le Goater wrote:
Fred discusses frequently with the IBM HW designers, he is fluent in
XIVE logic, add him as a reviewer.
Cc: Frédéric Barrat
Signed-off-by: Cédric Le Goater
---
Acked-by: Frederic Barrat
Fred
MAINTAINERS | 1 +
1 file changed, 1 insert
When a device has an upstream PCIE port, we can only use slot 0. Non-zero slots
are invalid. This change ensures that we throw an error if the user
tries to hotplug a device with an upstream PCIE port to a non-zero slot.
CC: jus...@redhat.com
CC: imamm...@redhat.com
Resolves: https://bugzilla.redh
On 6/20/23 07:29, Philippe Mathieu-Daudé wrote:
On 19/6/23 16:02, Richard Henderson wrote:
One cannot test for feature aa32_simd_r32 without first
testing if AArch32 mode is supported at all. This leads to
qemu-system-aarch64: ARM CPUs must have both VFP-D32 and Neon or neither
for Apple M1 c
On 6/8/23 11:07, ~foxes wrote:
From: Foxes Hung
Signed-off-by: Foxes Hung
---
semihosting/syscalls.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/semihosting/syscalls.c b/semihosting/syscalls.c
index 68899ebb1c..1a5d39da01 100644
--- a/semihosting/syscalls.c
+++ b/semihosting/sysc
On 6/8/23 11:06, ~foxes wrote:
From: Foxes Hung
Signed-off-by: Foxes Hung
---
gdbstub/syscalls.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gdbstub/syscalls.c b/gdbstub/syscalls.c
index 02e3a8f74c..4c6b5f728b 100644
--- a/gdbstub/syscalls.c
+++ b/gdbstub/syscalls.c
On 6/19/23 19:34, Alex Bennée wrote:
Richard Henderson writes:
On 6/12/23 04:50, Richard Henderson wrote:
On 6/11/23 02:14, Alex Bennée wrote:
Richard Henderson writes:
This is a perfectly natural occurrence for x86 "rep movb",
where the "rep" prefix forms a counted loop of the one insn
Although the PPC target only supports the TCG and KVM
accelerators, QEMU supports more. We can no assume that
'!kvm == tcg', so test for the correct accelerator. This
also eases code review, because here we don't care about
KVM, we really want to test for TCG.
Signed-off-by: Philippe Mathieu-Daudé
On 6/20/23 09:48, Philippe Mathieu-Daudé wrote:
> Although the PPC target only supports the TCG and KVM
> accelerators, QEMU supports more. We can no assume that
> '!kvm == tcg', so test for the correct accelerator. This
> also eases code review, because here we don't care about
> KVM, we really wa
On 6/20/23 13:18, Philippe Mathieu-Daudé wrote:
Although the PPC target only supports the TCG and KVM
accelerators, QEMU supports more. We can no assume that
'!kvm == tcg', so test for the correct accelerator. This
also eases code review, because here we don't care about
KVM, we really want to
On 6/20/23 09:48, Philippe Mathieu-Daudé wrote:
Although the PPC target only supports the TCG and KVM
accelerators, QEMU supports more. We can no assume that
'!kvm == tcg', so test for the correct accelerator. This
also eases code review, because here we don't care about
KVM, we really want to te
Since we always check whether KVM is enabled before calling
kvm_riscv_reset_vcpu() and kvm_riscv_set_irq(), their call
is elided by the compiler when KVM is not available.
Therefore the stubs are not even linked. Remove them.
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/kvm-stub.c | 3
On 20/06/2023 04:04, Duan, Zhenzhong wrote:
>> -Original Message-
>> From: Avihai Horon
>> Sent: Monday, June 19, 2023 7:14 PM
> ...
>>> a/hw/vfio/migration.c b/hw/vfio/migration.c index
>>> 6b58dddb8859..bc51aa765cb8 100644
>>> --- a/hw/vfio/migration.c
>>> +++ b/hw/vfio/migration.c
>>> @
From: Philippe Mathieu-Daudé
We use the CONFIG_USER_ONLY key to describe user emulation,
and the CONFIG_SOFTMMU key to describe system emulation. Alias
it as 'CONFIG_SYSTEM_ONLY' for parity with user emulation.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <2
From: Philippe Mathieu-Daudé
Since cpu_mmu_index() is well-defined for user-only,
we can remove the surrounding #ifdef'ry entirely.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20230613133347.82210-2-phi...@linaro.org>
Signe
From: Philippe Mathieu-Daudé
We want to check the softmmu tlb availability, not
if we are targetting system emulation. Besides, this
code could be used by user emulation in the future.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20230605230216.17202-1-phi.
From: Philippe Mathieu-Daudé
Since we *might* have user emulation with softmmu,
replace the system emulation check by !user emulation one.
Invert some if() ladders for clarity.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20230613133347.82210-4-phi...@lina
Otherwise we hit the default assert not reached.
Handle it as MO_ATOM_NONE, because of size and misalignment.
We already handle this correctly in do_ld16_beN.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/a
Restructure the ifdef ladder, separating 64-bit from 32-bit,
and ensure _CALL_AIX is set for ELF v1. Fixes the build for
ppc64 big-endian host with clang.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 23 ---
1 file cha
From: Philippe Mathieu-Daudé
We only need lookup_tb_ptr() prototype.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20230611085846.21415-3-phi...@linaro.org>
Signed-off-by: Richard Henderson
---
accel/tcg/cpu-exec.c | 2 +-
1 file changed, 1 insertion(+), 1
From: Philippe Mathieu-Daudé
We use the user_ss[] array to hold the user emulation sources,
and the softmmu_ss[] array to hold the system emulation ones.
Hold the latter in the 'system_ss[]' array for parity with user
emulation.
Mechanical change doing:
$ sed -i -e s/softmmu_ss/system_ss/g $(
From: Philippe Mathieu-Daudé
Commit 2f3a57ee47 ("cputlb: ensure we save the IOTLB data in
case of reset") added the SavedIOTLB structure -- which is
system emulation specific -- in the generic CPUState structure.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id:
The macOS catalina compiler produces an error for __int128_t
as the type for allocation with SSE inline asm constraint.
Create a new X86Int128Union type and use the vector type for
all SSE register inputs and outputs.
Tested-by: Peter Maydell
Signed-off-by: Richard Henderson
---
host/include/x8
u.git tags/pull-tcg-20230620
for you to fetch changes up to d7ee93e24359703debf4137f4cc632563aa4e8d1:
cputlb: Restrict SavedIOTLB to system emulation (2023-06-20 10:02:14 +0200)
tcg: Define _CALL_AIX for clang on ppc64
accel/tcg: Bui
From: Philippe Mathieu-Daudé
Since we *might* have user emulation with softmmu,
replace the system emulation check by !user emulation one.
Invert some if() ladders for clarity.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20230613133347.82210-7-phi...@lina
From: Philippe Mathieu-Daudé
We don't build any user emulation target for Tricore,
only the system emulation. No need to check for it as
it is always defined.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Bastian Koppelmann
Message-Id: <20230613133347.82210
From: Philippe Mathieu-Daudé
Since we *might* have user emulation with softmmu,
replace the system emulation check by !user emulation one.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Nicholas Piggin
Message-Id: <20230613133347.82210-5-phi...@linaro.org>
S
From: Philippe Mathieu-Daudé
Since we *might* have user emulation with softmmu,
use the clearer 'CONFIG_SYSTEM_ONLY' key to check
for system emulation.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20230613133347.82210-9-phi...@linaro.org>
Signed-off-by: Ric
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20230611085846.21415-2-phi...@linaro.org>
Signed-off-by: Richard Henderson
---
plugins/core.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/plugins/core.c b/plugins/core.c
index
From: Philippe Mathieu-Daudé
Since we *might* have user emulation with softmmu,
replace the system emulation check by !user emulation one.
Invert the #ifdef'ry in TCGCPUOps structure for clarity.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20230613133347.
After removing the kvmclock_create() stub we restrict
"hw/kvm/clock.h" to x86, the single arch implementing /
using this.
Philippe Mathieu-Daudé (2):
hw/i386: Remove unuseful kvmclock_create() stub
hw/i386: Rename 'hw/kvm/clock.h' -> 'hw/i386/kvm/clock.h'
{include/hw => hw/i386}/kvm/clock.h
We shouldn't call kvmclock_create() when KVM is not available
or disabled:
- check for kvm_enabled() before calling it
- assert KVM is enabled once called
Since the call is elided when KVM is not available, we can
remove the stub (it is never compiled).
Signed-off-by: Philippe Mathieu-Daudé
---
kvmclock_create() is only implemented in hw/i386/kvm/clock.h.
Restrict the "hw/kvm/clock.h" header to i386 by moving it to
hw/i386/.
Signed-off-by: Philippe Mathieu-Daudé
---
RFC: No other arch had to implement this for 12 years,
safe enough to restrict to x86?
---
{include/hw => hw/i386}/k
Fix arch name in the define that prevents multiple inclusions.
Signed-off-by: Frédéric Pétrot
---
host/include/x86_64/host/atomic128-ldst.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/host/include/x86_64/host/atomic128-ldst.h
b/host/include/x86_64/host/atomic128-ld
On Tue, Jun 20, 2023 at 09:48:02AM +0200, Philippe Mathieu-Daudé wrote:
> Although the PPC target only supports the TCG and KVM
> accelerators, QEMU supports more. We can no assume that
> '!kvm == tcg', so test for the correct accelerator. This
> also eases code review, because here we don't care a
>-Original Message-
>From: Joao Martins
>Sent: Tuesday, June 20, 2023 4:23 PM
>To: Duan, Zhenzhong ; Avihai Horon
>; qemu-devel@nongnu.org
>Cc: alex.william...@redhat.com; c...@redhat.com; Peng, Chao P
>
>Subject: Re: [PATCH v2] vfio/migration: Refactor and fix print of "Migration
>disab
On Tue, 20 Jun 2023 12:48:05 +0530
Ani Sinha wrote:
> When a device has an upstream PCIE port, we can only use slot 0. Non-zero
> slots
> are invalid.
> This change ensures that we throw an error if the user
> tries to hotplug a device with an upstream PCIE port to a non-zero slot.
Isn't the s
On 6/20/23 10:39, Frédéric Pétrot wrote:
Fix arch name in the define that prevents multiple inclusions.
Signed-off-by: Frédéric Pétrot
---
host/include/x86_64/host/atomic128-ldst.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Whoopsie.
Reviewed-by: Richard Henderson
r~
On 6/19/23 17:42, Philippe Mathieu-Daudé wrote:
In order to restrict lookup_cp_reg() and set_rmode() helpers
to VFP translation, un-inline gen_lookup_cp_reg and gen_set /
gen_restore_rmode.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/tcg/translate.h | 22 +++---
On 6/20/23 07:59, Cédric Le Goater wrote:
When the Timer Control and Timer Status registers are modified, avoid
calling the KVM backend when not available
Signed-off-by: Cédric Le Goater
---
target/ppc/kvm.c | 12
1 file changed, 12 insertions(+)
diff --git a/target/ppc/kvm.c b
On 6/20/23 07:59, Cédric Le Goater wrote:
Fred and Nick have been hacking baremetal POWER systems (OPAL) for
many years. They use and modify the QEMU models regularly. Add them as
PowerNV reviewers.
Cc: Frédéric Barrat
Cc: Nicholas Piggin
Signed-off-by: Cédric Le Goater
---
MAINTAINERS | 2 ++
On 6/20/23 07:59, Cédric Le Goater wrote:
Nick has great knowledge of the PowerPC CPUs, software and hardware.
Add him as a reviewer on CPU TCG modeling.
Cc: Nicholas Piggin
Signed-off-by: Cédric Le Goater
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Richard Henderson
On 6/20/23 07:59, Cédric Le Goater wrote:
Fred discusses frequently with the IBM HW designers, he is fluent in
XIVE logic, add him as a reviewer.
Cc: Frédéric Barrat
Signed-off-by: Cédric Le Goater
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Richard Henderson
r~
On 6/20/23 07:59, Cédric Le Goater wrote:
The 'sam460ex' machine never supported KVM. This piece of code was
inherited from another model.
Cc: BALATON Zoltan
Signed-off-by: Cédric Le Goater
---
hw/ppc/sam460ex.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
Reviewed-
On 6/20/23 07:59, Cédric Le Goater wrote:
The 'prep' machine never supported KVM. This piece of code was
probably inherited from another model.
Cc: Hervé Poussineau
Signed-off-by: Cédric Le Goater
---
hw/ppc/prep.c | 20 +++-
1 file changed, 7 insertions(+), 13 deletions(-)
On 6/20/23 07:59, Cédric Le Goater wrote:
The 'pegasos2' machine never supported KVM. This piece of code was
inherited from another model.
Cc: BALATON Zoltan
Signed-off-by: Cédric Le Goater
---
hw/ppc/pegasos2.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
Reviewed-by: Richar
On 6/20/23 07:59, Cédric Le Goater wrote:
The 'bamboo' machine was used as a KVM platform in the early days (~2008).
It clearly doesn't support it anymore.
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc440_bamboo.c | 17 ++---
1 file changed, 6 insertions(+), 11 deletions(-)
Rev
On 6/20/23 07:59, Cédric Le Goater wrote:
Signed-off-by: Cédric Le Goater
---
hw/ppc/pnv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
Hi Gerd Hoffmann
On 2023/6/19 20:51, Gerd Hoffmann wrote:
> Hi,
>> Adding a new command requires new feature flag (and maybe it should be in
>> the <0x1000 range instead)
>>
>> But I am not sure we need a new message at the virtio-gpu level. Gerd, wdyt?
>>
>> Maybe it's not a good place to rese
On Sun, Jun 11, 2023 at 01:47:51AM +0200, Henrik Carlqvist wrote:
> I have now changed the patch to instead use
>
> -global escc.chnA-sunkbd-layout=
>
> and documented in docs/system/keyboard.rst which I have linked from
> target-sparc.rst. Unfortunately, I am not very used to these .rst files
>
On 6/5/23 16:53, Nicholas Piggin wrote:
PPC TCG now supports multi-threaded CPU configuration for non-hypervisor
state. This requires PIR and TIR be set, because that's how sibling thread
matching is done.
spapr's nested-HV capability does not currently coexist with SMT. This
is quite analogo
On 20/06/2023 09:55, Duan, Zhenzhong wrote:
>> -Original Message-
>> From: Joao Martins
>> Sent: Tuesday, June 20, 2023 4:23 PM
>> To: Duan, Zhenzhong ; Avihai Horon
>> ; qemu-devel@nongnu.org
>> Cc: alex.william...@redhat.com; c...@redhat.com; Peng, Chao P
>>
>> Subject: Re: [PATCH v2] v
This patch includes:
- XVADDI.{B/H/W/D}U;
- XVSUBI.{B/H/W/D}U.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 14
target/loongarch/insn_trans/trans_lasx.c.inc | 37
target/loongarch/insns.decode| 12 ++-
3 files change
Signed-off-by: Song Gao
---
target/loongarch/insn_trans/trans_lasx.c.inc | 6 ++
target/loongarch/lasx_helper.c | 6 ++
target/loongarch/meson.build | 1 +
target/loongarch/translate.c | 1 +
4 files changed, 14 insertions(+)
create mode 1006
This patch includes:
- XVADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- XVSUBW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- XVADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 43 ++
target/loongarch/helper.h| 45 ++
target/loongar
This patch includes:
- XVEXTH.{H.B/W.H/D.W/Q.D};
- XVEXTH.{HU.BU/WU.HU/DU.WU/QU.DU}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 9 +
target/loongarch/helper.h| 9 +
target/loongarch/insn_trans/trans_lasx.c.inc | 20 ++
target/
Hi,
This series adds LoongArch LASX instructions.
About test:
We use RISU test the LoongArch LASX instructions.
QEMU:
https://github.com/loongson/qemu/tree/tcg-old-abi-support-lasx
RISU:
https://github.com/loongson/risu/tree/loongarch-suport-lasx
Please review, Thanks.
Song Gao (46):
This patch includes:
- XVSADD.{B/H/W/D}[U];
- XVSSUB.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 17 +
target/loongarch/insn_trans/trans_lasx.c.inc | 17 +
target/loongarch/insns.decode| 18 +
This patch includes:
- XVSIGNCOV.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 5 +++
target/loongarch/helper.h| 5 +++
target/loongarch/insn_trans/trans_lasx.c.inc | 41
target/loongarch/insns.decode
This patch includes:
- XVMSKLTZ.{B/H/W/D};
- XVMSKGEZ.B;
- XVMSKNZ.B.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 7 ++
target/loongarch/helper.h| 7 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 7 ++
target/loongarch/insns.decode
This patch includes:
- XVFRSTP[I].{B/H}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 5 ++
target/loongarch/helper.h| 5 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 5 ++
target/loongarch/insns.decode| 5 ++
target/loon
This patch includes:
- XVAVG.{B/H/W/D/}[U];
- XVAVGR.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 17 ++
target/loongarch/helper.h| 18 +++
target/loongarch/insn_trans/trans_lasx.c.inc | 162 +++
target/loongarch/i
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 2 ++
target/loongarch/cpu.h | 2 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 10 ++
3 files changed, 14 insertions(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
ind
This patch includes:
- XVBITCLR[I].{B/H/W/D};
- XVBITSET[I].{B/H/W/D};
- XVBITREV[I].{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 25 ++
target/loongarch/helper.h| 27 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 246 +++
This patch includes:
- XVFCVT{L/H}.{S.H/D.S};
- XVFCVT.{H.S/S.D};
- XVFRINT[{RNE/RZ/RP/RM}].{S/D};
- XVFTINT[{RNE/RZ/RP/RM}].{W.S/L.D};
- XVFTINT[RZ].{WU.S/LU.D};
- XVFTINT[{RNE/RZ/RP/RM}].W.D;
- XVFTINT[{RNE/RZ/RP/RM}]{L/H}.L.S;
- XVFFINT.{S.W/D.L}[U];
- X[CVFFINT.S.L, VFFINT{L/H}.D.W.
Signed-off
This patch includes:
- XVSRLRN.{B.H/H.W/W.D};
- XVSRARN.{B.H/H.W/W.D};
- XVSRLRNI.{B.H/H.W/W.D/D.Q};
- XVSRARNI.{B.H/H.W/W.D/D.Q}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 16 ++
target/loongarch/helper.h| 16 ++
target/loongarch/insn_trans
This patch includes:
- XVDIV.{B/H/W/D}[U];
- XVMOD.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 17 +++
target/loongarch/helper.h| 17 +++
target/loongarch/insn_trans/trans_lasx.c.inc | 17 +++
target/loongar
This patch includes:
- XVNEG.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 10 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 20
target/loongarch/insns.decode| 7 +++
3 files changed, 37 insertions(+)
This patch includes:
- XVFCMP.cond.{S/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 94
target/loongarch/helper.h| 5 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 32 +++
target/loongarch/insns.decode
This patch includes:
- XVF{ADD/SUB/MUL/DIV}.{S/D};
- XVF{MADD/MSUB/NMADD/NMSUB}.{S/D};
- XVF{MAX/MIN}.{S/D};
- XVF{MAXA/MINA}.{S/D};
- XVFLOGB.{S/D};
- XVFCLASS.{S/D};
- XVF{SQRT/RECIP/RSQRT}.{S/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 46 +
target/l
This patch includes:
- XVADD.{B/H/W/D/Q};
- XVSUB.{B/H/W/D/Q}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 23
target/loongarch/insn_trans/trans_lasx.c.inc | 59
target/loongarch/insns.decode| 23
target/loonga
This patch includes:
- XVCLO.{B/H/W/D};
- XVCLZ.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 9 +
target/loongarch/helper.h| 9 +
target/loongarch/insn_trans/trans_lasx.c.inc | 9 +
target/loongarch/insns.dec
Signed-off-by: Song Gao
---
linux-user/loongarch64/signal.c | 1 +
target/loongarch/cpu.c | 1 +
target/loongarch/cpu.h | 14 +
target/loongarch/gdbstub.c | 1 +
target/loongarch/internals.h| 22 --
target/loongarch/lsx_helper.c | 1 +
target/l
This patch includes:
- XVSSRLRN.{B.H/H.W/W.D};
- XVSSRARN.{B.H/H.W/W.D};
- XVSSRLRN.{BU.H/HU.W/WU.D};
- XVSSRARN.{BU.H/HU.W/WU.D};
- XVSSRLRNI.{B.H/H.W/W.D/D.Q};
- XVSSRARNI.{B.H/H.W/W.D/D.Q};
- XVSSRLRNI.{BU.H/HU.W/WU.D/DU.Q};
- XVSSRARNI.{BU.H/HU.W/WU.D/DU.Q}.
Signed-off-by: Song Gao
---
targe
This patch includes:
- XVREPLGR2VR.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 10 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 16
target/loongarch/insns.decode| 8
3 files changed, 34 insertions(+
This patch includes:
- XVADDA.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 5 +++
target/loongarch/helper.h| 5 +++
target/loongarch/insn_trans/trans_lasx.c.inc | 41
target/loongarch/insns.decode
This patch includes:
- XVMADD.{B/H/W/D};
- XVMSUB.{B/H/W/D};
- XVMADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- XVMADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 34 ++
target/loongarch/helper.h| 30 ++
target/loo
This patch includes:
- VEXT2XV.{H/W/D}.B, VEXT2XV.{HU/WU/DU}.BU;
- VEXT2XV.{W/D}.B, VEXT2XV.{WU/DU}.HU;
- VEXT2XV.D.W, VEXT2XV.DU.WU.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 13 ++
target/loongarch/helper.h| 13 ++
target/loo
This patch includes:
- XVREPLVE.{B/H/W/D};
- XVREPL128VEI.{B/H/W/D};
- XVREPLVE0.{B/H/W/D/Q};
- XVINSVE0.{W/D};
- XVPICKVE.{W/D};
- XVBSLL.V, XVBSRL.V.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 29 +++
target/loongarch/helper.h| 5 +
target
This patch includes:
- XVPACK{EV/OD}.{B/H/W/D};
- XVPICK{EV/OD}.{B/H/W/D};
- XVILV{L/H}.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 27
target/loongarch/helper.h| 27
target/loongarch/insn_trans/trans_lasx.c.inc | 27
This patch includes:
- XVSLLWIL.{H.B/W.H/D.W};
- XVSLLWIL.{HU.BU/WU.HU/DU.WU};
- XVEXTL.Q.D, VEXTL.QU.DU.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 9
target/loongarch/helper.h| 9
target/loongarch/insn_trans/trans_lasx.c.inc | 21
On Tue Jun 20, 2023 at 3:59 PM AEST, Cédric Le Goater wrote:
> Fred and Nick have been hacking baremetal POWER systems (OPAL) for
> many years. They use and modify the QEMU models regularly. Add them as
> PowerNV reviewers.
>
Reviewed-by: Nicholas Piggin
> Cc: Frédéric Barrat
> Cc: Nicholas Pig
This patch includes:
- XV{AND/OR/XOR/NOR/ANDN/ORN}.V;
- XV{AND/OR/XOR/NOR}I.B.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 12 ++
target/loongarch/helper.h| 2 +
target/loongarch/insn_trans/trans_lasx.c.inc | 42
target
This patch includes:
- XVSEQ[I].{B/H/W/D};
- XVSLE[I].{B/H/W/D}[U];
- XVSLT[I].{B/H/W/D/}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 43 ++
target/loongarch/helper.h| 23 +++
target/loongarch/insn_trans/trans_lasx.c.inc | 154
This patch includes:
- XVMAX[I].{B/H/W/D}[U];
- XVMIN[I].{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 33
target/loongarch/helper.h| 18 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 180 +++
target/loonga
This patch includes:
- XVSRLR[I].{B/H/W/D};
- XVSRAR[I].{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 18
target/loongarch/helper.h| 18
target/loongarch/insn_trans/trans_lasx.c.inc | 18
target/loongarch/insns.decode
This patch includes:
- XVBITSEL.V;
- XVBITSELI.B;
- XVSET{EQZ/NEZ}.V;
- XVSETANYEQZ.{B/H/W/D};
- XVSETALLNEZ.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 19 +
target/loongarch/helper.h| 11 +++
target/loongarch/insn_trans/trans_la
This patch includes:
- XVSLL[I].{B/H/W/D};
- XVSRL[I].{B/H/W/D};
- XVSRA[I].{B/H/W/D};
- XVROTR[I].{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 36
target/loongarch/insn_trans/trans_lasx.c.inc | 36
target/loongar
This patch includes:
- XVSSRLN.{B.H/H.W/W.D};
- XVSSRAN.{B.H/H.W/W.D};
- XVSSRLN.{BU.H/HU.W/WU.D};
- XVSSRAN.{BU.H/HU.W/WU.D};
- XVSSRLNI.{B.H/H.W/W.D/D.Q};
- XVSSRANI.{B.H/H.W/W.D/D.Q};
- XVSSRLNI.{BU.H/HU.W/WU.D/DU.Q};
- XVSSRANI.{BU.H/HU.W/WU.D/DU.Q}.
Signed-off-by: Song Gao
---
target/loonga
This patch includes:
- XVHADDW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU};
- XVHSUBW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 17
target/loongarch/helper.h| 18
target/loongarch/insn_trans/t
This patch includes:
- XVABSD.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 9 +++
target/loongarch/helper.h| 9 +++
target/loongarch/insn_trans/trans_lasx.c.inc | 81
target/loongarch/insns.decode
This patch includes:
- XVLDI.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 7 +++
target/loongarch/insn_trans/trans_lasx.c.inc | 21
target/loongarch/insns.decode| 5 -
3 files changed, 32 insertions(+), 1 deletion(-)
This patch includes:
- XVSRLN.{B.H/H.W/W.D};
- XVSRAN.{B.H/H.W/W.D};
- XVSRLNI.{B.H/H.W/W.D/D.Q};
- XVSRANI.{B.H/H.W/W.D/D.Q}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 16 +++
target/loongarch/helper.h| 16 +++
target/loongarch/insn_trans/t
This patch includes:
- XVINSGR2VR.{W/D};
- XVPICKVE2GR.{W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 17 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 54
target/loongarch/insns.decode| 13 +
3 files changed,
Hi,
> > The guest driver should be able to restore resources after resume.
>
> Thank you for your suggestion!
> As far as I know, resources are created on host side and guest has no backup,
> if resources are destroyed, guest can't restore them.
> Or do you mean guest driver need to send comma
On Tue Jun 20, 2023 at 3:59 PM AEST, Cédric Le Goater wrote:
> Nick has great knowledge of the PowerPC CPUs, software and hardware.
> Add him as a reviewer on CPU TCG modeling.
Reviewed-by: Nicholas Piggin
>
> Cc: Nicholas Piggin
> Signed-off-by: Cédric Le Goater
> ---
> MAINTAINERS | 1 +
>
On Tue Jun 20, 2023 at 7:27 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 6/5/23 16:53, Nicholas Piggin wrote:
> > PPC TCG now supports multi-threaded CPU configuration for non-hypervisor
> > state. This requires PIR and TIR be set, because that's how sibling thread
> > matching is done.
> >
> > spa
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index c9f9cbb19d..aeccbb42e6 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -392,6 +392,7 @@ static void loongarch_la464_init
This patch includes:
- XVLD[X], XVST[X];
- XVLDREPL.{B/H/W/D};
- XVSTELM.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 24 +
target/loongarch/helper.h| 3 +
target/loongarch/insn_trans/trans_lasx.c.inc | 97
ta
This patch includes:
- XVMUL.{B/H/W/D};
- XVMUH.{B/H/W/D}[U];
- XVMULW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- XVMULW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 38 +++
target/loongarch/helper.h| 30 ++
target/loo
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