On Tue Jun 20, 2023 at 7:27 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 6/5/23 16:53, Nicholas Piggin wrote:
> > PPC TCG now supports multi-threaded CPU configuration for non-hypervisor
> > state. This requires PIR and TIR be set, because that's how sibling thread
> > matching is done.
> >
> > spapr's nested-HV capability does not currently coexist with SMT. This
> > is quite analogous to LPAR-per-core mode on real hardware which also
> > does not support KVM.
> >
> > Signed-off-by: Nicholas Piggin <npig...@gmail.com>
> > ---
> > hw/ppc/spapr.c | 16 ++++++++++++----
> > hw/ppc/spapr_caps.c | 14 ++++++++++++++
> > hw/ppc/spapr_cpu_core.c | 7 +++++--
> > 3 files changed, 31 insertions(+), 6 deletions(-)
> >
> > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> > index dcb7f1c70a..deb8b507e3 100644
> > --- a/hw/ppc/spapr.c
> > +++ b/hw/ppc/spapr.c
> > @@ -2524,10 +2524,18 @@ static void spapr_set_vsmt_mode(SpaprMachineState
> > *spapr, Error **errp)
> > int ret;
> > unsigned int smp_threads = ms->smp.threads;
> >
> > - if (!kvm_enabled() && (smp_threads > 1)) {
> > - error_setg(errp, "TCG cannot support more than 1 thread/core "
> > - "on a pseries machine");
> > - return;
> > + if (!kvm_enabled()) {
>
> Can we make it a check for tcg_enabled() which would be more appropriate
> or as Cedric suggested, may be include this one along with your series:
>
> https://lore.kernel.org/qemu-devel/20230620074802.86898-1-phi...@linaro.org/
Good point, I'll keep it in mind.
Thanks,
Nick
